|
version 1.1, 2003/12/08 00:55:31
|
version 1.20, 2005/03/12 12:32:54
|
|
Line 12
|
Line 12
|
| * 2. Redistributions in binary form must reproduce the above copyright |
* 2. Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
* notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
* documentation and/or other materials provided with the distribution. |
| * 3. The name of the author may not be used to endorse or promote products |
|
| * derived from this software without specific prior written permission. |
|
| * |
* |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
|
Line 34
|
Line 32
|
| extern "C" { |
extern "C" { |
| #endif |
#endif |
| |
|
| /* enter/leave paging mode */ |
/* |
| void FASTCALL change_pg(int onoff); |
* ページ・ディレクトリ・エントリ (4K バイトページ使用時) |
| |
* |
| |
* 31 12 11 9 8 7 6 5 4 3 2 1 0 |
| |
* +----------------------------------------+------+-+--+-+-+---+---+---+---+-+ |
| |
* | ページ・テーブルのベース・アドレス |使用可|G|PS|-|A|PCD|PWT|U/S|R/W|P| |
| |
* +----------------------------------------+------+-+--+-+-+---+---+---+---+-+ |
| |
* | | | | | | | | | | |
| |
* 9-11: システム・プログラマが使用可能 --------+ | | | | | | | | | |
| |
* 8: グローバル・ページ(無視される) ------------+ | | | | | | | | |
| |
* 7: ページ・サイズ (0 = 4k バイトページ) ---------+ | | | | | | | |
| |
* 6: 予約 (-) ---------------------------------------+ | | | | | | |
| |
* 5: アクセス -----------------------------------------+ | | | | | |
| |
* 4: キャッシュ無効 --------------------------------------+ | | | | |
| |
* 3: ライトスルー --------------------------------------------+ | | | |
| |
* 2: ユーザ／スーパバイザ (0 = スーパバイザ) ---------------------+ | | |
| |
* 1: 読み取り／書き込み (0 = 読み取りのみ) ---------------------------+ | |
| |
* 0: ページ存在 ---------------------------------------------------------+ |
| |
*/ |
| |
#define CPU_PDE_BASEADDR_MASK 0xfffff000 |
| |
#define CPU_PDE_GLOBAL_PAGE (1 << 8) |
| |
#define CPU_PDE_PAGE_SIZE (1 << 7) |
| |
#define CPU_PDE_DIRTY (1 << 6) |
| |
#define CPU_PDE_ACCESS (1 << 5) |
| |
#define CPU_PDE_CACHE_DISABLE (1 << 4) |
| |
#define CPU_PDE_WRITE_THROUGH (1 << 3) |
| |
#define CPU_PDE_USER_MODE (1 << 2) |
| |
#define CPU_PDE_WRITABLE (1 << 1) |
| |
#define CPU_PDE_PRESENT (1 << 0) |
| |
|
| |
/* |
| |
* ページ・ディレクトリ・エントリ (4M バイトページ使用時) |
| |
* |
| |
* 31 22 21 12 11 9 8 7 6 5 4 3 2 1 0 |
| |
* +----------------------------+-----------+------+-+--+-+-+---+---+---+---+-+ |
| |
* |ページテーブルの物理アドレス| 予約済み |使用可|G|PS|D|A|PCD|PWT|U/S|R/W|P| |
| |
* +----------------------------+-----------+------+-+--+-+-+---+---+---+---+-+ |
| |
* | | | | | | | | | | |
| |
* 9-11: システム・プログラマが使用可能 --------+ | | | | | | | | | |
| |
* 8: グローバル・ページ ------------------------+ | | | | | | | | |
| |
* 7: ページ・サイズ (1 = 4M バイトページ) ---------+ | | | | | | | |
| |
* 6: ダーティ ---------------------------------------+ | | | | | | |
| |
* 5: アクセス -----------------------------------------+ | | | | | |
| |
* 4: キャッシュ無効 --------------------------------------+ | | | | |
| |
* 3: ライトスルー --------------------------------------------+ | | | |
| |
* 2: ユーザ／スーパバイザ (0 = スーパバイザ) ---------------------+ | | |
| |
* 1: 読み取り／書き込み (0 = 読み取りのみ) ---------------------------+ | |
| |
* 0: ページ存在 ---------------------------------------------------------+ |
| |
*/ |
| |
#define CPU_PDE_4M_BASEADDR_MASK 0xffc00000 |
| |
#define CPU_PDE_4M_GLOBAL_PAGE (1 << 8) |
| |
#define CPU_PDE_4M_PAGE_SIZE (1 << 7) |
| |
#define CPU_PDE_4M_DIRTY (1 << 6) |
| |
#define CPU_PDE_4M_ACCESS (1 << 5) |
| |
#define CPU_PDE_4M_CACHE_DISABLE (1 << 4) |
| |
#define CPU_PDE_4M_WRITE_THROUGH (1 << 3) |
| |
#define CPU_PDE_4M_USER_MODE (1 << 2) |
| |
#define CPU_PDE_4M_WRITABLE (1 << 1) |
| |
#define CPU_PDE_4M_PRESENT (1 << 0) |
| |
|
| /* paging check */ |
/* |
| void MEMCALL paging_check(DWORD laddr, DWORD length, int rw); |
* ページ・テーブル・エントリ (4k バイト・ページ) |
| |
* |
| |
* 31 12 11 9 8 7 6 5 4 3 2 1 0 |
| |
* +----------------------------------------+------+-+-+-+-+---+---+---+---+-+ |
| |
* | ページのベース・アドレス |使用可|G|-|D|A|PCD|PWT|U/S|R/W|P| |
| |
* +----------------------------------------+------+-+-+-+-+---+---+---+---+-+ |
| |
* | | | | | | | | | | |
| |
* 9-11: システム・プログラマが使用可能 -------+ | | | | | | | | | |
| |
* 8: グローバル・ページ -----------------------+ | | | | | | | | |
| |
* 7: 予約 (-) -----------------------------------+ | | | | | | | |
| |
* 6: ダーティ -------------------------------------+ | | | | | | |
| |
* 5: アクセス ---------------------------------------+ | | | | | |
| |
* 4: キャッシュ無効 ------------------------------------+ | | | | |
| |
* 3: ライトスルー ------------------------------------------+ | | | |
| |
* 2: ユーザ／スーパバイザ (0 = スーパバイザ) -------------------+ | | |
| |
* 1: 読み取り／書き込み (0 = 読み取りのみ) -------------------------+ | |
| |
* 0: ページ存在 -------------------------------------------------------+ |
| |
*/ |
| |
#define CPU_PTE_BASEADDR_MASK 0xfffff000 |
| |
#define CPU_PTE_GLOBAL_PAGE (1 << 8) |
| |
#define CPU_PTE_PAGE_SIZE (1 << 7) |
| |
#define CPU_PTE_DIRTY (1 << 6) |
| |
#define CPU_PTE_ACCESS (1 << 5) |
| |
#define CPU_PTE_CACHE_DISABLE (1 << 4) |
| |
#define CPU_PTE_WRITE_THROUGH (1 << 3) |
| |
#define CPU_PTE_USER_MODE (1 << 2) |
| |
#define CPU_PTE_WRITABLE (1 << 1) |
| |
#define CPU_PTE_PRESENT (1 << 0) |
| |
|
| |
|
| |
/* |
| |
* linear address memory access function |
| |
*/ |
| |
void MEMCALL cpu_memory_access_la_region(UINT32 address, UINT length, const int ucrw, BYTE *data); |
| |
void MEMCALL paging_check(UINT32 laddr, UINT length, const int ucrw); |
| |
|
| |
/* ucrw */ |
| |
#define CPU_PAGE_WRITE (1 << 0) |
| |
#define CPU_PAGE_CODE (1 << 1) |
| |
#define CPU_PAGE_DATA (1 << 2) |
| |
#define CPU_PAGE_USER_MODE (1 << 3) /* == CPU_MODE_USER */ |
| |
#define CPU_PAGE_READ_CODE (CPU_PAGE_CODE) |
| |
#define CPU_PAGE_READ_DATA (CPU_PAGE_DATA) |
| |
#define CPU_PAGE_WRITE_DATA (CPU_PAGE_WRITE|CPU_PAGE_DATA) |
| |
|
| |
UINT8 MEMCALL cpu_memory_access_la_RMW_b(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg) GCC_ATTR_REGPARM; |
| |
UINT16 MEMCALL cpu_memory_access_la_RMW_w(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg) GCC_ATTR_REGPARM; |
| |
UINT32 MEMCALL cpu_memory_access_la_RMW_d(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg) GCC_ATTR_REGPARM; |
| |
UINT8 MEMCALL cpu_linear_memory_read_b(UINT32 laddr, const int ucrw) GCC_ATTR_REGPARM; |
| |
UINT16 MEMCALL cpu_linear_memory_read_w(UINT32 laddr, const int ucrw) GCC_ATTR_REGPARM; |
| |
UINT32 MEMCALL cpu_linear_memory_read_d(UINT32 laddr, const int ucrw) GCC_ATTR_REGPARM; |
| |
UINT64 MEMCALL cpu_linear_memory_read_q(UINT32 laddr, const int ucrw) GCC_ATTR_REGPARM; |
| |
REG80 MEMCALL cpu_linear_memory_read_f(UINT32 laddr, const int ucrw) GCC_ATTR_REGPARM; |
| |
void MEMCALL cpu_linear_memory_write_b(UINT32 laddr, UINT8 value, const int user_mode) GCC_ATTR_REGPARM; |
| |
void MEMCALL cpu_linear_memory_write_w(UINT32 laddr, UINT16 value, const int user_mode) GCC_ATTR_REGPARM; |
| |
void MEMCALL cpu_linear_memory_write_d(UINT32 laddr, UINT32 value, const int user_mode) GCC_ATTR_REGPARM; |
| |
void MEMCALL cpu_linear_memory_write_q(UINT32 laddr, UINT64 value, const int user_mode) GCC_ATTR_REGPARM; |
| |
void MEMCALL cpu_linear_memory_write_f(UINT32 laddr, const REG80 *value, const int user_mode) GCC_ATTR_REGPARM; |
| |
|
| |
#define cpu_lmemoryread(a,pl) \ |
| |
(!CPU_STAT_PAGING) ? \ |
| |
cpu_memoryread(a) : \ |
| |
cpu_linear_memory_read_b(a,CPU_PAGE_READ_DATA | (pl)) |
| |
#define cpu_lmemoryread_b(a,pl) cpu_lmemoryread(a,pl) |
| |
#define cpu_lmemoryread_w(a,pl) \ |
| |
(!CPU_STAT_PAGING) ? \ |
| |
cpu_memoryread_w(a) : \ |
| |
cpu_linear_memory_read_w(a,CPU_PAGE_READ_DATA | (pl)) |
| |
#define cpu_lmemoryread_d(a,pl) \ |
| |
(!CPU_STAT_PAGING) ? \ |
| |
cpu_memoryread_d(a) : \ |
| |
cpu_linear_memory_read_d(a,CPU_PAGE_READ_DATA | (pl)) |
| |
#define cpu_lmemoryread_q(a,pl) \ |
| |
(!CPU_STAT_PAGING) ? \ |
| |
cpu_memoryread_q(a) : \ |
| |
cpu_linear_memory_read_q(a,CPU_PAGE_READ_DATA | (pl)) |
| |
|
| |
#define cpu_lmemorywrite(a,v,pl) \ |
| |
(!CPU_STAT_PAGING) ? \ |
| |
cpu_memorywrite(a,v) : cpu_linear_memory_write_b(a,v,pl) |
| |
#define cpu_lmemorywrite_b(a,v,pl) cpu_lmemorywrite(a,v,pl) |
| |
#define cpu_lmemorywrite_w(a,v,pl) \ |
| |
(!CPU_STAT_PAGING) ? \ |
| |
cpu_memorywrite_w(a,v) : cpu_linear_memory_write_w(a,v,pl) |
| |
#define cpu_lmemorywrite_d(a,v,pl) \ |
| |
(!CPU_STAT_PAGING) ? \ |
| |
cpu_memorywrite_d(a,v) : cpu_linear_memory_write_d(a,v,pl) |
| |
#define cpu_lmemorywrite_q(a,v,pl) \ |
| |
(!CPU_STAT_PAGING) ? \ |
| |
cpu_memorywrite_q(a,v) : cpu_linear_memory_write_q(a,v,pl) |
| |
|
| |
/* |
| |
* linear address memory access with superviser mode |
| |
*/ |
| |
#define cpu_kmemoryread(a) cpu_lmemoryread(a,CPU_MODE_SUPERVISER) |
| |
#define cpu_kmemoryread_w(a) cpu_lmemoryread_w(a,CPU_MODE_SUPERVISER) |
| |
#define cpu_kmemoryread_d(a) cpu_lmemoryread_d(a,CPU_MODE_SUPERVISER) |
| |
#define cpu_kmemorywrite(a,v) cpu_lmemorywrite(a,v,CPU_MODE_SUPERVISER) |
| |
#define cpu_kmemorywrite_w(a,v) cpu_lmemorywrite_w(a,v,CPU_MODE_SUPERVISER) |
| |
#define cpu_kmemorywrite_d(a,v) cpu_lmemorywrite_d(a,v,CPU_MODE_SUPERVISER) |
| |
|
| |
|
| |
/* |
| |
* CR3 (Page Directory Entry base physical address) |
| |
*/ |
| |
#define set_CR3(cr3) \ |
| |
do { \ |
| |
VERBOSE(("set_CR3: old = %08x, new = 0x%08x", CPU_CR3, (cr3) & CPU_CR3_MASK)); \ |
| |
CPU_CR3 = (cr3) & CPU_CR3_MASK; \ |
| |
CPU_STAT_PDE_BASE = CPU_CR3 & CPU_CR3_PD_MASK; \ |
| |
tlb_flush(FALSE); \ |
| |
} while (/*CONSTCOND*/ 0) |
| |
|
| /* paging_check(): rw */ |
|
| #define CPU_PAGING_PAGE_READ (0 << 0) |
|
| #define CPU_PAGING_PAGE_WRITE (1 << 0) |
|
| |
|
| /* |
|
| * linear address function |
|
| */ |
|
| DWORD MEMCALL cpu_linear_memory_read(DWORD address, DWORD length, int code); |
|
| void MEMCALL cpu_linear_memory_write(DWORD address, DWORD length, DWORD value); |
|
| |
|
| /* cpu_linear_memory_read(): code */ |
|
| #define CPU_PAGING_PAGE_CODE (1 << 1) |
|
| #define CPU_PAGING_PAGE_DATA (1 << 2) |
|
| |
|
| #define cpu_lmemoryread(a) \ |
|
| (CPU_STAT_PAGING) ? \ |
|
| (BYTE)cpu_linear_memory_read(a, 1, FALSE) : \ |
|
| cpu_memoryread(a); |
|
| #define cpu_lmemoryread_w(a) \ |
|
| (CPU_STAT_PAGING) ? \ |
|
| (WORD)cpu_linear_memory_read(a, 2, FALSE) : \ |
|
| cpu_memoryread_w(a); |
|
| #define cpu_lmemoryread_d(a) \ |
|
| (CPU_STAT_PAGING) ? \ |
|
| cpu_linear_memory_read(a, 4, FALSE) : \ |
|
| cpu_memoryread_d(a); |
|
| |
|
| #define cpu_lmemorywrite(a,v) \ |
|
| (CPU_STAT_PAGING) ? \ |
|
| cpu_linear_memory_write(a, 1, v) : \ |
|
| cpu_memorywrite(a,v); |
|
| #define cpu_lmemorywrite_w(a,v) \ |
|
| (CPU_STAT_PAGING) ? \ |
|
| cpu_linear_memory_write(a, 2, v) : \ |
|
| cpu_memorywrite_w(a,v); |
|
| #define cpu_lmemorywrite_d(a,v) \ |
|
| (CPU_STAT_PAGING) ? \ |
|
| cpu_linear_memory_write(a, 4, v) : \ |
|
| cpu_memorywrite_d(a,v); |
|
| |
|
| #define cpu_lcmemoryread(a) \ |
|
| (CPU_STAT_PAGING) ? \ |
|
| (BYTE)cpu_linear_memory_read(a, 1, TRUE) : \ |
|
| cpu_memoryread(a); |
|
| #define cpu_lcmemoryread_w(a) \ |
|
| (CPU_STAT_PAGING) ? \ |
|
| (WORD)cpu_linear_memory_read(a, 2, TRUE) : \ |
|
| cpu_memoryread_w(a); |
|
| #define cpu_lcmemoryread_d(a) \ |
|
| (CPU_STAT_PAGING) ? \ |
|
| cpu_linear_memory_read(a, 4, TRUE) : \ |
|
| cpu_memoryread_d(a); |
|
| |
|
| /* |
/* |
| * TLB function |
* TLB function |
| */ |
*/ |
| void tlb_init(); |
typedef struct { |
| void tlb_flush(BOOL allflush); |
UINT32 tag; /* linear address */ |
| void tlb_flush_page(DWORD vaddr); |
#define TLB_ENTRY_TAG_VALID (1 << 0) |
| |
/* pde & pte & CPU_PTE_WRITABLE (1 << 1) */ |
| |
/* pde & pte & CPU_PTE_USER_MODE (1 << 2) */ |
| |
#define TLB_ENTRY_TAG_DIRTY CPU_PTE_DIRTY /* (1 << 6) */ |
| |
#define TLB_ENTRY_TAG_GLOBAL CPU_PTE_GLOBAL_PAGE /* (1 << 8) */ |
| |
#define TLB_ENTRY_TAG_MAX_SHIFT 12 |
| |
|
| |
UINT32 paddr; /* physical address */ |
| |
|
| |
UINT8 *memp; /* shortcut for pre-fetch queue */ |
| |
} TLB_ENTRY_T; |
| |
|
| |
|
| |
#if defined(IA32_SUPPORT_TLB) |
| |
void tlb_init(void); |
| |
void MEMCALL tlb_flush(BOOL allflush) GCC_ATTR_REGPARM; |
| |
void MEMCALL tlb_flush_page(UINT32 laddr) GCC_ATTR_REGPARM; |
| |
TLB_ENTRY_T* MEMCALL tlb_lookup(const UINT32 laddr, const int ucrw) GCC_ATTR_REGPARM; |
| |
#else |
| |
#define tlb_init() |
| |
#define tlb_flush(allflush) (void)(allflush) |
| |
#define tlb_flush_page(la) (void)(la) |
| |
#define tlb_lookup(la, ucrw) NULL |
| |
#endif |
| |
|
| #ifdef __cplusplus |
#ifdef __cplusplus |
| } |
} |
| #endif |
#endif |
![[BACK]](/cvs/cvsweb/icons/back.gif){kind=icon}
Return to paging.h CVS log ![[TXT]](/cvs/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvs/cvsweb/icons/dir.gif){kind=icon}
Up to [RetroPC.NET] / np2 / i386c / ia32