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| version 1.8, 2004/02/05 16:43:44 | version 1.12, 2004/03/05 14:17:35 |
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| Line 39 extern "C" { | Line 39 extern "C" { |
| * | * |
| * 31 12 11 9 8 7 6 5 4 3 2 1 0 | * 31 12 11 9 8 7 6 5 4 3 2 1 0 |
| * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+ | * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+ |
| * | ページ・テーブルのベース・アドレス |使用可|G|PS|0|A|PCD|PWT|U/S|R/W|P| | * | ページ・テーブルのベース・アドレス |使用可|G|PS|-|A|PCD|PWT|U/S|R/W|P| |
| * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+ | * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+ |
| * | | | | | | | | | | | * | | | | | | | | | | |
| * 9-11: システム・プログラマが使用可能 --------+ | | | | | | | | | | * 9-11: システム・プログラマが使用可能 --------+ | | | | | | | | | |
| * 8: グローバル・ページ(無視される) ------------+ | | | | | | | | | * 8: グローバル・ページ(無視される) ------------+ | | | | | | | | |
| * 7: ページ・サイズ (0 = 4k バイトページ) ---------+ | | | | | | | | * 7: ページ・サイズ (0 = 4k バイトページ) ---------+ | | | | | | | |
| * 6: 予約 (0) ---------------------------------------+ | | | | | | | * 6: 予約 (-) ---------------------------------------+ | | | | | | |
| * 5: アクセス -----------------------------------------+ | | | | | | * 5: アクセス -----------------------------------------+ | | | | | |
| * 4: キャッシュ無効 --------------------------------------+ | | | | | * 4: キャッシュ無効 --------------------------------------+ | | | | |
| * 3: ライトスルー --------------------------------------------+ | | | | * 3: ライトスルー --------------------------------------------+ | | | |
| Line 54 extern "C" { | Line 54 extern "C" { |
| * 0: ページ存在 ---------------------------------------------------------+ | * 0: ページ存在 ---------------------------------------------------------+ |
| */ | */ |
| #define CPU_PDE_BASEADDR_MASK 0xfffff000 | #define CPU_PDE_BASEADDR_MASK 0xfffff000 |
| #define CPU_PDE_GLOBAL_PAGE (1 << 8) | |
| #define CPU_PDE_PAGE_SIZE (1 << 7) | #define CPU_PDE_PAGE_SIZE (1 << 7) |
| #define CPU_PDE_DIRTY (1 << 6) | |
| #define CPU_PDE_ACCESS (1 << 5) | #define CPU_PDE_ACCESS (1 << 5) |
| #define CPU_PDE_CACHE_DISABLE (1 << 4) | #define CPU_PDE_CACHE_DISABLE (1 << 4) |
| #define CPU_PDE_WRITE_THROUGH (1 << 3) | #define CPU_PDE_WRITE_THROUGH (1 << 3) |
| Line 97 extern "C" { | Line 99 extern "C" { |
| * | * |
| * 31 12 11 9 8 7 6 5 4 3 2 1 0 | * 31 12 11 9 8 7 6 5 4 3 2 1 0 |
| * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+ | * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+ |
| * | ページのベース・アドレス |使用可|G|0|D|A|PCD|PWT|U/S|R/W|P| | * | ページのベース・アドレス |使用可|G|-|D|A|PCD|PWT|U/S|R/W|P| |
| * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+ | * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+ |
| * | | | | | | | | | | | * | | | | | | | | | | |
| * 9-11: システム・プログラマが使用可能 -------+ | | | | | | | | | | * 9-11: システム・プログラマが使用可能 -------+ | | | | | | | | | |
| * 8: グローバル・ページ -----------------------+ | | | | | | | | | * 8: グローバル・ページ -----------------------+ | | | | | | | | |
| * 7: 予約 (0) -----------------------------------+ | | | | | | | | * 7: 予約 (-) -----------------------------------+ | | | | | | | |
| * 6: ダーティ -------------------------------------+ | | | | | | | * 6: ダーティ -------------------------------------+ | | | | | | |
| * 5: アクセス ---------------------------------------+ | | | | | | * 5: アクセス ---------------------------------------+ | | | | | |
| * 4: キャッシュ無効 ------------------------------------+ | | | | | * 4: キャッシュ無効 ------------------------------------+ | | | | |
| Line 113 extern "C" { | Line 115 extern "C" { |
| */ | */ |
| #define CPU_PTE_BASEADDR_MASK 0xfffff000 | #define CPU_PTE_BASEADDR_MASK 0xfffff000 |
| #define CPU_PTE_GLOBAL_PAGE (1 << 8) | #define CPU_PTE_GLOBAL_PAGE (1 << 8) |
| #define CPU_PTE_PAGE_SIZE (1 << 7) | |
| #define CPU_PTE_DIRTY (1 << 6) | #define CPU_PTE_DIRTY (1 << 6) |
| #define CPU_PTE_ACCESS (1 << 5) | #define CPU_PTE_ACCESS (1 << 5) |
| #define CPU_PTE_CACHE_DISABLE (1 << 4) | #define CPU_PTE_CACHE_DISABLE (1 << 4) |
| Line 125 extern "C" { | Line 128 extern "C" { |
| /* | /* |
| * linear address memory access function | * linear address memory access function |
| */ | */ |
| DWORD MEMCALL cpu_linear_memory_read(DWORD address, DWORD length, int code, int user_mode); | void MEMCALL cpu_memory_access_la_region(UINT32 address, UINT length, int crw, int user_mode, BYTE *data); |
| void MEMCALL cpu_linear_memory_write(DWORD address, DWORD value, DWORD length, int user_mode); | UINT32 MEMCALL cpu_linear_memory_read(UINT32 address, UINT length, int crw, int user_mode); |
| void MEMCALL paging_check(DWORD laddr, DWORD length, int crw, int user_mode); | void MEMCALL cpu_linear_memory_write(UINT32 address, UINT32 value, UINT length, int user_mode); |
| void MEMCALL paging_check(UINT32 laddr, UINT length, int crw, int user_mode); | |
| /* crw */ | /* crw */ |
| #define CPU_PAGE_READ (0 << 0) | #define CPU_PAGE_READ (0 << 0) |
| Line 142 void MEMCALL paging_check(DWORD laddr, D | Line 146 void MEMCALL paging_check(DWORD laddr, D |
| #define cpu_lmemoryread(a,pl) \ | #define cpu_lmemoryread(a,pl) \ |
| (!CPU_STAT_PAGING) ? \ | (!CPU_STAT_PAGING) ? \ |
| cpu_memoryread(a) : \ | cpu_memoryread(a) : \ |
| (BYTE)cpu_linear_memory_read(a,1,CPU_PAGE_READ_DATA,pl) | (UINT8)cpu_linear_memory_read(a,1,CPU_PAGE_READ_DATA,pl) |
| #define cpu_lmemoryread_w(a,pl) \ | #define cpu_lmemoryread_w(a,pl) \ |
| (!CPU_STAT_PAGING) ? \ | (!CPU_STAT_PAGING) ? \ |
| cpu_memoryread_w(a) : \ | cpu_memoryread_w(a) : \ |
| (WORD)cpu_linear_memory_read(a,2,CPU_PAGE_READ_DATA,pl) | (UINT16)cpu_linear_memory_read(a,2,CPU_PAGE_READ_DATA,pl) |
| #define cpu_lmemoryread_d(a,pl) \ | #define cpu_lmemoryread_d(a,pl) \ |
| (!CPU_STAT_PAGING) ? \ | (!CPU_STAT_PAGING) ? \ |
| cpu_memoryread_d(a) : \ | cpu_memoryread_d(a) : \ |
| Line 171 void MEMCALL paging_check(DWORD laddr, D | Line 175 void MEMCALL paging_check(DWORD laddr, D |
| #define cpu_lcmemoryread(a) \ | #define cpu_lcmemoryread(a) \ |
| (!CPU_STAT_PAGING) ? \ | (!CPU_STAT_PAGING) ? \ |
| cpu_memoryread(a) : \ | cpu_memoryread(a) : \ |
| (BYTE)cpu_linear_memory_read(a,1,CPU_PAGE_READ_CODE,CPU_STAT_USER_MODE) | (UINT8)cpu_linear_memory_read(a,1,CPU_PAGE_READ_CODE,CPU_STAT_USER_MODE) |
| #define cpu_lcmemoryread_w(a) \ | #define cpu_lcmemoryread_w(a) \ |
| (!CPU_STAT_PAGING) ? \ | (!CPU_STAT_PAGING) ? \ |
| cpu_memoryread_w(a) : \ | cpu_memoryread_w(a) : \ |
| (WORD)cpu_linear_memory_read(a,2,CPU_PAGE_READ_CODE,CPU_STAT_USER_MODE) | (UINT16)cpu_linear_memory_read(a,2,CPU_PAGE_READ_CODE,CPU_STAT_USER_MODE) |
| #define cpu_lcmemoryread_d(a) \ | #define cpu_lcmemoryread_d(a) \ |
| (!CPU_STAT_PAGING) ? \ | (!CPU_STAT_PAGING) ? \ |
| cpu_memoryread_d(a) : \ | cpu_memoryread_d(a) : \ |
| Line 208 do { \ | Line 212 do { \ |
| * TLB function | * TLB function |
| */ | */ |
| #if defined(IA32_SUPPORT_TLB) | #if defined(IA32_SUPPORT_TLB) |
| void tlb_init(); | void tlb_init(void); |
| void tlb_flush(BOOL allflush); | void tlb_flush(BOOL allflush); |
| void tlb_flush_page(DWORD vaddr); | void tlb_flush_page(UINT32 laddr); |
| #else | #else |
| #define tlb_init() | #define tlb_init() |
| #define tlb_flush(allflush) (void)allflush | #define tlb_flush(allflush) (void)(allflush) |
| #define tlb_flush_page(vaddr) (void)vaddr | #define tlb_flush_page(laddr) (void)(laddr) |
| #endif | #endif |
| #ifdef __cplusplus | #ifdef __cplusplus |