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Diff for /np2/i386c/ia32/paging.h between versions 1.6 and 1.15

version 1.6, 2004/02/03 14:49:39 version 1.15, 2004/03/24 14:03:52
Line 39  extern "C" { Line 39  extern "C" {
  *   *
  *  31                                    12 11   9 8  7 6 5  4   3   2   1  0    *  31                                    12 11   9 8  7 6 5  4   3   2   1  0 
  * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+   * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+
  * |   ページ・テーブルのベース・アドレス   |使用可|G|PS|0|A|PCD|PWT|U/S|R/W|P|   * |   ページ・テーブルのベース・アドレス   |使用可|G|PS|-|A|PCD|PWT|U/S|R/W|P|
  * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+   * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+
  *                                              |   |  | | |  |   |   |   |  |   *                                              |   |  | | |  |   |   |   |  |
  * 9-11: システム・プログラマが使用可能 --------+   |  | | |  |   |   |   |  |   * 9-11: システム・プログラマが使用可能 --------+   |  | | |  |   |   |   |  |
  *    8: グローバル・ページ(無視される) ------------+  | | |  |   |   |   |  |   *    8: グローバル・ページ(無視される) ------------+  | | |  |   |   |   |  |
  *    7: ページ・サイズ (0 = 4k バイトページ) ---------+ | |  |   |   |   |  |   *    7: ページ・サイズ (0 = 4k バイトページ) ---------+ | |  |   |   |   |  |
  *    6: 予約 (0) ---------------------------------------+ |  |   |   |   |  |   *    6: 予約 (-) ---------------------------------------+ |  |   |   |   |  |
  *    5: アクセス -----------------------------------------+  |   |   |   |  |   *    5: アクセス -----------------------------------------+  |   |   |   |  |
  *    4: キャッシュ無効 --------------------------------------+   |   |   |  |   *    4: キャッシュ無効 --------------------------------------+   |   |   |  |
  *    3: ライトスルー --------------------------------------------+   |   |  |   *    3: ライトスルー --------------------------------------------+   |   |  |
Line 54  extern "C" { Line 54  extern "C" {
  *    0: ページ存在 ---------------------------------------------------------+   *    0: ページ存在 ---------------------------------------------------------+
  */   */
 #define CPU_PDE_BASEADDR_MASK   0xfffff000  #define CPU_PDE_BASEADDR_MASK   0xfffff000
   #define CPU_PDE_GLOBAL_PAGE     (1 << 8)
 #define CPU_PDE_PAGE_SIZE       (1 << 7)  #define CPU_PDE_PAGE_SIZE       (1 << 7)
   #define CPU_PDE_DIRTY           (1 << 6)
 #define CPU_PDE_ACCESS          (1 << 5)  #define CPU_PDE_ACCESS          (1 << 5)
 #define CPU_PDE_CACHE_DISABLE   (1 << 4)  #define CPU_PDE_CACHE_DISABLE   (1 << 4)
 #define CPU_PDE_WRITE_THROUGH   (1 << 3)  #define CPU_PDE_WRITE_THROUGH   (1 << 3)
Line 97  extern "C" { Line 99  extern "C" {
  *   *
  *  31                                    12 11   9 8 7 6 5  4   3   2   1  0    *  31                                    12 11   9 8 7 6 5  4   3   2   1  0 
  * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+   * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+
  * |        ページのベース・アドレス        |使用可|G|0|D|A|PCD|PWT|U/S|R/W|P|   * |        ページのベース・アドレス        |使用可|G|-|D|A|PCD|PWT|U/S|R/W|P|
  * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+   * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+
  *                                              |   | | | |  |   |   |   |  |   *                                              |   | | | |  |   |   |   |  |
  *  9-11: システム・プログラマが使用可能 -------+   | | | |  |   |   |   |  |   *  9-11: システム・プログラマが使用可能 -------+   | | | |  |   |   |   |  |
  *     8: グローバル・ページ -----------------------+ | | |  |   |   |   |  |   *     8: グローバル・ページ -----------------------+ | | |  |   |   |   |  |
  *     7: 予約 (0) -----------------------------------+ | |  |   |   |   |  |   *     7: 予約 (-) -----------------------------------+ | |  |   |   |   |  |
  *     6: ダーティ -------------------------------------+ |  |   |   |   |  |   *     6: ダーティ -------------------------------------+ |  |   |   |   |  |
  *     5: アクセス ---------------------------------------+  |   |   |   |  |   *     5: アクセス ---------------------------------------+  |   |   |   |  |
  *     4: キャッシュ無効 ------------------------------------+   |   |   |  |   *     4: キャッシュ無効 ------------------------------------+   |   |   |  |
Line 113  extern "C" { Line 115  extern "C" {
  */   */
 #define CPU_PTE_BASEADDR_MASK   0xfffff000  #define CPU_PTE_BASEADDR_MASK   0xfffff000
 #define CPU_PTE_GLOBAL_PAGE     (1 << 8)  #define CPU_PTE_GLOBAL_PAGE     (1 << 8)
   #define CPU_PTE_PAGE_SIZE       (1 << 7)
 #define CPU_PTE_DIRTY           (1 << 6)  #define CPU_PTE_DIRTY           (1 << 6)
 #define CPU_PTE_ACCESS          (1 << 5)  #define CPU_PTE_ACCESS          (1 << 5)
 #define CPU_PTE_CACHE_DISABLE   (1 << 4)  #define CPU_PTE_CACHE_DISABLE   (1 << 4)
Line 121  extern "C" { Line 124  extern "C" {
 #define CPU_PTE_WRITABLE        (1 << 1)  #define CPU_PTE_WRITABLE        (1 << 1)
 #define CPU_PTE_PRESENT         (1 << 0)  #define CPU_PTE_PRESENT         (1 << 0)
   
 /* paging_check(): rw */  
 #define CPU_PAGING_PAGE_READ    (0 << 0)  
 #define CPU_PAGING_PAGE_WRITE   (1 << 0)  
 #define CPU_PAGING_PAGE_CODE    (1 << 1)  
 #define CPU_PAGING_PAGE_DATA    (1 << 2)  
   
   /*
    * linear address memory access function
    */
   #if defined(IA32_PAGING_EACHSIZE)
   UINT8 MEMCALL cpu_memory_access_la_RMW_b(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg);
   UINT16 MEMCALL cpu_memory_access_la_RMW_w(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg);
   UINT32 MEMCALL cpu_memory_access_la_RMW_d(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg);
   UINT8 MEMCALL cpu_linear_memory_read_b(UINT32 laddr, const int crw, const int user_mode);
   UINT16 MEMCALL cpu_linear_memory_read_w(UINT32 laddr, const int crw, const int user_mode);
   UINT32 MEMCALL cpu_linear_memory_read_d(UINT32 laddr, const int crw, const int user_mode);
   void MEMCALL cpu_linear_memory_write_b(UINT32 laddr, UINT8 value, const int user_mode);
   void MEMCALL cpu_linear_memory_write_w(UINT32 laddr, UINT16 value, const int user_mode);
   void MEMCALL cpu_linear_memory_write_d(UINT32 laddr, UINT32 value, const int user_mode);
   #else   /* !IA32_PAGING_EACHSIZE */
   UINT32 MEMCALL cpu_memory_access_la_RMW(UINT32 laddr, UINT length, const int user_mode, UINT32 (*func)(UINT32, void *), void *arg);
   UINT32 MEMCALL cpu_linear_memory_read(UINT32 address, UINT length, const int crw, const int user_mode);
   void MEMCALL cpu_linear_memory_write(UINT32 address, UINT32 value, UINT length, const int user_mode);
   #endif  /* IA32_PAGING_EACHSIZE */
   void MEMCALL cpu_memory_access_la_region(UINT32 address, UINT length, const int crw, const int user_mode, BYTE *data);
   void MEMCALL paging_check(UINT32 laddr, UINT length, const int crw, const int user_mode);
   
   /* crw */
   #define CPU_PAGE_READ           (0 << 0)
   #define CPU_PAGE_WRITE          (1 << 0)
   #define CPU_PAGE_CODE           (1 << 1)
   #define CPU_PAGE_DATA           (1 << 2)
   #define CPU_PAGE_READ_CODE      (CPU_PAGE_READ|CPU_PAGE_CODE)
   #define CPU_PAGE_READ_DATA      (CPU_PAGE_READ|CPU_PAGE_DATA)
   #define CPU_PAGE_WRITE_DATA     (CPU_PAGE_WRITE|CPU_PAGE_DATA)
   
   #if defined(IA32_PAGING_EACHSIZE)
   
   #define cpu_lmemoryread(a,pl) \
           (!CPU_STAT_PAGING) ? \
            cpu_memoryread(a) : cpu_linear_memory_read_b(a,CPU_PAGE_READ_DATA,pl)
   #define cpu_lmemoryread_b(a,pl) cpu_lmemoryread(a,pl)
   #define cpu_lmemoryread_w(a,pl) \
           (!CPU_STAT_PAGING) ? \
            cpu_memoryread_w(a) : cpu_linear_memory_read_w(a,CPU_PAGE_READ_DATA,pl)
   #define cpu_lmemoryread_d(a,pl) \
           (!CPU_STAT_PAGING) ? \
            cpu_memoryread_d(a) : cpu_linear_memory_read_d(a,CPU_PAGE_READ_DATA,pl)
   
   #define cpu_lmemorywrite(a,v,pl) \
           (!CPU_STAT_PAGING) ? \
            cpu_memorywrite(a,v) : cpu_linear_memory_write_b(a,v,pl)
   #define cpu_lmemorywrite_b(a,v,pl) cpu_lmemorywrite(a,v,pl)
   #define cpu_lmemorywrite_w(a,v,pl) \
           (!CPU_STAT_PAGING) ? \
            cpu_memorywrite_w(a,v) : cpu_linear_memory_write_w(a,v,pl)
   #define cpu_lmemorywrite_d(a,v,pl) \
           (!CPU_STAT_PAGING) ? \
            cpu_memorywrite_d(a,v) : cpu_linear_memory_write_d(a,v,pl)
   
 /* enter/leave paging mode */  /* code */
 void FASTCALL change_pg(int onoff);  #define cpu_lcmemoryread(a) \
           (!CPU_STAT_PAGING) ? \
            cpu_memoryread(a) : \
            cpu_linear_memory_read_b(a,CPU_PAGE_READ_CODE,CPU_STAT_USER_MODE)
   #define cpu_lcmemoryread_w(a) \
           (!CPU_STAT_PAGING) ? \
            cpu_memoryread_w(a) : \
            cpu_linear_memory_read_w(a,CPU_PAGE_READ_CODE,CPU_STAT_USER_MODE)
   #define cpu_lcmemoryread_d(a) \
           (!CPU_STAT_PAGING) ? \
            cpu_memoryread_d(a) : \
            cpu_linear_memory_read_d(a,CPU_PAGE_READ_CODE,CPU_STAT_USER_MODE)
   
 /* paging check */  #else   /* !IA32_PAGING_EACHSIZE */
 void MEMCALL paging_check(DWORD laddr, DWORD length, int rw);  
   
 /*  #define cpu_memory_access_la_RMW_b(l,f,a) \
  * linear address function           cpu_memory_access_la_RMW(l,1,f,a)
  */  #define cpu_memory_access_la_RMW_w(l,f,a) \
 DWORD MEMCALL cpu_linear_memory_read(DWORD address, DWORD length, int code);           cpu_memory_access_la_RMW(l,2,f,a)
 void MEMCALL cpu_linear_memory_write(DWORD address, DWORD value, DWORD length);  #define cpu_memory_access_la_RMW_d(l,f,a) \
            cpu_memory_access_la_RMW(l,4,f,a)
   
 #define cpu_lmemoryread(a) \  #define cpu_lmemoryread(a,pl) \
         (!CPU_STAT_PAGING) ? \          (!CPU_STAT_PAGING) ? \
                 cpu_memoryread(a) : \           cpu_memoryread(a) : \
                 (BYTE)cpu_linear_memory_read(a,1,FALSE)           (UINT8)cpu_linear_memory_read(a,1,CPU_PAGE_READ_DATA,pl)
 #define cpu_lmemoryread_w(a) \  #define cpu_lmemoryread_b(a,pl) cpu_lmemoryread(a,pl)
   #define cpu_lmemoryread_w(a,pl) \
         (!CPU_STAT_PAGING) ? \          (!CPU_STAT_PAGING) ? \
                 cpu_memoryread_w(a) : \           cpu_memoryread_w(a) : \
                 (WORD)cpu_linear_memory_read(a,2,FALSE)           (UINT16)cpu_linear_memory_read(a,2,CPU_PAGE_READ_DATA,pl)
 #define cpu_lmemoryread_d(a) \  #define cpu_lmemoryread_d(a,pl) \
         (!CPU_STAT_PAGING) ? \          (!CPU_STAT_PAGING) ? \
                 cpu_memoryread_d(a) : \           cpu_memoryread_d(a) : \
                 cpu_linear_memory_read(a,4,FALSE)           cpu_linear_memory_read(a,4,CPU_PAGE_READ_DATA,pl)
   
 #define cpu_lmemorywrite(a,v) \  #define cpu_lmemorywrite(a,v,pl) \
         (!CPU_STAT_PAGING) ? \          (!CPU_STAT_PAGING) ? \
                 cpu_memorywrite(a,v) : \           cpu_memorywrite(a,v) : \
                 cpu_linear_memory_write(a,v,1)           cpu_linear_memory_write(a,v,1,pl)
 #define cpu_lmemorywrite_w(a,v) \  #define cpu_lmemorywrite_b(a,v,pl) cpu_lmemorywrite(a,v,pl)
   #define cpu_lmemorywrite_w(a,v,pl) \
         (!CPU_STAT_PAGING) ? \          (!CPU_STAT_PAGING) ? \
                 cpu_memorywrite_w(a,v) : \           cpu_memorywrite_w(a,v) : \
                 cpu_linear_memory_write(a,v,2)           cpu_linear_memory_write(a,v,2,pl)
 #define cpu_lmemorywrite_d(a,v) \  #define cpu_lmemorywrite_d(a,v,pl) \
         (!CPU_STAT_PAGING) ? \          (!CPU_STAT_PAGING) ? \
                 cpu_memorywrite_d(a,v) : \           cpu_memorywrite_d(a,v) : \
                 cpu_linear_memory_write(a,v,4)           cpu_linear_memory_write(a,v,4,pl)
   
   /* code */
 #define cpu_lcmemoryread(a) \  #define cpu_lcmemoryread(a) \
         (!CPU_STAT_PAGING) ? \          (!CPU_STAT_PAGING) ? \
                 cpu_memoryread(a) : \           cpu_memoryread(a) : \
                 (BYTE)cpu_linear_memory_read(a,1,TRUE)           (UINT8)cpu_linear_memory_read(a,1,CPU_PAGE_READ_CODE,CPU_STAT_USER_MODE)
 #define cpu_lcmemoryread_w(a) \  #define cpu_lcmemoryread_w(a) \
         (!CPU_STAT_PAGING) ? \          (!CPU_STAT_PAGING) ? \
                 cpu_memoryread_w(a) : \           cpu_memoryread_w(a) : \
                 (WORD)cpu_linear_memory_read(a,2,TRUE)           (UINT16)cpu_linear_memory_read(a,2,CPU_PAGE_READ_CODE,CPU_STAT_USER_MODE)
 #define cpu_lcmemoryread_d(a) \  #define cpu_lcmemoryread_d(a) \
         (!CPU_STAT_PAGING) ? \          (!CPU_STAT_PAGING) ? \
                 cpu_memoryread_d(a) : \           cpu_memoryread_d(a) : \
                 cpu_linear_memory_read(a,4,TRUE)           cpu_linear_memory_read(a,4,CPU_PAGE_READ_CODE,CPU_STAT_USER_MODE)
   
   #endif  /* IA32_PAGING_EACHSIZE */
   
   /*
    * linear address memory access with superviser mode
    */
   #define cpu_kmemoryread(a)      cpu_lmemoryread(a,CPU_MODE_SUPERVISER)
   #define cpu_kmemoryread_w(a)    cpu_lmemoryread_w(a,CPU_MODE_SUPERVISER)
   #define cpu_kmemoryread_d(a)    cpu_lmemoryread_d(a,CPU_MODE_SUPERVISER)
   #define cpu_kmemorywrite(a,v)   cpu_lmemorywrite(a,v,CPU_MODE_SUPERVISER)
   #define cpu_kmemorywrite_w(a,v) cpu_lmemorywrite_w(a,v,CPU_MODE_SUPERVISER)
   #define cpu_kmemorywrite_d(a,v) cpu_lmemorywrite_d(a,v,CPU_MODE_SUPERVISER)
   
   
   /*
    * CR3 (Page Directory Entry base physical address)
    */
 #define set_CR3(cr3) \  #define set_CR3(cr3) \
 do { \  do { \
           VERBOSE(("set_CR3: old = %08x, new = 0x%08x", CPU_CR3, (cr3) & CPU_CR3_MASK)); \
         CPU_CR3 = (cr3) & CPU_CR3_MASK; \          CPU_CR3 = (cr3) & CPU_CR3_MASK; \
         CPU_STAT_PDE_BASE = CPU_CR3 & CPU_CR3_PD_MASK; \          CPU_STAT_PDE_BASE = CPU_CR3 & CPU_CR3_PD_MASK; \
         tlb_flush(FALSE); \          tlb_flush(FALSE); \
Line 190  do { \ Line 272  do { \
 /*  /*
  * TLB function   * TLB function
  */   */
 void tlb_init();  #if defined(IA32_SUPPORT_TLB)
   void tlb_init(void);
 void tlb_flush(BOOL allflush);  void tlb_flush(BOOL allflush);
 void tlb_flush_page(DWORD vaddr);  void tlb_flush_page(UINT32 laddr);
   #else
   #define tlb_init()
   #define tlb_flush(allflush)     (void)(allflush)
   #define tlb_flush_page(laddr)   (void)(laddr)
   #endif
   
 #ifdef __cplusplus  #ifdef __cplusplus
 }  }
Removed from v.1.6  
changed lines
  Added in v.1.15

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