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Diff for /np2/i386c/ia32/paging.h between versions 1.16 and 1.28

-version 1.16, 2004/03/24 14:34:23
+version 1.28, 2012/01/08 18:26:10
  Line 1
- /*      $Id$    */
  /*
   * Copyright (c) 2003 NONAKA Kimihiro
   * All rights reserved.
- Line 12
+ Line 10
   * 2. Redistributions in binary form must reproduce the above copyright
   *    notice, this list of conditions and the following disclaimer in the
   *    documentation and/or other materials provided with the distribution.
-  * 3. The name of the author may not be used to endorse or promote products
-  *    derived from this software without specific prior written permission.
   *
   * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- Line 35  extern "C" {
+ Line 31  extern "C" {
  #endif
  /*
   * 矢□斥’犯奴伊弁玄伉’巨件玄伉 (4K 田奶玄矢□斥銀迕凜)
   *
   *  31                                    12 11   9 8  7 6 5  4   3   2   1  0
   * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+
-  * |   ’伊﹝扑’弁﹝仲’瓦﹝扑’亥’鬖石’伙﹝扑’弗﹝仲’＞’用’孎弗   |扔生目丞奶玄|G|PS|-|A|PCD|PWT|U/S|R/W|P|
+  * |   樍婍汙槻弁樍扔樍砍汙樍极早槦亦樍砱汙槻弗樍扔槻＞樍脣旨槻弗   |餈末薀奴濈永|G|PS|-|A|PCD|PWT|U/S|R/W|P|
   * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+
   *                                              |   |  | | |  |   |   |   |  |
-  * 9-11: ’平’弗’瓦’逽仲’仿’𤪦□’穨‵﹜乓扔生目丞奶玄甘旦 --------+   |  | | |  |   |   |   |  |
+  * 9-11: 扑旦氾丞’皿伕弘仿穴互銀迕第チ --------+   |  | | |  |   |   |   |  |
-  *    8: ’□’减扑’立’鬕仲’伊﹝扑’弁(白左扔鬖左﹜囍 ------------+  | | |  |   |   |   |  |
+  *    8: 弘伕□田伙’矢□斥(拑骰今木月) ------------+  | | |  |   |   |   |  |
   *    7: 矢□斥’扔奶朮 (0 = 4k 田奶玄矢□斥) ---------+ | |  |   |   |   |  |
   *    6: 芺沶 (-) ---------------------------------------+ |  |   |   |   |  |
   *    5: 失弁本旦 -----------------------------------------+  |   |   |   |  |
   *    4: 平乓永扑亙拑躲 --------------------------------------+   |   |   |  |
   *    3: 仿奶玄旦伙□ --------------------------------------------+   |   |  |
   *    2: 交□扒▼旦□由田奶扒 (0 = 旦□由田奶扒) ---------------------+   |  |
   *    1: 厶心潸曰▼踏五慇心 (0 = 厶心潸曰及心) ---------------------------+  |
   *    0: 矢□斥繡箕 ---------------------------------------------------------+
   */
  #define CPU_PDE_BASEADDR_MASK   0xfffff000
  #define CPU_PDE_GLOBAL_PAGE     (1 << 8)
- Line 65  extern "C" {
+ Line 61  extern "C" {
  #define CPU_PDE_PRESENT         (1 << 0)
  /*
   * 矢□斥’犯奴伊弁玄伉’巨件玄伉 (4M 田奶玄矢□斥銀迕凜)
   *
   *  31                        22 21       12 11   9 8  7 6 5  4   3   2   1  0
   * +----------------------------+-----------+------+-+--+-+-+---+---+---+---+-+
-  * |矢□斥氾□皮伙及坁咥失玉伊旦|  芺沶碧心 |銀迕第|G|PS|D|A|PCD|PWT|U/S|R/W|P|
+  * |樍婍汙槻弁樍砍汙樍极早槦亦臄孕艛砍中樍脣旨槻弗|  頛圈巨刻弁啣Ⅸ |餈末薀奴濈永|G|PS|D|A|PCD|PWT|U/S|R/W|P|
   * +----------------------------+-----------+------+-+--+-+-+---+---+---+---+-+
   *                                              |   |  | | |  |   |   |   |  |
-  * 9-11: ’平’弗’瓦’逽仲’仿’𤪦□’穨‵﹜乓扔生目丞奶玄甘旦 --------+   |  | | |  |   |   |   |  |
+  * 9-11: 扑旦氾丞’皿伕弘仿穴互銀迕第チ --------+   |  | | |  |   |   |   |  |
-  *    8: ’□’减扑’立’鬕仲’伊﹝扑’弁 ------------------------+  | | |  |   |   |   |  |
+  *    8: 弘伕□田伙’矢□斥 ------------------------+  | | |  |   |   |   |  |
-  *    7: ’伊﹝扑’弁﹝仲’左’﹜’戊 (1 = 4M ’立’﹜’生’伊﹝扑’弁) ---------+ | |  |   |   |   |  |
+  *    7: 矢□斥’扔奶朮 (1 = 4M 田奶玄矢□斥) ---------+ | |  |   |   |   |  |
-  *    6: ’正﹝扑’瓦’＝ ---------------------------------------+ |  |   |   |   |  |
+  *    6: 母□氾奴 ---------------------------------------+ |  |   |   |   |  |
-  *    5: ’＞’永’扔’弗 -----------------------------------------+  |   |   |   |  |
+  *    5: 失弁本旦 -----------------------------------------+  |   |   |   |  |
-  *    4: ’亙’瑽氾’平’縗左弁--------------------------------------+   |   |   |  |
+  *    4: 平乓永扑亙拑躲 --------------------------------------+   |   |   |  |
-  *    3: ’穨﹜’生’弗’鬕扑 --------------------------------------------+   |   |  |
+  *    3: 仿奶玄旦伙□ --------------------------------------------+   |   |  |
-  *    2: ’鴥扑’市﹝末’弗﹝扑’丞’立’﹜’市 (0 = ’弗﹝扑’丞’立’﹜’市) ---------------------+   |  |
+  *    2: 交□扒▼旦□由田奶扒 (0 = 旦□由田奶扒) ---------------------+   |  |
-  *    1: 瓦用﹜′扑藀穬末旦韙食孆(0 = 厶心潸曰及心) ---------------------------+  |
+  *    1: 厶心潸曰▼踏五慇心 (0 = 厶心潸曰及心) ---------------------------+  |
   *    0: 矢□斥繡箕 ---------------------------------------------------------+
   */
  #define CPU_PDE_4M_BASEADDR_MASK        0xffc00000
  #define CPU_PDE_4M_GLOBAL_PAGE          (1 << 8)
- Line 95  extern "C" {
+ Line 91  extern "C" {
  #define CPU_PDE_4M_PRESENT              (1 << 0)
  /*
-  * 矢□斥’氾□皮伙’巨件玄伉 (4k 田奶玄’矢□斥)
+  * 樍婍汙槻弁樍扔樍砍汙樍极早樍扔槻奴樍它樍啣收 (4k 樍濰丹樍啣汗樍婍汙槻弁)
   *
   *  31                                    12 11   9 8 7 6 5  4   3   2   1  0
   * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+
-  * |        ’伊﹝扑’弁﹜石’伙﹝扑’弗﹝仲’＞’用’孎弗        |扔生目丞奶玄|G|-|D|A|PCD|PWT|U/S|R/W|P|
+  * |        樍婍汙槻弁槦亦樍砱汙槻弗樍扔槻＞樍脣旨槻弗        |餈末薀奴濈永|G|-|D|A|PCD|PWT|U/S|R/W|P|
   * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+
   *                                              |   | | | |  |   |   |   |  |
-  *  9-11: ’平’弗’瓦’逽仲’仿’𤪦□’穨‵﹜乓扔生目丞奶玄甘旦 -------+   | | | |  |   |   |   |  |
+  *  9-11: 扑旦氾丞’皿伕弘仿穴互銀迕第チ -------+   | | | |  |   |   |   |  |
-  *     8: ’□’减扑’立’鬕仲’伊﹝扑’弁 -----------------------+ | | |  |   |   |   |  |
+  *     8: 弘伕□田伙’矢□斥 -----------------------+ | | |  |   |   |   |  |
-  *     7: 目旦白(-) -----------------------------------+ | |  |   |   |   |  |
+  *     7: 芺沶 (-) -----------------------------------+ | |  |   |   |   |  |
   *     6: 母□氾奴 -------------------------------------+ |  |   |   |   |  |
   *     5: 失弁本旦 ---------------------------------------+  |   |   |   |  |
   *     4: 平乓永扑亙拑躲 ------------------------------------+   |   |   |  |
   *     3: 仿奶玄旦伙□ ------------------------------------------+   |   |  |
   *     2: 交□扒▼旦□由田奶扒 (0 = 旦□由田奶扒) -------------------+   |  |
   *     1: 厶心潸曰▼踏五慇心 (0 = 厶心潸曰及心) -------------------------+  |
   *     0: 矢□斥繡箕 -------------------------------------------------------+
   */
  #define CPU_PTE_BASEADDR_MASK   0xfffff000
  #define CPU_PTE_GLOBAL_PAGE     (1 << 8)
- Line 124  extern "C" {
+ Line 120  extern "C" {
  #define CPU_PTE_WRITABLE        (1 << 1)
  #define CPU_PTE_PRESENT         (1 << 0)
+ #define PAGE_SIZE       0x1000
+ #define PAGE_MASK       (PAGE_SIZE - 1)
- /*
+ /* ucrw */
-  * linear address memory access function
-  */
- void MEMCALL cpu_memory_access_la_region(UINT32 address, UINT length, const int ucrw, BYTE *data);
- void MEMCALL paging_check(UINT32 laddr, UINT length, const int ucrw);
- /* crw */
- #define CPU_PAGE_READ           (0 << 0)
  #define CPU_PAGE_WRITE          (1 << 0)
  #define CPU_PAGE_CODE           (1 << 1)
  #define CPU_PAGE_DATA           (1 << 2)
  #define CPU_PAGE_USER_MODE      (1 << 3)        /* == CPU_MODE_USER */
- #define CPU_PAGE_READ_CODE      (CPU_PAGE_READ|CPU_PAGE_CODE)
+ #define CPU_PAGE_READ_CODE      (CPU_PAGE_CODE)
- #define CPU_PAGE_READ_DATA      (CPU_PAGE_READ|CPU_PAGE_DATA)
+ #define CPU_PAGE_READ_DATA      (CPU_PAGE_DATA)
  #define CPU_PAGE_WRITE_DATA     (CPU_PAGE_WRITE|CPU_PAGE_DATA)
- #if defined(IA32_PAGING_EACHSIZE)
+ UINT8 MEMCALL cpu_memory_access_la_RMW_b(UINT32 laddr, UINT32 (CPUCALL *func)(UINT32, void *), void *arg);
+ UINT16 MEMCALL cpu_memory_access_la_RMW_w(UINT32 laddr, UINT32 (CPUCALL *func)(UINT32, void *), void *arg);
+ UINT32 MEMCALL cpu_memory_access_la_RMW_d(UINT32 laddr, UINT32 (CPUCALL *func)(UINT32, void *), void *arg);
+ UINT8 MEMCALL cpu_linear_memory_read_b(UINT32 laddr, int ucrw);
+ UINT16 MEMCALL cpu_linear_memory_read_w(UINT32 laddr, int ucrw);
+ UINT32 MEMCALL cpu_linear_memory_read_d(UINT32 laddr, int ucrw);
+ UINT64 MEMCALL cpu_linear_memory_read_q(UINT32 laddr, int ucrw);
+ REG80 MEMCALL cpu_linear_memory_read_f(UINT32 laddr, int ucrw);
+ void MEMCALL cpu_linear_memory_write_b(UINT32 laddr, UINT8 value, int ucrw);
+ void MEMCALL cpu_linear_memory_write_w(UINT32 laddr, UINT16 value, int ucrw);
+ void MEMCALL cpu_linear_memory_write_d(UINT32 laddr, UINT32 value, int ucrw);
+ void MEMCALL cpu_linear_memory_write_q(UINT32 laddr, UINT64 value, int ucrw);
+ void MEMCALL cpu_linear_memory_write_f(UINT32 laddr, const REG80 *value, int ucrw);
+ /*
+  * linear address memory access function with TLB
+  */
+ /* RMW */
+ STATIC_INLINE UINT8 MEMCALL
+ cpu_lmemory_RMW_b(UINT32 laddr, UINT32 (CPUCALL *func)(UINT32, void *), void *arg)
+ {
+         UINT32 result;
+         UINT8 value;
+         if (!CPU_STAT_PAGING) {
+                 value = cpu_memoryread_b(laddr);
+                 result = (*func)(value, arg);
+                 cpu_memorywrite_b(laddr, result);
+                 return value;
+         }
+         return cpu_memory_access_la_RMW_b(laddr, func, arg);
+ }
+ STATIC_INLINE UINT16 MEMCALL
+ cpu_lmemory_RMW_w(UINT32 laddr, UINT32 (CPUCALL *func)(UINT32, void *), void *arg)
+ {
+         UINT32 result;
+         UINT16 value;
+         if (!CPU_STAT_PAGING) {
+                 value = cpu_memoryread_w(laddr);
+                 result = (*func)(value, arg);
+                 cpu_memorywrite_w(laddr, result);
+                 return value;
+         }
+         return cpu_memory_access_la_RMW_w(laddr, func, arg);
+ }
+ STATIC_INLINE UINT32 MEMCALL
+ cpu_lmemory_RMW_d(UINT32 laddr, UINT32 (CPUCALL *func)(UINT32, void *), void *arg)
+ {
+         UINT32 result;
+         UINT32 value;
+         if (!CPU_STAT_PAGING) {
+                 value = cpu_memoryread_d(laddr);
+                 result = (*func)(value, arg);
+                 cpu_memorywrite_d(laddr, result);
+                 return value;
+         }
+         return cpu_memory_access_la_RMW_d(laddr, func, arg);
+ }
+ /* read */
+ STATIC_INLINE UINT8 MEMCALL
+ cpu_lmemoryread_b(UINT32 laddr, int ucrw)
+ {
+         if (!CPU_STAT_PAGING)
+                 return cpu_memoryread_b(laddr);
+         return cpu_linear_memory_read_b(laddr, ucrw);
+ }
+ #define cpu_lmemoryread(a,ucrw) cpu_lmemoryread_b((a),(ucrw))
+ STATIC_INLINE UINT16 MEMCALL
+ cpu_lmemoryread_w(UINT32 laddr, int ucrw)
+ {
+         if (!CPU_STAT_PAGING)
+                 return cpu_memoryread_w(laddr);
+         return cpu_linear_memory_read_w(laddr, ucrw);
+ }
+ STATIC_INLINE UINT32 MEMCALL
+ cpu_lmemoryread_d(UINT32 laddr, int ucrw)
+ {
+         if (!CPU_STAT_PAGING)
+                 return cpu_memoryread_d(laddr);
+         return cpu_linear_memory_read_d(laddr, ucrw);
+ }
+ STATIC_INLINE UINT64
+ cpu_lmemoryread_q(UINT32 laddr, int ucrw)
+ {
+         if (!CPU_STAT_PAGING)
+                 return cpu_memoryread_q(laddr);
+         return cpu_linear_memory_read_q(laddr, ucrw);
+ }
+ STATIC_INLINE REG80
+ cpu_lmemoryread_f(UINT32 laddr, int ucrw)
+ {
+         if (!CPU_STAT_PAGING)
+                 return cpu_memoryread_f(laddr);
+         return cpu_linear_memory_read_f(laddr, ucrw);
+ }
+ /* write */
+ STATIC_INLINE void MEMCALL
+ cpu_lmemorywrite_b(UINT32 laddr, UINT8 value, int ucrw)
+ {
+         if (!CPU_STAT_PAGING) {
+                 cpu_memorywrite_b(laddr, value);
+                 return;
+         }
+         cpu_linear_memory_write_b(laddr, value, ucrw);
+ }
+ #define cpu_lmemorywrite(a,v,ucrw) cpu_lmemorywrite_b((a),(v),(ucrw))
+ STATIC_INLINE void MEMCALL
+ cpu_lmemorywrite_w(UINT32 laddr, UINT16 value, int ucrw)
+ {
+         if (!CPU_STAT_PAGING) {
+                 cpu_memorywrite_w(laddr, value);
+                 return;
+         }
+         cpu_linear_memory_write_w(laddr, value, ucrw);
+ }
- UINT8 MEMCALL cpu_memory_access_la_RMW_b(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg);
+ STATIC_INLINE void MEMCALL
- UINT16 MEMCALL cpu_memory_access_la_RMW_w(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg);
+ cpu_lmemorywrite_d(UINT32 laddr, UINT32 value, int ucrw)
- UINT32 MEMCALL cpu_memory_access_la_RMW_d(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg);
+ {
- UINT8 MEMCALL cpu_linear_memory_read_b(UINT32 laddr, const int ucrw);
- UINT16 MEMCALL cpu_linear_memory_read_w(UINT32 laddr, const int ucrw);
+         if (!CPU_STAT_PAGING) {
- UINT32 MEMCALL cpu_linear_memory_read_d(UINT32 laddr, const int ucrw);
+                 cpu_memorywrite_d(laddr, value);
- void MEMCALL cpu_linear_memory_write_b(UINT32 laddr, UINT8 value, const int user_mode);
+                 return;
- void MEMCALL cpu_linear_memory_write_w(UINT32 laddr, UINT16 value, const int user_mode);
+         }
- void MEMCALL cpu_linear_memory_write_d(UINT32 laddr, UINT32 value, const int user_mode);
+         cpu_linear_memory_write_d(laddr, value, ucrw);
+ }
- #define cpu_lmemoryread(a,pl) \
-         (!CPU_STAT_PAGING) ? \
+ STATIC_INLINE void MEMCALL
-          cpu_memoryread(a) : \
+ cpu_lmemorywrite_q(UINT32 laddr, UINT64 value, int ucrw)
-          cpu_linear_memory_read_b(a,CPU_PAGE_READ_DATA | (pl))
+ {
- #define cpu_lmemoryread_b(a,pl) cpu_lmemoryread(a,pl)
- #define cpu_lmemoryread_w(a,pl) \
+         if (!CPU_STAT_PAGING) {
-         (!CPU_STAT_PAGING) ? \
+                 cpu_memorywrite_q(laddr, value);
-          cpu_memoryread_w(a) : \
+                 return;
-          cpu_linear_memory_read_w(a,CPU_PAGE_READ_DATA | (pl))
+         }
- #define cpu_lmemoryread_d(a,pl) \
+         cpu_linear_memory_write_q(laddr, value, ucrw);
-         (!CPU_STAT_PAGING) ? \
+ }
-          cpu_memoryread_d(a) : \
-          cpu_linear_memory_read_d(a,CPU_PAGE_READ_DATA | (pl))
+ STATIC_INLINE void MEMCALL
+ cpu_lmemorywrite_f(UINT32 laddr, const REG80 *value, int ucrw)
- #define cpu_lmemorywrite(a,v,pl) \
+ {
-         (!CPU_STAT_PAGING) ? \
-          cpu_memorywrite(a,v) : cpu_linear_memory_write_b(a,v,pl)
+         if (!CPU_STAT_PAGING) {
- #define cpu_lmemorywrite_b(a,v,pl) cpu_lmemorywrite(a,v,pl)
+                 cpu_memorywrite_f(laddr, value);
- #define cpu_lmemorywrite_w(a,v,pl) \
+                 return;
-         (!CPU_STAT_PAGING) ? \
+         }
-          cpu_memorywrite_w(a,v) : cpu_linear_memory_write_w(a,v,pl)
+         cpu_linear_memory_write_f(laddr, value, ucrw);
- #define cpu_lmemorywrite_d(a,v,pl) \
+ }
-         (!CPU_STAT_PAGING) ? \
-          cpu_memorywrite_d(a,v) : cpu_linear_memory_write_d(a,v,pl)
- /* code */
- #define cpu_lcmemoryread(a) \
-         (!CPU_STAT_PAGING) ? \
-          cpu_memoryread(a) : \
-          cpu_linear_memory_read_b(a,CPU_PAGE_READ_CODE|CPU_STAT_USER_MODE)
- #define cpu_lcmemoryread_w(a) \
-         (!CPU_STAT_PAGING) ? \
-          cpu_memoryread_w(a) : \
-          cpu_linear_memory_read_w(a,CPU_PAGE_READ_CODE|CPU_STAT_USER_MODE)
- #define cpu_lcmemoryread_d(a) \
-         (!CPU_STAT_PAGING) ? \
-          cpu_memoryread_d(a) : \
-          cpu_linear_memory_read_d(a,CPU_PAGE_READ_CODE|CPU_STAT_USER_MODE)
- #else   /* !IA32_PAGING_EACHSIZE */
- UINT32 MEMCALL cpu_memory_access_la_RMW(UINT32 laddr, UINT length, UINT32 (*func)(UINT32, void *), void *arg);
- UINT32 MEMCALL cpu_linear_memory_read(UINT32 address, UINT length, const int ucrw);
- void MEMCALL cpu_linear_memory_write(UINT32 address, UINT32 value, UINT length, const int user_mode);
- #define cpu_memory_access_la_RMW_b(l,f,a) \
-          cpu_memory_access_la_RMW(l,1,f,a)
- #define cpu_memory_access_la_RMW_w(l,f,a) \
-          cpu_memory_access_la_RMW(l,2,f,a)
- #define cpu_memory_access_la_RMW_d(l,f,a) \
-          cpu_memory_access_la_RMW(l,4,f,a)
- #define cpu_lmemoryread(a,pl) \
-         (!CPU_STAT_PAGING) ? \
-          cpu_memoryread(a) : \
-          (UINT8)cpu_linear_memory_read(a,1,CPU_PAGE_READ_DATA | (pl))
- #define cpu_lmemoryread_b(a,pl) cpu_lmemoryread(a,pl)
- #define cpu_lmemoryread_w(a,pl) \
-         (!CPU_STAT_PAGING) ? \
-          cpu_memoryread_w(a) : \
-          (UINT16)cpu_linear_memory_read(a,2,CPU_PAGE_READ_DATA | (pl))
- #define cpu_lmemoryread_d(a,pl) \
-         (!CPU_STAT_PAGING) ? \
-          cpu_memoryread_d(a) : \
-          cpu_linear_memory_read(a,4,CPU_PAGE_READ_DATA | (pl))
- #define cpu_lmemorywrite(a,v,pl) \
-         (!CPU_STAT_PAGING) ? \
-          cpu_memorywrite(a,v) : \
-          cpu_linear_memory_write(a,v,1,pl)
- #define cpu_lmemorywrite_b(a,v,pl) cpu_lmemorywrite(a,v,pl)
- #define cpu_lmemorywrite_w(a,v,pl) \
-         (!CPU_STAT_PAGING) ? \
-          cpu_memorywrite_w(a,v) : \
-          cpu_linear_memory_write(a,v,2,pl)
- #define cpu_lmemorywrite_d(a,v,pl) \
-         (!CPU_STAT_PAGING) ? \
-          cpu_memorywrite_d(a,v) : \
-          cpu_linear_memory_write(a,v,4,pl)
- /* code */
- #define cpu_lcmemoryread(a) \
-         (!CPU_STAT_PAGING) ? \
-          cpu_memoryread(a) : \
-          (UINT8)cpu_linear_memory_read(a,1,CPU_PAGE_READ_CODE|CPU_STAT_USER_MODE)
- #define cpu_lcmemoryread_w(a) \
-         (!CPU_STAT_PAGING) ? \
-          cpu_memoryread_w(a) : \
-          (UINT16)cpu_linear_memory_read(a,2,CPU_PAGE_READ_CODE|CPU_STAT_USER_MODE)
- #define cpu_lcmemoryread_d(a) \
-         (!CPU_STAT_PAGING) ? \
-          cpu_memoryread_d(a) : \
-          cpu_linear_memory_read(a,4,CPU_PAGE_READ_CODE|CPU_STAT_USER_MODE)
- #endif  /* IA32_PAGING_EACHSIZE */
  /*
   * linear address memory access with superviser mode
   */
- #define cpu_kmemoryread(a)      cpu_lmemoryread(a,CPU_MODE_SUPERVISER)
+ #define cpu_kmemoryread(a) \
- #define cpu_kmemoryread_w(a)    cpu_lmemoryread_w(a,CPU_MODE_SUPERVISER)
+         cpu_lmemoryread((a),CPU_PAGE_READ_DATA|CPU_MODE_SUPERVISER)
- #define cpu_kmemoryread_d(a)    cpu_lmemoryread_d(a,CPU_MODE_SUPERVISER)
+ #define cpu_kmemoryread_w(a) \
- #define cpu_kmemorywrite(a,v)   cpu_lmemorywrite(a,v,CPU_MODE_SUPERVISER)
+         cpu_lmemoryread_w((a),CPU_PAGE_READ_DATA|CPU_MODE_SUPERVISER)
- #define cpu_kmemorywrite_w(a,v) cpu_lmemorywrite_w(a,v,CPU_MODE_SUPERVISER)
+ #define cpu_kmemoryread_d(a) \
- #define cpu_kmemorywrite_d(a,v) cpu_lmemorywrite_d(a,v,CPU_MODE_SUPERVISER)
+         cpu_lmemoryread_d((a),CPU_PAGE_READ_DATA|CPU_MODE_SUPERVISER)
+ #define cpu_kmemorywrite(a,v) \
+         cpu_lmemorywrite((a),(v),CPU_PAGE_WRITE_DATA|CPU_MODE_SUPERVISER)
+ #define cpu_kmemorywrite_w(a,v) \
+         cpu_lmemorywrite_w((a),(v),CPU_PAGE_WRITE_DATA|CPU_MODE_SUPERVISER)
+ #define cpu_kmemorywrite_d(a,v) \
+         cpu_lmemorywrite_d((a),(v),CPU_PAGE_WRITE_DATA|CPU_MODE_SUPERVISER)
  /*
-  * CR3 (Page Directory Entry base physical address)
+  * linear address memory access function
   */
- #define set_CR3(cr3) \
+ void MEMCALL cpu_memory_access_la_region(UINT32 address, UINT length, int ucrw, UINT8 *data);
- do { \
+ UINT32 MEMCALL laddr2paddr(UINT32 laddr, int ucrw);
-         VERBOSE(("set_CR3: old = %08x, new = 0x%08x", CPU_CR3, (cr3) & CPU_CR3_MASK)); \
-         CPU_CR3 = (cr3) & CPU_CR3_MASK; \
-         CPU_STAT_PDE_BASE = CPU_CR3 & CPU_CR3_PD_MASK; \
-         tlb_flush(FALSE); \
- } while (/*CONSTCOND*/ 0)
+ STATIC_INLINE UINT32 MEMCALL
+ laddr_to_paddr(UINT32 laddr, int ucrw)
+ {
+         if (!CPU_STAT_PAGING)
+                 return laddr;
+         return laddr2paddr(laddr, ucrw);
+ }
  /*
   * TLB function
   */
- #if defined(IA32_SUPPORT_TLB)
+ struct tlb_entry;
  void tlb_init(void);
- void tlb_flush(BOOL allflush);
+ void MEMCALL tlb_flush(BOOL allflush);
- void tlb_flush_page(UINT32 laddr);
+ void MEMCALL tlb_flush_page(UINT32 laddr);
- #else
+ struct tlb_entry *MEMCALL tlb_lookup(UINT32 laddr, int ucrw);
- #define tlb_init()
- #define tlb_flush(allflush)     (void)(allflush)
- #define tlb_flush_page(laddr)   (void)(laddr)
- #endif
  #ifdef __cplusplus
  }

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	Added in v.1.28