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Diff for /np2/i386c/ia32/paging.h between versions 1.8 and 1.18

version 1.8, 2004/02/05 16:43:44 version 1.18, 2004/06/15 13:50:13
Line 39  extern "C" { Line 39  extern "C" {
  *   *
  *  31                                    12 11   9 8  7 6 5  4   3   2   1  0    *  31                                    12 11   9 8  7 6 5  4   3   2   1  0 
  * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+   * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+
  * |   ページ・テーブルのベース・アドレス   |使用可|G|PS|0|A|PCD|PWT|U/S|R/W|P|   * |   ページ・テーブルのベース・アドレス   |使用可|G|PS|-|A|PCD|PWT|U/S|R/W|P|
  * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+   * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+
  *                                              |   |  | | |  |   |   |   |  |   *                                              |   |  | | |  |   |   |   |  |
  * 9-11: システム・プログラマが使用可能 --------+   |  | | |  |   |   |   |  |   * 9-11: システム・プログラマが使用可能 --------+   |  | | |  |   |   |   |  |
  *    8: グローバル・ページ(無視される) ------------+  | | |  |   |   |   |  |   *    8: グローバル・ページ(無視される) ------------+  | | |  |   |   |   |  |
  *    7: ページ・サイズ (0 = 4k バイトページ) ---------+ | |  |   |   |   |  |   *    7: ページ・サイズ (0 = 4k バイトページ) ---------+ | |  |   |   |   |  |
  *    6: 予約 (0) ---------------------------------------+ |  |   |   |   |  |   *    6: 予約 (-) ---------------------------------------+ |  |   |   |   |  |
  *    5: アクセス -----------------------------------------+  |   |   |   |  |   *    5: アクセス -----------------------------------------+  |   |   |   |  |
  *    4: キャッシュ無効 --------------------------------------+   |   |   |  |   *    4: キャッシュ無効 --------------------------------------+   |   |   |  |
  *    3: ライトスルー --------------------------------------------+   |   |  |   *    3: ライトスルー --------------------------------------------+   |   |  |
Line 54  extern "C" { Line 54  extern "C" {
  *    0: ページ存在 ---------------------------------------------------------+   *    0: ページ存在 ---------------------------------------------------------+
  */   */
 #define CPU_PDE_BASEADDR_MASK   0xfffff000  #define CPU_PDE_BASEADDR_MASK   0xfffff000
   #define CPU_PDE_GLOBAL_PAGE     (1 << 8)
 #define CPU_PDE_PAGE_SIZE       (1 << 7)  #define CPU_PDE_PAGE_SIZE       (1 << 7)
   #define CPU_PDE_DIRTY           (1 << 6)
 #define CPU_PDE_ACCESS          (1 << 5)  #define CPU_PDE_ACCESS          (1 << 5)
 #define CPU_PDE_CACHE_DISABLE   (1 << 4)  #define CPU_PDE_CACHE_DISABLE   (1 << 4)
 #define CPU_PDE_WRITE_THROUGH   (1 << 3)  #define CPU_PDE_WRITE_THROUGH   (1 << 3)
Line 97  extern "C" { Line 99  extern "C" {
  *   *
  *  31                                    12 11   9 8 7 6 5  4   3   2   1  0    *  31                                    12 11   9 8 7 6 5  4   3   2   1  0 
  * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+   * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+
  * |        ページのベース・アドレス        |使用可|G|0|D|A|PCD|PWT|U/S|R/W|P|   * |        ページのベース・アドレス        |使用可|G|-|D|A|PCD|PWT|U/S|R/W|P|
  * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+   * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+
  *                                              |   | | | |  |   |   |   |  |   *                                              |   | | | |  |   |   |   |  |
  *  9-11: システム・プログラマが使用可能 -------+   | | | |  |   |   |   |  |   *  9-11: システム・プログラマが使用可能 -------+   | | | |  |   |   |   |  |
  *     8: グローバル・ページ -----------------------+ | | |  |   |   |   |  |   *     8: グローバル・ページ -----------------------+ | | |  |   |   |   |  |
  *     7: 予約 (0) -----------------------------------+ | |  |   |   |   |  |   *     7: 予約 (-) -----------------------------------+ | |  |   |   |   |  |
  *     6: ダーティ -------------------------------------+ |  |   |   |   |  |   *     6: ダーティ -------------------------------------+ |  |   |   |   |  |
  *     5: アクセス ---------------------------------------+  |   |   |   |  |   *     5: アクセス ---------------------------------------+  |   |   |   |  |
  *     4: キャッシュ無効 ------------------------------------+   |   |   |  |   *     4: キャッシュ無効 ------------------------------------+   |   |   |  |
Line 113  extern "C" { Line 115  extern "C" {
  */   */
 #define CPU_PTE_BASEADDR_MASK   0xfffff000  #define CPU_PTE_BASEADDR_MASK   0xfffff000
 #define CPU_PTE_GLOBAL_PAGE     (1 << 8)  #define CPU_PTE_GLOBAL_PAGE     (1 << 8)
   #define CPU_PTE_PAGE_SIZE       (1 << 7)
 #define CPU_PTE_DIRTY           (1 << 6)  #define CPU_PTE_DIRTY           (1 << 6)
 #define CPU_PTE_ACCESS          (1 << 5)  #define CPU_PTE_ACCESS          (1 << 5)
 #define CPU_PTE_CACHE_DISABLE   (1 << 4)  #define CPU_PTE_CACHE_DISABLE   (1 << 4)
Line 125  extern "C" { Line 128  extern "C" {
 /*  /*
  * linear address memory access function   * linear address memory access function
  */   */
 DWORD MEMCALL cpu_linear_memory_read(DWORD address, DWORD length, int code, int user_mode);  void MEMCALL cpu_memory_access_la_region(UINT32 address, UINT length, const int ucrw, BYTE *data);
 void MEMCALL cpu_linear_memory_write(DWORD address, DWORD value, DWORD length, int user_mode);  void MEMCALL paging_check(UINT32 laddr, UINT length, const int ucrw);
 void MEMCALL paging_check(DWORD laddr, DWORD length, int crw, int user_mode);  
   
 /* crw */  /* ucrw */
 #define CPU_PAGE_READ           (0 << 0)  
 #define CPU_PAGE_WRITE          (1 << 0)  #define CPU_PAGE_WRITE          (1 << 0)
 #define CPU_PAGE_CODE           (1 << 1)  #define CPU_PAGE_CODE           (1 << 1)
 #define CPU_PAGE_DATA           (1 << 2)  #define CPU_PAGE_DATA           (1 << 2)
 #define CPU_PAGE_READ_CODE      (CPU_PAGE_READ|CPU_PAGE_CODE)  #define CPU_PAGE_USER_MODE      (1 << 3)        /* == CPU_MODE_USER */
 #define CPU_PAGE_READ_DATA      (CPU_PAGE_READ|CPU_PAGE_DATA)  #define CPU_PAGE_READ_CODE      (CPU_PAGE_CODE)
   #define CPU_PAGE_READ_DATA      (CPU_PAGE_DATA)
 #define CPU_PAGE_WRITE_DATA     (CPU_PAGE_WRITE|CPU_PAGE_DATA)  #define CPU_PAGE_WRITE_DATA     (CPU_PAGE_WRITE|CPU_PAGE_DATA)
   
   #if defined(IA32_PAGING_EACHSIZE)
   
   UINT8 MEMCALL cpu_memory_access_la_RMW_b(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg) GCC_ATTR_REGPARM;
   UINT16 MEMCALL cpu_memory_access_la_RMW_w(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg) GCC_ATTR_REGPARM;
   UINT32 MEMCALL cpu_memory_access_la_RMW_d(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg) GCC_ATTR_REGPARM;
   UINT8 MEMCALL cpu_linear_memory_read_b(UINT32 laddr, const int ucrw) GCC_ATTR_REGPARM;
   UINT16 MEMCALL cpu_linear_memory_read_w(UINT32 laddr, const int ucrw) GCC_ATTR_REGPARM;
   UINT32 MEMCALL cpu_linear_memory_read_d(UINT32 laddr, const int ucrw) GCC_ATTR_REGPARM;
   void MEMCALL cpu_linear_memory_write_b(UINT32 laddr, UINT8 value, const int user_mode) GCC_ATTR_REGPARM;
   void MEMCALL cpu_linear_memory_write_w(UINT32 laddr, UINT16 value, const int user_mode) GCC_ATTR_REGPARM;
   void MEMCALL cpu_linear_memory_write_d(UINT32 laddr, UINT32 value, const int user_mode) GCC_ATTR_REGPARM;
   
 #define cpu_lmemoryread(a,pl) \  #define cpu_lmemoryread(a,pl) \
         (!CPU_STAT_PAGING) ? \          (!CPU_STAT_PAGING) ? \
          cpu_memoryread(a) : \           cpu_memoryread(a) : \
          (BYTE)cpu_linear_memory_read(a,1,CPU_PAGE_READ_DATA,pl)           cpu_linear_memory_read_b(a,CPU_PAGE_READ_DATA | (pl))
   #define cpu_lmemoryread_b(a,pl) cpu_lmemoryread(a,pl)
 #define cpu_lmemoryread_w(a,pl) \  #define cpu_lmemoryread_w(a,pl) \
         (!CPU_STAT_PAGING) ? \          (!CPU_STAT_PAGING) ? \
          cpu_memoryread_w(a) : \           cpu_memoryread_w(a) : \
          (WORD)cpu_linear_memory_read(a,2,CPU_PAGE_READ_DATA,pl)           cpu_linear_memory_read_w(a,CPU_PAGE_READ_DATA | (pl))
 #define cpu_lmemoryread_d(a,pl) \  #define cpu_lmemoryread_d(a,pl) \
         (!CPU_STAT_PAGING) ? \          (!CPU_STAT_PAGING) ? \
          cpu_memoryread_d(a) : \           cpu_memoryread_d(a) : \
          cpu_linear_memory_read(a,4,CPU_PAGE_READ_DATA,pl)           cpu_linear_memory_read_d(a,CPU_PAGE_READ_DATA | (pl))
   
 #define cpu_lmemorywrite(a,v,pl) \  #define cpu_lmemorywrite(a,v,pl) \
         (!CPU_STAT_PAGING) ? \          (!CPU_STAT_PAGING) ? \
          cpu_memorywrite(a,v) : \           cpu_memorywrite(a,v) : cpu_linear_memory_write_b(a,v,pl)
          cpu_linear_memory_write(a,v,1,pl)  #define cpu_lmemorywrite_b(a,v,pl) cpu_lmemorywrite(a,v,pl)
 #define cpu_lmemorywrite_w(a,v,pl) \  #define cpu_lmemorywrite_w(a,v,pl) \
         (!CPU_STAT_PAGING) ? \          (!CPU_STAT_PAGING) ? \
          cpu_memorywrite_w(a,v) : \           cpu_memorywrite_w(a,v) : cpu_linear_memory_write_w(a,v,pl)
          cpu_linear_memory_write(a,v,2,pl)  
 #define cpu_lmemorywrite_d(a,v,pl) \  #define cpu_lmemorywrite_d(a,v,pl) \
         (!CPU_STAT_PAGING) ? \          (!CPU_STAT_PAGING) ? \
          cpu_memorywrite_d(a,v) : \           cpu_memorywrite_d(a,v) : cpu_linear_memory_write_d(a,v,pl)
          cpu_linear_memory_write(a,v,4,pl)  
   
 /*  #else   /* !IA32_PAGING_EACHSIZE */
  * code segment  
  */  UINT32 MEMCALL cpu_memory_access_la_RMW(UINT32 laddr, UINT length, UINT32 (*func)(UINT32, void *), void *arg) GCC_ATTR_REGPARM;
 #define cpu_lcmemoryread(a) \  #define cpu_memory_access_la_RMW_b(l,f,a) cpu_memory_access_la_RMW(l,1,f,a)
   #define cpu_memory_access_la_RMW_w(l,f,a) cpu_memory_access_la_RMW(l,2,f,a)
   #define cpu_memory_access_la_RMW_d(l,f,a) cpu_memory_access_la_RMW(l,4,f,a)
   
   UINT32 MEMCALL cpu_linear_memory_read(UINT32 address, UINT length, const int ucrw) GCC_ATTR_REGPARM;
   #define cpu_linear_memory_read_b(a,pl) cpu_linear_memory_read(a,1,pl)
   #define cpu_linear_memory_read_w(a,pl) cpu_linear_memory_read(a,2,pl)
   #define cpu_linear_memory_read_d(a,pl) cpu_linear_memory_read(a,4,pl)
   
   void MEMCALL cpu_linear_memory_write(UINT32 address, UINT32 value, UINT length, const int user_mode) GCC_ATTR_REGPARM;
   #define cpu_linear_memory_write_b(a,v,pl) cpu_linear_memory_write(a,v,1,pl)
   #define cpu_linear_memory_write_w(a,v,pl) cpu_linear_memory_write(a,v,2,pl)
   #define cpu_linear_memory_write_d(a,v,pl) cpu_linear_memory_write(a,v,4,pl)
   
   #define cpu_lmemoryread(a,pl) \
         (!CPU_STAT_PAGING) ? \          (!CPU_STAT_PAGING) ? \
          cpu_memoryread(a) : \           cpu_memoryread(a) : \
          (BYTE)cpu_linear_memory_read(a,1,CPU_PAGE_READ_CODE,CPU_STAT_USER_MODE)           (UINT8)cpu_linear_memory_read(a,1,CPU_PAGE_READ_DATA | (pl))
 #define cpu_lcmemoryread_w(a) \  #define cpu_lmemoryread_b(a,pl) cpu_lmemoryread(a,pl)
   #define cpu_lmemoryread_w(a,pl) \
         (!CPU_STAT_PAGING) ? \          (!CPU_STAT_PAGING) ? \
          cpu_memoryread_w(a) : \           cpu_memoryread_w(a) : \
          (WORD)cpu_linear_memory_read(a,2,CPU_PAGE_READ_CODE,CPU_STAT_USER_MODE)           (UINT16)cpu_linear_memory_read(a,2,CPU_PAGE_READ_DATA | (pl))
 #define cpu_lcmemoryread_d(a) \  #define cpu_lmemoryread_d(a,pl) \
         (!CPU_STAT_PAGING) ? \          (!CPU_STAT_PAGING) ? \
          cpu_memoryread_d(a) : \           cpu_memoryread_d(a) : \
          cpu_linear_memory_read(a,4,CPU_PAGE_READ_CODE,CPU_STAT_USER_MODE)           cpu_linear_memory_read(a,4,CPU_PAGE_READ_DATA | (pl))
   
   #define cpu_lmemorywrite(a,v,pl) \
           (!CPU_STAT_PAGING) ? \
            cpu_memorywrite(a,v) : \
            cpu_linear_memory_write(a,v,1,pl)
   #define cpu_lmemorywrite_b(a,v,pl) cpu_lmemorywrite(a,v,pl)
   #define cpu_lmemorywrite_w(a,v,pl) \
           (!CPU_STAT_PAGING) ? \
            cpu_memorywrite_w(a,v) : \
            cpu_linear_memory_write(a,v,2,pl)
   #define cpu_lmemorywrite_d(a,v,pl) \
           (!CPU_STAT_PAGING) ? \
            cpu_memorywrite_d(a,v) : \
            cpu_linear_memory_write(a,v,4,pl)
   
   #endif  /* IA32_PAGING_EACHSIZE */
   
 /*  /*
  * linear address memory access with superviser mode   * linear address memory access with superviser mode
Line 207  do { \ Line 250  do { \
 /*  /*
  * TLB function   * TLB function
  */   */
   typedef struct {
           UINT32  tag;    /* linear address */
   #define TLB_ENTRY_TAG_VALID             (1 << 0)
   /*      pde & pte & CPU_PTE_WRITABLE    (1 << 1)        */
   /*      pde & pte & CPU_PTE_USER_MODE   (1 << 2)        */
   #define TLB_ENTRY_TAG_DIRTY             CPU_PTE_DIRTY           /* (1 << 6) */
   #define TLB_ENTRY_TAG_GLOBAL            CPU_PTE_GLOBAL_PAGE     /* (1 << 8) */
   #define TLB_ENTRY_TAG_MAX_SHIFT         12
   
           UINT32  paddr;  /* physical address */
   
           UINT8   *memp;  /* shortcut for pre-fetch queue */
   } TLB_ENTRY_T;
   
   
 #if defined(IA32_SUPPORT_TLB)  #if defined(IA32_SUPPORT_TLB)
 void tlb_init();  void tlb_init(void);
 void tlb_flush(BOOL allflush);  void MEMCALL tlb_flush(BOOL allflush) GCC_ATTR_REGPARM;
 void tlb_flush_page(DWORD vaddr);  void MEMCALL tlb_flush_page(UINT32 laddr) GCC_ATTR_REGPARM;
   TLB_ENTRY_T* MEMCALL tlb_lookup(const UINT32 laddr, const int ucrw) GCC_ATTR_REGPARM;
 #else  #else
 #define tlb_init()  #define tlb_init()
 #define tlb_flush(allflush)     (void)allflush  #define tlb_flush(allflush)     (void)(allflush)
 #define tlb_flush_page(vaddr)   (void)vaddr  #define tlb_flush_page(la)      (void)(la)
   #define tlb_lookup(la, ucrw)    NULL
 #endif  #endif
   
 #ifdef __cplusplus  #ifdef __cplusplus
Removed from v.1.8  
changed lines
  Added in v.1.18

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