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| version 1.19, 2005/03/05 16:47:04 | version 1.27, 2011/12/29 13:32:12 |
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| Line 1 | Line 1 |
| /* $Id$ */ | |
| /* | /* |
| * Copyright (c) 2003 NONAKA Kimihiro | * Copyright (c) 2003 NONAKA Kimihiro |
| * All rights reserved. | * All rights reserved. |
| Line 12 | Line 10 |
| * 2. Redistributions in binary form must reproduce the above copyright | * 2. Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the | * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. | * documentation and/or other materials provided with the distribution. |
| * 3. The name of the author may not be used to endorse or promote products | |
| * derived from this software without specific prior written permission. | |
| * | * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| Line 35 extern "C" { | Line 31 extern "C" { |
| #endif | #endif |
| /* | /* |
| * ¥Ú¡¼¥¸¡¦¥Ç¥£¥ì¥¯¥È¥ê¡¦¥¨¥ó¥È¥ê (4K ¥Ð¥¤¥È¥Ú¡¼¥¸»ÈÍÑ»þ) | * ¥Ú¡¼¥¸¡¦¥Ç¥£¥ì¥¯¥È¥ê¡¦¥¨¥ó¥È¥ê (4K ¥Ð¥¤¥È¥Ú¡¼¥¸»ÈÍÑ»þ) |
| * | * |
| * 31 12 11 9 8 7 6 5 4 3 2 1 0 | * 31 12 11 9 8 7 6 5 4 3 2 1 0 |
| * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+ | * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+ |
| * | ¡¦¥ì¡£¥·¡¦¥¯¡£¥ò¡¦¥Ë¡£¥·¡¦¥è¡¦ö¦¥Û¡¦¥ë¡£¥·¡¦¥±¡£¥ò¡¦¡Ö¡¦¥Î¡¦ø§¥± |¥µ¥Í¥Ø¥à¥¤¥È|G|PS|-|A|PCD|PWT|U/S|R/W|P| | * | åãÔ妾å⥯å㥵åã¬å¦¾åãÌå¦åá¥çåãÒ妾å⥱å㥵åâ¡Öåã²å¦®å⥱ |è¿¥½íô¥£éï¥Ã|G|PS|-|A|PCD|PWT|U/S|R/W|P| |
| * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+ | * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+ |
| * | | | | | | | | | | | * | | | | | | | | | | |
| * 9-11: ¡¦¥¡¦¥±¡¦¥Ë¡¦à£¥ò¡¦¥é¡¦ú§¡¼¡¦ò§¡«¡¢¥ã¥µ¥Í¥Ø¥à¥¤¥È¥Ì¥¹ --------+ | | | | | | | | | | * 9-11: ¥·¥¹¥Æ¥à¡¦¥×¥í¥°¥é¥Þ¤¬»ÈÍѲÄǽ --------+ | | | | | | | | | |
| * 8: ¡¦¡¼¡¦ú£¥·¡¦¥ß¡¦ö£¥ò¡¦¥ì¡£¥·¡¦¥¯(¥Õ¥ª¥µö¦¥ª¡¢ø¦ ------------+ | | | | | | | | | * 8: ¥°¥í¡¼¥Ð¥ë¡¦¥Ú¡¼¥¸(̵»ë¤µ¤ì¤ë) ------------+ | | | | | | | | |
| * 7: ¥Ú¡¼¥¸¡¦¥µ¥¤¥º (0 = 4k ¥Ð¥¤¥È¥Ú¡¼¥¸) ---------+ | | | | | | | | * 7: ¥Ú¡¼¥¸¡¦¥µ¥¤¥º (0 = 4k ¥Ð¥¤¥È¥Ú¡¼¥¸) ---------+ | | | | | | | |
| * 6: ͽÌó (-) ---------------------------------------+ | | | | | | | * 6: ͽÌó (-) ---------------------------------------+ | | | | | | |
| * 5: ¥¢¥¯¥»¥¹ -----------------------------------------+ | | | | | | * 5: ¥¢¥¯¥»¥¹ -----------------------------------------+ | | | | | |
| * 4: ¥¥ã¥Ã¥·¥å̵¸ú --------------------------------------+ | | | | | * 4: ¥¥ã¥Ã¥·¥å̵¸ú --------------------------------------+ | | | | |
| * 3: ¥é¥¤¥È¥¹¥ë¡¼ --------------------------------------------+ | | | | * 3: ¥é¥¤¥È¥¹¥ë¡¼ --------------------------------------------+ | | | |
| * 2: ¥æ¡¼¥¶¡¿¥¹¡¼¥Ñ¥Ð¥¤¥¶ (0 = ¥¹¡¼¥Ñ¥Ð¥¤¥¶) ---------------------+ | | | * 2: ¥æ¡¼¥¶¡¿¥¹¡¼¥Ñ¥Ð¥¤¥¶ (0 = ¥¹¡¼¥Ñ¥Ð¥¤¥¶) ---------------------+ | | |
| * 1: ÆÉ¤ß¼è¤ê¡¿½ñ¤¹þ¤ß (0 = ÆÉ¤ß¼è¤ê¤Î¤ß) ---------------------------+ | | * 1: ÆÉ¤ß¼è¤ê¡¿½ñ¤¹þ¤ß (0 = ÆÉ¤ß¼è¤ê¤Î¤ß) ---------------------------+ | |
| * 0: ¥Ú¡¼¥¸Â¸ºß ---------------------------------------------------------+ | * 0: ¥Ú¡¼¥¸Â¸ºß ---------------------------------------------------------+ |
| */ | */ |
| #define CPU_PDE_BASEADDR_MASK 0xfffff000 | #define CPU_PDE_BASEADDR_MASK 0xfffff000 |
| #define CPU_PDE_GLOBAL_PAGE (1 << 8) | #define CPU_PDE_GLOBAL_PAGE (1 << 8) |
| Line 65 extern "C" { | Line 61 extern "C" { |
| #define CPU_PDE_PRESENT (1 << 0) | #define CPU_PDE_PRESENT (1 << 0) |
| /* | /* |
| * ¥Ú¡¼¥¸¡¦¥Ç¥£¥ì¥¯¥È¥ê¡¦¥¨¥ó¥È¥ê (4M ¥Ð¥¤¥È¥Ú¡¼¥¸»ÈÍÑ»þ) | * ¥Ú¡¼¥¸¡¦¥Ç¥£¥ì¥¯¥È¥ê¡¦¥¨¥ó¥È¥ê (4M ¥Ð¥¤¥È¥Ú¡¼¥¸»ÈÍÑ»þ) |
| * | * |
| * 31 22 21 12 11 9 8 7 6 5 4 3 2 1 0 | * 31 22 21 12 11 9 8 7 6 5 4 3 2 1 0 |
| * +----------------------------+-----------+------+-+--+-+-+---+---+---+---+-+ | * +----------------------------+-----------+------+-+--+-+-+---+---+---+---+-+ |
| * |¥Ú¡¼¥¸¥Æ¡¼¥Ö¥ë¤ÎʪÍý¥¢¥É¥ì¥¹| ͽÌóºÑ¤ß |»ÈÍѲÄ|G|PS|D|A|PCD|PWT|U/S|R/W|P| | * |åãÔ妾å⥯åã¬å¦¾åãÌå¦åá¥çí饥íð¬å¤¤åã²å¦®å⥱| 輰饨¨è¥¯°å¢Á |è¿¥½íô¥£éï¥Ã|G|PS|D|A|PCD|PWT|U/S|R/W|P| |
| * +----------------------------+-----------+------+-+--+-+-+---+---+---+---+-+ | * +----------------------------+-----------+------+-+--+-+-+---+---+---+---+-+ |
| * | | | | | | | | | | | * | | | | | | | | | | |
| * 9-11: ¡¦¥¡¦¥±¡¦¥Ë¡¦à£¥ò¡¦¥é¡¦ú§¡¼¡¦ò§¡«¡¢¥ã¥µ¥Í¥Ø¥à¥¤¥È¥Ì¥¹ --------+ | | | | | | | | | | * 9-11: ¥·¥¹¥Æ¥à¡¦¥×¥í¥°¥é¥Þ¤¬»ÈÍѲÄǽ --------+ | | | | | | | | | |
| * 8: ¡¦¡¼¡¦ú£¥·¡¦¥ß¡¦ö£¥ò¡¦¥ì¡£¥·¡¦¥¯ ------------------------+ | | | | | | | | | * 8: ¥°¥í¡¼¥Ð¥ë¡¦¥Ú¡¼¥¸ ------------------------+ | | | | | | | | |
| * 7: ¡¦¥ì¡£¥·¡¦¥¯¡£¥ò¡¦¥ª¡¦¡¢¡¦¥³ (1 = 4M ¡¦¥ß¡¦¡¢¡¦¥Í¡¦¥ì¡£¥·¡¦¥¯) ---------+ | | | | | | | | * 7: ¥Ú¡¼¥¸¡¦¥µ¥¤¥º (1 = 4M ¥Ð¥¤¥È¥Ú¡¼¥¸) ---------+ | | | | | | | |
| * 6: ¡¦¥¿¡£¥·¡¦¥Ë¡¦¡× ---------------------------------------+ | | | | | | | * 6: ¥À¡¼¥Æ¥£ ---------------------------------------+ | | | | | | |
| * 5: ¡¦¡Ö¡¦¥Ã¡¦¥µ¡¦¥± -----------------------------------------+ | | | | | | * 5: ¥¢¥¯¥»¥¹ -----------------------------------------+ | | | | | |
| * 4: ¡¦¥å¡¦æ§¥Æ¡¦¥¡¦êÎ¥ª¥¯--------------------------------------+ | | | | | * 4: ¥¥ã¥Ã¥·¥å̵¸ú --------------------------------------+ | | | | |
| * 3: ¡¦ò§¡¢¡¦¥Í¡¦¥±¡¦ö£¥· --------------------------------------------+ | | | | * 3: ¥é¥¤¥È¥¹¥ë¡¼ --------------------------------------------+ | | | |
| * 2: ¡¦ì£¥·¡¦¥«¡£¥½¡¦¥±¡£¥·¡¦¥à¡¦¥ß¡¦¡¢¡¦¥« (0 = ¡¦¥±¡£¥·¡¦¥à¡¦¥ß¡¦¡¢¡¦¥«) ---------------------+ | | | * 2: ¥æ¡¼¥¶¡¿¥¹¡¼¥Ñ¥Ð¥¤¥¶ (0 = ¥¹¡¼¥Ñ¥Ð¥¤¥¶) ---------------------+ | | |
| * 1: ¥Ë¥Î¡¢¡¬¥·ð¦ô£¥½¥¹ñ¤¹þ¤(0 = ÆÉ¤ß¼è¤ê¤Î¤ß) ---------------------------+ | | * 1: ÆÉ¤ß¼è¤ê¡¿½ñ¤¹þ¤ß (0 = ÆÉ¤ß¼è¤ê¤Î¤ß) ---------------------------+ | |
| * 0: ¥Ú¡¼¥¸Â¸ºß ---------------------------------------------------------+ | * 0: ¥Ú¡¼¥¸Â¸ºß ---------------------------------------------------------+ |
| */ | */ |
| #define CPU_PDE_4M_BASEADDR_MASK 0xffc00000 | #define CPU_PDE_4M_BASEADDR_MASK 0xffc00000 |
| #define CPU_PDE_4M_GLOBAL_PAGE (1 << 8) | #define CPU_PDE_4M_GLOBAL_PAGE (1 << 8) |
| Line 95 extern "C" { | Line 91 extern "C" { |
| #define CPU_PDE_4M_PRESENT (1 << 0) | #define CPU_PDE_4M_PRESENT (1 << 0) |
| /* | /* |
| * ¥Ú¡¼¥¸¡¦¥Æ¡¼¥Ö¥ë¡¦¥¨¥ó¥È¥ê (4k ¥Ð¥¤¥È¡¦¥Ú¡¼¥¸) | * åãÔ妾å⥯å㥵åã¬å¦¾åãÌå¦å㥵å⥣å㥦åã°å¦¬ (4k åãÀ夦åã°å¦½åãÔ妾å⥯) |
| * | * |
| * 31 12 11 9 8 7 6 5 4 3 2 1 0 | * 31 12 11 9 8 7 6 5 4 3 2 1 0 |
| * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+ | * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+ |
| * | ¡¦¥ì¡£¥·¡¦¥¯¡¢¥Û¡¦¥ë¡£¥·¡¦¥±¡£¥ò¡¦¡Ö¡¦¥Î¡¦ø§¥± |¥µ¥Í¥Ø¥à¥¤¥È|G|-|D|A|PCD|PWT|U/S|R/W|P| | * | åãÔ妾å⥯åá¥çåãÒ妾å⥱å㥵åâ¡Öåã²å¦®å⥱ |è¿¥½íô¥£éï¥Ã|G|-|D|A|PCD|PWT|U/S|R/W|P| |
| * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+ | * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+ |
| * | | | | | | | | | | | * | | | | | | | | | | |
| * 9-11: ¡¦¥¡¦¥±¡¦¥Ë¡¦à£¥ò¡¦¥é¡¦ú§¡¼¡¦ò§¡«¡¢¥ã¥µ¥Í¥Ø¥à¥¤¥È¥Ì¥¹ -------+ | | | | | | | | | | * 9-11: ¥·¥¹¥Æ¥à¡¦¥×¥í¥°¥é¥Þ¤¬»ÈÍѲÄǽ -------+ | | | | | | | | | |
| * 8: ¡¦¡¼¡¦ú£¥·¡¦¥ß¡¦ö£¥ò¡¦¥ì¡£¥·¡¦¥¯ -----------------------+ | | | | | | | | | * 8: ¥°¥í¡¼¥Ð¥ë¡¦¥Ú¡¼¥¸ -----------------------+ | | | | | | | | |
| * 7: ¥Ø¥¹¥Õ(-) -----------------------------------+ | | | | | | | | * 7: ͽÌó (-) -----------------------------------+ | | | | | | | |
| * 6: ¥À¡¼¥Æ¥£ -------------------------------------+ | | | | | | | * 6: ¥À¡¼¥Æ¥£ -------------------------------------+ | | | | | | |
| * 5: ¥¢¥¯¥»¥¹ ---------------------------------------+ | | | | | | * 5: ¥¢¥¯¥»¥¹ ---------------------------------------+ | | | | | |
| * 4: ¥¥ã¥Ã¥·¥å̵¸ú ------------------------------------+ | | | | | * 4: ¥¥ã¥Ã¥·¥å̵¸ú ------------------------------------+ | | | | |
| * 3: ¥é¥¤¥È¥¹¥ë¡¼ ------------------------------------------+ | | | | * 3: ¥é¥¤¥È¥¹¥ë¡¼ ------------------------------------------+ | | | |
| * 2: ¥æ¡¼¥¶¡¿¥¹¡¼¥Ñ¥Ð¥¤¥¶ (0 = ¥¹¡¼¥Ñ¥Ð¥¤¥¶) -------------------+ | | | * 2: ¥æ¡¼¥¶¡¿¥¹¡¼¥Ñ¥Ð¥¤¥¶ (0 = ¥¹¡¼¥Ñ¥Ð¥¤¥¶) -------------------+ | | |
| * 1: ÆÉ¤ß¼è¤ê¡¿½ñ¤¹þ¤ß (0 = ÆÉ¤ß¼è¤ê¤Î¤ß) -------------------------+ | | * 1: ÆÉ¤ß¼è¤ê¡¿½ñ¤¹þ¤ß (0 = ÆÉ¤ß¼è¤ê¤Î¤ß) -------------------------+ | |
| * 0: ¥Ú¡¼¥¸Â¸ºß -------------------------------------------------------+ | * 0: ¥Ú¡¼¥¸Â¸ºß -------------------------------------------------------+ |
| */ | */ |
| #define CPU_PTE_BASEADDR_MASK 0xfffff000 | #define CPU_PTE_BASEADDR_MASK 0xfffff000 |
| #define CPU_PTE_GLOBAL_PAGE (1 << 8) | #define CPU_PTE_GLOBAL_PAGE (1 << 8) |
| Line 128 extern "C" { | Line 124 extern "C" { |
| /* | /* |
| * linear address memory access function | * linear address memory access function |
| */ | */ |
| void MEMCALL cpu_memory_access_la_region(UINT32 address, UINT length, const int ucrw, BYTE *data); | void MEMCALL cpu_memory_access_la_region(UINT32 address, UINT length, const int ucrw, UINT8 *data); |
| void MEMCALL paging_check(UINT32 laddr, UINT length, const int ucrw); | UINT32 MEMCALL laddr2paddr(const UINT32 laddr, const int ucrw); |
| #define laddr_to_paddr(laddr, ucrw) \ | |
| (!CPU_STAT_PAGING) ? (laddr) : (laddr2paddr((laddr), (ucrw))) | |
| /* ucrw */ | /* ucrw */ |
| #define CPU_PAGE_WRITE (1 << 0) | #define CPU_PAGE_WRITE (1 << 0) |
| Line 140 void MEMCALL paging_check(UINT32 laddr, | Line 139 void MEMCALL paging_check(UINT32 laddr, |
| #define CPU_PAGE_READ_DATA (CPU_PAGE_DATA) | #define CPU_PAGE_READ_DATA (CPU_PAGE_DATA) |
| #define CPU_PAGE_WRITE_DATA (CPU_PAGE_WRITE|CPU_PAGE_DATA) | #define CPU_PAGE_WRITE_DATA (CPU_PAGE_WRITE|CPU_PAGE_DATA) |
| UINT8 MEMCALL cpu_memory_access_la_RMW_b(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg) GCC_ATTR_REGPARM; | UINT8 MEMCALL cpu_memory_access_la_RMW_b(UINT32 laddr, UINT32 (CPUCALL *func)(UINT32, void *), void *arg); |
| UINT16 MEMCALL cpu_memory_access_la_RMW_w(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg) GCC_ATTR_REGPARM; | UINT16 MEMCALL cpu_memory_access_la_RMW_w(UINT32 laddr, UINT32 (CPUCALL *func)(UINT32, void *), void *arg); |
| UINT32 MEMCALL cpu_memory_access_la_RMW_d(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg) GCC_ATTR_REGPARM; | UINT32 MEMCALL cpu_memory_access_la_RMW_d(UINT32 laddr, UINT32 (CPUCALL *func)(UINT32, void *), void *arg); |
| UINT8 MEMCALL cpu_linear_memory_read_b(UINT32 laddr, const int ucrw) GCC_ATTR_REGPARM; | UINT8 MEMCALL cpu_linear_memory_read_b(UINT32 laddr, const int ucrw); |
| UINT16 MEMCALL cpu_linear_memory_read_w(UINT32 laddr, const int ucrw) GCC_ATTR_REGPARM; | UINT16 MEMCALL cpu_linear_memory_read_w(UINT32 laddr, const int ucrw); |
| UINT32 MEMCALL cpu_linear_memory_read_d(UINT32 laddr, const int ucrw) GCC_ATTR_REGPARM; | UINT32 MEMCALL cpu_linear_memory_read_d(UINT32 laddr, const int ucrw); |
| UINT64 MEMCALL cpu_linear_memory_read_q(UINT32 laddr, const int ucrw) GCC_ATTR_REGPARM; | UINT64 MEMCALL cpu_linear_memory_read_q(UINT32 laddr, const int ucrw); |
| REG80 MEMCALL cpu_linear_memory_read_f(UINT32 laddr, const int ucrw) GCC_ATTR_REGPARM; | REG80 MEMCALL cpu_linear_memory_read_f(UINT32 laddr, const int ucrw); |
| void MEMCALL cpu_linear_memory_write_b(UINT32 laddr, UINT8 value, const int user_mode) GCC_ATTR_REGPARM; | void MEMCALL cpu_linear_memory_write_b(UINT32 laddr, UINT8 value, const int user_mode); |
| void MEMCALL cpu_linear_memory_write_w(UINT32 laddr, UINT16 value, const int user_mode) GCC_ATTR_REGPARM; | void MEMCALL cpu_linear_memory_write_w(UINT32 laddr, UINT16 value, const int user_mode); |
| void MEMCALL cpu_linear_memory_write_d(UINT32 laddr, UINT32 value, const int user_mode) GCC_ATTR_REGPARM; | void MEMCALL cpu_linear_memory_write_d(UINT32 laddr, UINT32 value, const int user_mode); |
| void MEMCALL cpu_linear_memory_write_q(UINT32 laddr, UINT64 value, const int user_mode) GCC_ATTR_REGPARM; | void MEMCALL cpu_linear_memory_write_q(UINT32 laddr, UINT64 value, const int user_mode); |
| void MEMCALL cpu_linear_memory_write_f(UINT32 laddr, const REG80 *value, const int user_mode) GCC_ATTR_REGPARM; | void MEMCALL cpu_linear_memory_write_f(UINT32 laddr, const REG80 *value, const int user_mode); |
| #define cpu_lmemoryread(a,pl) \ | #define cpu_lmemoryread(a,pl) \ |
| (!CPU_STAT_PAGING) ? \ | (!CPU_STAT_PAGING) ? \ |
| Line 198 void MEMCALL cpu_linear_memory_write_f(U | Line 197 void MEMCALL cpu_linear_memory_write_f(U |
| /* | /* |
| * CR3 (Page Directory Entry base physical address) | |
| */ | |
| #define set_CR3(cr3) \ | |
| do { \ | |
| VERBOSE(("set_CR3: old = %08x, new = 0x%08x", CPU_CR3, (cr3) & CPU_CR3_MASK)); \ | |
| CPU_CR3 = (cr3) & CPU_CR3_MASK; \ | |
| CPU_STAT_PDE_BASE = CPU_CR3 & CPU_CR3_PD_MASK; \ | |
| tlb_flush(FALSE); \ | |
| } while (/*CONSTCOND*/ 0) | |
| /* | |
| * TLB function | * TLB function |
| */ | */ |
| typedef struct { | typedef struct { |
| Line 226 typedef struct { | Line 213 typedef struct { |
| UINT8 *memp; /* shortcut for pre-fetch queue */ | UINT8 *memp; /* shortcut for pre-fetch queue */ |
| } TLB_ENTRY_T; | } TLB_ENTRY_T; |
| #if defined(IA32_SUPPORT_TLB) | |
| void tlb_init(void); | void tlb_init(void); |
| void MEMCALL tlb_flush(BOOL allflush) GCC_ATTR_REGPARM; | void MEMCALL tlb_flush(BOOL allflush); |
| void MEMCALL tlb_flush_page(UINT32 laddr) GCC_ATTR_REGPARM; | void MEMCALL tlb_flush_page(UINT32 laddr); |
| TLB_ENTRY_T* MEMCALL tlb_lookup(const UINT32 laddr, const int ucrw) GCC_ATTR_REGPARM; | TLB_ENTRY_T* MEMCALL tlb_lookup(const UINT32 laddr, const int ucrw); |
| #else | |
| #define tlb_init() | |
| #define tlb_flush(allflush) (void)(allflush) | |
| #define tlb_flush_page(la) (void)(la) | |
| #define tlb_lookup(la, ucrw) NULL | |
| #endif | |
| #ifdef __cplusplus | #ifdef __cplusplus |
| } | } |