[BACK]Return to paging.h CVS log [TXT] [DIR] Up to [RetroPC.NET] / np2 / i386c / ia32

Diff for /np2/i386c/ia32/paging.h between versions 1.5 and 1.24

version 1.5, 2004/01/27 15:56:57 version 1.24, 2011/01/15 18:36:12
Line 1 Line 1
 /*      $Id$    */  
   
 /*  /*
  * Copyright (c) 2003 NONAKA Kimihiro   * Copyright (c) 2003 NONAKA Kimihiro
  * All rights reserved.   * All rights reserved.
Line 12 Line 10
  * 2. Redistributions in binary form must reproduce the above copyright   * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the   *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.   *    documentation and/or other materials provided with the distribution.
  * 3. The name of the author may not be used to endorse or promote products  
  *    derived from this software without specific prior written permission.  
  *   *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR   * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES   * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
Line 39  extern "C" { Line 35  extern "C" {
  *   *
  *  31                                    12 11   9 8  7 6 5  4   3   2   1  0    *  31                                    12 11   9 8  7 6 5  4   3   2   1  0 
  * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+   * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+
  * |   ページ・テーブルのベース・アドレス   |使用可|G|PS|0|A|PCD|PWT|U/S|R/W|P|   * |   ページ・テーブルのベース・アドレス   |使用可|G|PS|-|A|PCD|PWT|U/S|R/W|P|
  * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+   * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+
  *                                              |   |  | | |  |   |   |   |  |   *                                              |   |  | | |  |   |   |   |  |
  * 9-11: システム・プログラマが使用可能 --------+   |  | | |  |   |   |   |  |   * 9-11: システム・プログラマが使用可能 --------+   |  | | |  |   |   |   |  |
  *    8: グローバル・ページ(無視される) ------------+  | | |  |   |   |   |  |   *    8: グローバル・ページ(無視される) ------------+  | | |  |   |   |   |  |
  *    7: ページ・サイズ (0 = 4k バイトページ) ---------+ | |  |   |   |   |  |   *    7: ページ・サイズ (0 = 4k バイトページ) ---------+ | |  |   |   |   |  |
  *    6: 予約 (0) ---------------------------------------+ |  |   |   |   |  |   *    6: 予約 (-) ---------------------------------------+ |  |   |   |   |  |
  *    5: アクセス -----------------------------------------+  |   |   |   |  |   *    5: アクセス -----------------------------------------+  |   |   |   |  |
  *    4: キャッシュ無効 --------------------------------------+   |   |   |  |   *    4: キャッシュ無効 --------------------------------------+   |   |   |  |
  *    3: ライトスルー --------------------------------------------+   |   |  |   *    3: ライトスルー --------------------------------------------+   |   |  |
Line 54  extern "C" { Line 50  extern "C" {
  *    0: ページ存在 ---------------------------------------------------------+   *    0: ページ存在 ---------------------------------------------------------+
  */   */
 #define CPU_PDE_BASEADDR_MASK   0xfffff000  #define CPU_PDE_BASEADDR_MASK   0xfffff000
   #define CPU_PDE_GLOBAL_PAGE     (1 << 8)
 #define CPU_PDE_PAGE_SIZE       (1 << 7)  #define CPU_PDE_PAGE_SIZE       (1 << 7)
   #define CPU_PDE_DIRTY           (1 << 6)
 #define CPU_PDE_ACCESS          (1 << 5)  #define CPU_PDE_ACCESS          (1 << 5)
 #define CPU_PDE_CACHE_DISABLE   (1 << 4)  #define CPU_PDE_CACHE_DISABLE   (1 << 4)
 #define CPU_PDE_WRITE_THROUGH   (1 << 3)  #define CPU_PDE_WRITE_THROUGH   (1 << 3)
Line 97  extern "C" { Line 95  extern "C" {
  *   *
  *  31                                    12 11   9 8 7 6 5  4   3   2   1  0    *  31                                    12 11   9 8 7 6 5  4   3   2   1  0 
  * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+   * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+
  * |        ページのベース・アドレス        |使用可|G|0|D|A|PCD|PWT|U/S|R/W|P|   * |        ページのベース・アドレス        |使用可|G|-|D|A|PCD|PWT|U/S|R/W|P|
  * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+   * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+
  *                                              |   | | | |  |   |   |   |  |   *                                              |   | | | |  |   |   |   |  |
  *  9-11: システム・プログラマが使用可能 -------+   | | | |  |   |   |   |  |   *  9-11: システム・プログラマが使用可能 -------+   | | | |  |   |   |   |  |
  *     8: グローバル・ページ -----------------------+ | | |  |   |   |   |  |   *     8: グローバル・ページ -----------------------+ | | |  |   |   |   |  |
  *     7: 予約 (0) -----------------------------------+ | |  |   |   |   |  |   *     7: 予約 (-) -----------------------------------+ | |  |   |   |   |  |
  *     6: ダーティ -------------------------------------+ |  |   |   |   |  |   *     6: ダーティ -------------------------------------+ |  |   |   |   |  |
  *     5: アクセス ---------------------------------------+  |   |   |   |  |   *     5: アクセス ---------------------------------------+  |   |   |   |  |
  *     4: キャッシュ無効 ------------------------------------+   |   |   |  |   *     4: キャッシュ無効 ------------------------------------+   |   |   |  |
Line 113  extern "C" { Line 111  extern "C" {
  */   */
 #define CPU_PTE_BASEADDR_MASK   0xfffff000  #define CPU_PTE_BASEADDR_MASK   0xfffff000
 #define CPU_PTE_GLOBAL_PAGE     (1 << 8)  #define CPU_PTE_GLOBAL_PAGE     (1 << 8)
   #define CPU_PTE_PAGE_SIZE       (1 << 7)
 #define CPU_PTE_DIRTY           (1 << 6)  #define CPU_PTE_DIRTY           (1 << 6)
 #define CPU_PTE_ACCESS          (1 << 5)  #define CPU_PTE_ACCESS          (1 << 5)
 #define CPU_PTE_CACHE_DISABLE   (1 << 4)  #define CPU_PTE_CACHE_DISABLE   (1 << 4)
Line 121  extern "C" { Line 120  extern "C" {
 #define CPU_PTE_WRITABLE        (1 << 1)  #define CPU_PTE_WRITABLE        (1 << 1)
 #define CPU_PTE_PRESENT         (1 << 0)  #define CPU_PTE_PRESENT         (1 << 0)
   
 /* paging_check(): rw */  
 #define CPU_PAGING_PAGE_READ    (0 << 0)  /*
 #define CPU_PAGING_PAGE_WRITE   (1 << 0)   * linear address memory access function
 #define CPU_PAGING_PAGE_CODE    (1 << 1)   */
 #define CPU_PAGING_PAGE_DATA    (1 << 2)  void MEMCALL cpu_memory_access_la_region(UINT32 address, UINT length, const int ucrw, UINT8 *data);
   UINT32 MEMCALL laddr2paddr(const UINT32 laddr, const int ucrw);
   #define laddr_to_paddr(laddr, ucrw) \
 /* enter/leave paging mode */          (!CPU_STAT_PAGING) ? (laddr) : (laddr2paddr((laddr), (ucrw)))
 void FASTCALL change_pg(int onoff);  
   
 /* paging check */  /* ucrw */
 void MEMCALL paging_check(DWORD laddr, DWORD length, int rw);  #define CPU_PAGE_WRITE          (1 << 0)
   #define CPU_PAGE_CODE           (1 << 1)
 /*  #define CPU_PAGE_DATA           (1 << 2)
  * linear address function  #define CPU_PAGE_USER_MODE      (1 << 3)        /* == CPU_MODE_USER */
  */  #define CPU_PAGE_READ_CODE      (CPU_PAGE_CODE)
 DWORD MEMCALL cpu_linear_memory_read(DWORD address, DWORD length, int code);  #define CPU_PAGE_READ_DATA      (CPU_PAGE_DATA)
 void MEMCALL cpu_linear_memory_write(DWORD address, DWORD length, DWORD value);  #define CPU_PAGE_WRITE_DATA     (CPU_PAGE_WRITE|CPU_PAGE_DATA)
   
 #define cpu_lmemoryread(a) \  UINT8 MEMCALL cpu_memory_access_la_RMW_b(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg);
         (CPU_STAT_PAGING) ? \  UINT16 MEMCALL cpu_memory_access_la_RMW_w(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg);
                 (BYTE)cpu_linear_memory_read(a, 1, FALSE) : \  UINT32 MEMCALL cpu_memory_access_la_RMW_d(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg);
                 cpu_memoryread(a);  UINT8 MEMCALL cpu_linear_memory_read_b(UINT32 laddr, const int ucrw);
 #define cpu_lmemoryread_w(a) \  UINT16 MEMCALL cpu_linear_memory_read_w(UINT32 laddr, const int ucrw);
         (CPU_STAT_PAGING) ? \  UINT32 MEMCALL cpu_linear_memory_read_d(UINT32 laddr, const int ucrw);
                 (WORD)cpu_linear_memory_read(a, 2, FALSE) : \  UINT64 MEMCALL cpu_linear_memory_read_q(UINT32 laddr, const int ucrw);
                 cpu_memoryread_w(a);  REG80 MEMCALL cpu_linear_memory_read_f(UINT32 laddr, const int ucrw);
 #define cpu_lmemoryread_d(a) \  void MEMCALL cpu_linear_memory_write_b(UINT32 laddr, UINT8 value, const int user_mode);
         (CPU_STAT_PAGING) ? \  void MEMCALL cpu_linear_memory_write_w(UINT32 laddr, UINT16 value, const int user_mode);
                 cpu_linear_memory_read(a, 4, FALSE) : \  void MEMCALL cpu_linear_memory_write_d(UINT32 laddr, UINT32 value, const int user_mode);
                 cpu_memoryread_d(a);  void MEMCALL cpu_linear_memory_write_q(UINT32 laddr, UINT64 value, const int user_mode);
   void MEMCALL cpu_linear_memory_write_f(UINT32 laddr, const REG80 *value, const int user_mode);
 #define cpu_lmemorywrite(a,v) \  
         (CPU_STAT_PAGING) ? \  #define cpu_lmemoryread(a,pl) \
                 cpu_linear_memory_write(a, 1, v) : \          (!CPU_STAT_PAGING) ? \
                 cpu_memorywrite(a,v);           cpu_memoryread(a) : \
 #define cpu_lmemorywrite_w(a,v) \           cpu_linear_memory_read_b(a,CPU_PAGE_READ_DATA | (pl))
         (CPU_STAT_PAGING) ? \  #define cpu_lmemoryread_b(a,pl) cpu_lmemoryread(a,pl)
                 cpu_linear_memory_write(a, 2, v) : \  #define cpu_lmemoryread_w(a,pl) \
                 cpu_memorywrite_w(a,v);          (!CPU_STAT_PAGING) ? \
 #define cpu_lmemorywrite_d(a,v) \           cpu_memoryread_w(a) : \
         (CPU_STAT_PAGING) ? \           cpu_linear_memory_read_w(a,CPU_PAGE_READ_DATA | (pl))
                 cpu_linear_memory_write(a, 4, v) : \  #define cpu_lmemoryread_d(a,pl) \
                 cpu_memorywrite_d(a,v);          (!CPU_STAT_PAGING) ? \
            cpu_memoryread_d(a) : \
 #define cpu_lcmemoryread(a) \           cpu_linear_memory_read_d(a,CPU_PAGE_READ_DATA | (pl))
         (CPU_STAT_PAGING) ? \  #define cpu_lmemoryread_q(a,pl) \
                 (BYTE)cpu_linear_memory_read(a, 1, TRUE) : \          (!CPU_STAT_PAGING) ? \
                 cpu_memoryread(a);           cpu_memoryread_q(a) : \
 #define cpu_lcmemoryread_w(a) \           cpu_linear_memory_read_q(a,CPU_PAGE_READ_DATA | (pl))
         (CPU_STAT_PAGING) ? \  
                 (WORD)cpu_linear_memory_read(a, 2, TRUE) : \  #define cpu_lmemorywrite(a,v,pl) \
                 cpu_memoryread_w(a);          (!CPU_STAT_PAGING) ? \
 #define cpu_lcmemoryread_d(a) \           cpu_memorywrite(a,v) : cpu_linear_memory_write_b(a,v,pl)
         (CPU_STAT_PAGING) ? \  #define cpu_lmemorywrite_b(a,v,pl) cpu_lmemorywrite(a,v,pl)
                 cpu_linear_memory_read(a, 4, TRUE) : \  #define cpu_lmemorywrite_w(a,v,pl) \
                 cpu_memoryread_d(a);          (!CPU_STAT_PAGING) ? \
            cpu_memorywrite_w(a,v) : cpu_linear_memory_write_w(a,v,pl)
 #define set_CR3(cr3) \  #define cpu_lmemorywrite_d(a,v,pl) \
 do { \          (!CPU_STAT_PAGING) ? \
         CPU_CR3 = (cr3) & CPU_CR3_MASK; \           cpu_memorywrite_d(a,v) : cpu_linear_memory_write_d(a,v,pl)
         tlb_flush(FALSE); \  #define cpu_lmemorywrite_q(a,v,pl) \
 } while (/*CONSTCOND*/ 0)          (!CPU_STAT_PAGING) ? \
            cpu_memorywrite_q(a,v) : cpu_linear_memory_write_q(a,v,pl)
   
   /*
    * linear address memory access with superviser mode
    */
   #define cpu_kmemoryread(a)      cpu_lmemoryread(a,CPU_MODE_SUPERVISER)
   #define cpu_kmemoryread_w(a)    cpu_lmemoryread_w(a,CPU_MODE_SUPERVISER)
   #define cpu_kmemoryread_d(a)    cpu_lmemoryread_d(a,CPU_MODE_SUPERVISER)
   #define cpu_kmemorywrite(a,v)   cpu_lmemorywrite(a,v,CPU_MODE_SUPERVISER)
   #define cpu_kmemorywrite_w(a,v) cpu_lmemorywrite_w(a,v,CPU_MODE_SUPERVISER)
   #define cpu_kmemorywrite_d(a,v) cpu_lmemorywrite_d(a,v,CPU_MODE_SUPERVISER)
   
   
 /*  /*
  * TLB function   * TLB function
  */   */
 void tlb_init();  typedef struct {
 void tlb_flush(BOOL allflush);          UINT32  tag;    /* linear address */
 void tlb_flush_page(DWORD vaddr);  #define TLB_ENTRY_TAG_VALID             (1 << 0)
   /*      pde & pte & CPU_PTE_WRITABLE    (1 << 1)        */
   /*      pde & pte & CPU_PTE_USER_MODE   (1 << 2)        */
   #define TLB_ENTRY_TAG_DIRTY             CPU_PTE_DIRTY           /* (1 << 6) */
   #define TLB_ENTRY_TAG_GLOBAL            CPU_PTE_GLOBAL_PAGE     /* (1 << 8) */
   #define TLB_ENTRY_TAG_MAX_SHIFT         12
   
           UINT32  paddr;  /* physical address */
   
           UINT8   *memp;  /* shortcut for pre-fetch queue */
   } TLB_ENTRY_T;
   
   
   #if defined(IA32_SUPPORT_TLB)
   void tlb_init(void);
   void MEMCALL tlb_flush(BOOL allflush);
   void MEMCALL tlb_flush_page(UINT32 laddr);
   TLB_ENTRY_T* MEMCALL tlb_lookup(const UINT32 laddr, const int ucrw);
   #else
   #define tlb_init()
   #define tlb_flush(allflush)
   #define tlb_flush_page(la)
   #define tlb_lookup(la, ucrw)    NULL
   #endif
   
 #ifdef __cplusplus  #ifdef __cplusplus
 }  }
Removed from v.1.5  
changed lines
  Added in v.1.24

RetroPC.NET-CVS <cvs@retropc.net>