| version 1.4, 2004/01/23 14:33:26 | version 1.27, 2011/12/29 13:32:12 | 
| Line 1 | Line 1 | 
 | /*      $Id$    */ |  | 
 |  |  | 
 | /* | /* | 
 | * Copyright (c) 2003 NONAKA Kimihiro | * Copyright (c) 2003 NONAKA Kimihiro | 
 | * All rights reserved. | * All rights reserved. | 
| Line 12 | Line 10 | 
 | * 2. Redistributions in binary form must reproduce the above copyright | * 2. Redistributions in binary form must reproduce the above copyright | 
 | *    notice, this list of conditions and the following disclaimer in the | *    notice, this list of conditions and the following disclaimer in the | 
 | *    documentation and/or other materials provided with the distribution. | *    documentation and/or other materials provided with the distribution. | 
 | * 3. The name of the author may not be used to endorse or promote products |  | 
 | *    derived from this software without specific prior written permission. |  | 
 | * | * | 
 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR | 
 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES | 
| Line 35  extern "C" { | Line 31  extern "C" { | 
 | #endif | #endif | 
 |  |  | 
 | /* | /* | 
| * ¥Ú¡¼¥¸¡¦¥Ç¥£¥ì¥¯¥È¥ê¡¦¥¨¥ó¥È¥ê (4K ¥Ð¥¤¥È¥Ú¡¼¥¸»ÈÍÑ»þ) | * ¥Ú¡¼¥¸¡¦¥Ç¥£¥ì¥¯¥È¥ê¡¦¥¨¥ó¥È¥ê (4K ¥Ð¥¤¥È¥Ú¡¼¥¸»ÈÍÑ»þ) | 
 | * | * | 
 | *  31                                    12 11   9 8  7 6 5  4   3   2   1  0 | *  31                                    12 11   9 8  7 6 5  4   3   2   1  0 | 
 | * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+ | * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+ | 
| * |   ¡¦¥ì¡£¥·¡¦¥¯¡£¥ò¡¦¥Ë¡£¥·¡¦¥è¡¦ö¦¥Û¡¦¥ë¡£¥·¡¦¥±¡£¥ò¡¦¡Ö¡¦¥Î¡¦ø§¥±   |¥µ¥Í¥Ø¥à¥¤¥È|G|PS|0|A|PCD|PWT|U/S|R/W|P| | * |   åãÔ妾å⥯å㥵åã¬å¦¾åãÌå¦åá¥çåãÒ妾å⥱å㥵åâ¡Öåã²å¦®å⥱   |è¿¥½íô¥£éï¥Ã|G|PS|-|A|PCD|PWT|U/S|R/W|P| | 
 | * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+ | * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+ | 
 | *                                              |   |  | | |  |   |   |   |  | | *                                              |   |  | | |  |   |   |   |  | | 
| * 9-11: ¡¦¥¡¦¥±¡¦¥Ë¡¦à£¥ò¡¦¥é¡¦ú§¡¼¡¦ò§¡«¡¢¥ã¥µ¥Í¥Ø¥à¥¤¥È¥Ì¥¹ --------+   |  | | |  |   |   |   |  | | * 9-11: ¥·¥¹¥Æ¥à¡¦¥×¥í¥°¥é¥Þ¤¬»ÈÍѲÄǽ --------+   |  | | |  |   |   |   |  | | 
| *    8: ¡¦¡¼¡¦ú£¥·¡¦¥ß¡¦ö£¥ò¡¦¥ì¡£¥·¡¦¥¯(¥Õ¥ª¥µö¦¥ª¡¢ø¦ ------------+  | | |  |   |   |   |  | | *    8: ¥°¥í¡¼¥Ð¥ë¡¦¥Ú¡¼¥¸(̵»ë¤µ¤ì¤ë) ------------+  | | |  |   |   |   |  | | 
| *    7: ¥Ú¡¼¥¸¡¦¥µ¥¤¥º (0 = 4k ¥Ð¥¤¥È¥Ú¡¼¥¸) ---------+ | |  |   |   |   |  | | *    7: ¥Ú¡¼¥¸¡¦¥µ¥¤¥º (0 = 4k ¥Ð¥¤¥È¥Ú¡¼¥¸) ---------+ | |  |   |   |   |  | | 
| *    6: ͽÌó (0) ---------------------------------------+ |  |   |   |   |  | | *    6: ͽÌó (-) ---------------------------------------+ |  |   |   |   |  | | 
| *    5: ¥¢¥¯¥»¥¹ -----------------------------------------+  |   |   |   |  | | *    5: ¥¢¥¯¥»¥¹ -----------------------------------------+  |   |   |   |  | | 
| *    4: ¥¥ã¥Ã¥·¥å̵¸ú --------------------------------------+   |   |   |  | | *    4: ¥¥ã¥Ã¥·¥å̵¸ú --------------------------------------+   |   |   |  | | 
| *    3: ¥é¥¤¥È¥¹¥ë¡¼ --------------------------------------------+   |   |  | | *    3: ¥é¥¤¥È¥¹¥ë¡¼ --------------------------------------------+   |   |  | | 
| *    2: ¥æ¡¼¥¶¡¿¥¹¡¼¥Ñ¥Ð¥¤¥¶ (0 = ¥¹¡¼¥Ñ¥Ð¥¤¥¶) ---------------------+   |  | | *    2: ¥æ¡¼¥¶¡¿¥¹¡¼¥Ñ¥Ð¥¤¥¶ (0 = ¥¹¡¼¥Ñ¥Ð¥¤¥¶) ---------------------+   |  | | 
| *    1: ÆÉ¤ß¼è¤ê¡¿½ñ¤¹þ¤ß (0 = ÆÉ¤ß¼è¤ê¤Î¤ß) ---------------------------+  | | *    1: ÆÉ¤ß¼è¤ê¡¿½ñ¤¹þ¤ß (0 = ÆÉ¤ß¼è¤ê¤Î¤ß) ---------------------------+  | | 
| *    0: ¥Ú¡¼¥¸Â¸ºß ---------------------------------------------------------+ | *    0: ¥Ú¡¼¥¸Â¸ºß ---------------------------------------------------------+ | 
 | */ | */ | 
 | #define CPU_PDE_BASEADDR_MASK   0xfffff000 | #define CPU_PDE_BASEADDR_MASK   0xfffff000 | 
 |  | #define CPU_PDE_GLOBAL_PAGE     (1 << 8) | 
 | #define CPU_PDE_PAGE_SIZE       (1 << 7) | #define CPU_PDE_PAGE_SIZE       (1 << 7) | 
 |  | #define CPU_PDE_DIRTY           (1 << 6) | 
 | #define CPU_PDE_ACCESS          (1 << 5) | #define CPU_PDE_ACCESS          (1 << 5) | 
 | #define CPU_PDE_CACHE_DISABLE   (1 << 4) | #define CPU_PDE_CACHE_DISABLE   (1 << 4) | 
 | #define CPU_PDE_WRITE_THROUGH   (1 << 3) | #define CPU_PDE_WRITE_THROUGH   (1 << 3) | 
| Line 63  extern "C" { | Line 61  extern "C" { | 
 | #define CPU_PDE_PRESENT         (1 << 0) | #define CPU_PDE_PRESENT         (1 << 0) | 
 |  |  | 
 | /* | /* | 
| * ¥Ú¡¼¥¸¡¦¥Ç¥£¥ì¥¯¥È¥ê¡¦¥¨¥ó¥È¥ê (4M ¥Ð¥¤¥È¥Ú¡¼¥¸»ÈÍÑ»þ) | * ¥Ú¡¼¥¸¡¦¥Ç¥£¥ì¥¯¥È¥ê¡¦¥¨¥ó¥È¥ê (4M ¥Ð¥¤¥È¥Ú¡¼¥¸»ÈÍÑ»þ) | 
 | * | * | 
 | *  31                        22 21       12 11   9 8  7 6 5  4   3   2   1  0 | *  31                        22 21       12 11   9 8  7 6 5  4   3   2   1  0 | 
 | * +----------------------------+-----------+------+-+--+-+-+---+---+---+---+-+ | * +----------------------------+-----------+------+-+--+-+-+---+---+---+---+-+ | 
| * |¥Ú¡¼¥¸¥Æ¡¼¥Ö¥ë¤ÎʪÍý¥¢¥É¥ì¥¹|  Í½ÌóºÑ¤ß |»ÈÍѲÄ|G|PS|D|A|PCD|PWT|U/S|R/W|P| | * |åãÔ妾å⥯åã¬å¦¾åãÌå¦åá¥çí饥íð¬å¤¤åã²å¦®å⥱|  è¼°é¥¨¨è¥¯°å¢Á |è¿¥½íô¥£éï¥Ã|G|PS|D|A|PCD|PWT|U/S|R/W|P| | 
 | * +----------------------------+-----------+------+-+--+-+-+---+---+---+---+-+ | * +----------------------------+-----------+------+-+--+-+-+---+---+---+---+-+ | 
 | *                                              |   |  | | |  |   |   |   |  | | *                                              |   |  | | |  |   |   |   |  | | 
| * 9-11: ¡¦¥¡¦¥±¡¦¥Ë¡¦à£¥ò¡¦¥é¡¦ú§¡¼¡¦ò§¡«¡¢¥ã¥µ¥Í¥Ø¥à¥¤¥È¥Ì¥¹ --------+   |  | | |  |   |   |   |  | | * 9-11: ¥·¥¹¥Æ¥à¡¦¥×¥í¥°¥é¥Þ¤¬»ÈÍѲÄǽ --------+   |  | | |  |   |   |   |  | | 
| *    8: ¡¦¡¼¡¦ú£¥·¡¦¥ß¡¦ö£¥ò¡¦¥ì¡£¥·¡¦¥¯ ------------------------+  | | |  |   |   |   |  | | *    8: ¥°¥í¡¼¥Ð¥ë¡¦¥Ú¡¼¥¸ ------------------------+  | | |  |   |   |   |  | | 
| *    7: ¡¦¥ì¡£¥·¡¦¥¯¡£¥ò¡¦¥ª¡¦¡¢¡¦¥³ (1 = 4M ¡¦¥ß¡¦¡¢¡¦¥Í¡¦¥ì¡£¥·¡¦¥¯) ---------+ | |  |   |   |   |  | | *    7: ¥Ú¡¼¥¸¡¦¥µ¥¤¥º (1 = 4M ¥Ð¥¤¥È¥Ú¡¼¥¸) ---------+ | |  |   |   |   |  | | 
| *    6: ¡¦¥¿¡£¥·¡¦¥Ë¡¦¡× ---------------------------------------+ |  |   |   |   |  | | *    6: ¥À¡¼¥Æ¥£ ---------------------------------------+ |  |   |   |   |  | | 
| *    5: ¡¦¡Ö¡¦¥Ã¡¦¥µ¡¦¥± -----------------------------------------+  |   |   |   |  | | *    5: ¥¢¥¯¥»¥¹ -----------------------------------------+  |   |   |   |  | | 
| *    4: ¡¦¥å¡¦æ§¥Æ¡¦¥¡¦êÎ¥ª¥¯--------------------------------------+   |   |   |  | | *    4: ¥¥ã¥Ã¥·¥å̵¸ú --------------------------------------+   |   |   |  | | 
| *    3: ¡¦ò§¡¢¡¦¥Í¡¦¥±¡¦ö£¥· --------------------------------------------+   |   |  | | *    3: ¥é¥¤¥È¥¹¥ë¡¼ --------------------------------------------+   |   |  | | 
| *    2: ¡¦ì£¥·¡¦¥«¡£¥½¡¦¥±¡£¥·¡¦¥à¡¦¥ß¡¦¡¢¡¦¥« (0 = ¡¦¥±¡£¥·¡¦¥à¡¦¥ß¡¦¡¢¡¦¥«) ---------------------+   |  | | *    2: ¥æ¡¼¥¶¡¿¥¹¡¼¥Ñ¥Ð¥¤¥¶ (0 = ¥¹¡¼¥Ñ¥Ð¥¤¥¶) ---------------------+   |  | | 
| *    1: ¥Ë¥Î¡¢¡¬¥·ð¦ô£¥½¥¹ñ¤¹þ¤(0 = ÆÉ¤ß¼è¤ê¤Î¤ß) ---------------------------+  | | *    1: ÆÉ¤ß¼è¤ê¡¿½ñ¤¹þ¤ß (0 = ÆÉ¤ß¼è¤ê¤Î¤ß) ---------------------------+  | | 
| *    0: ¥Ú¡¼¥¸Â¸ºß ---------------------------------------------------------+ | *    0: ¥Ú¡¼¥¸Â¸ºß ---------------------------------------------------------+ | 
 | */ | */ | 
 | #define CPU_PDE_4M_BASEADDR_MASK        0xffc00000 | #define CPU_PDE_4M_BASEADDR_MASK        0xffc00000 | 
 | #define CPU_PDE_4M_GLOBAL_PAGE          (1 << 8) | #define CPU_PDE_4M_GLOBAL_PAGE          (1 << 8) | 
| Line 93  extern "C" { | Line 91  extern "C" { | 
 | #define CPU_PDE_4M_PRESENT              (1 << 0) | #define CPU_PDE_4M_PRESENT              (1 << 0) | 
 |  |  | 
 | /* | /* | 
| * ¥Ú¡¼¥¸¡¦¥Æ¡¼¥Ö¥ë¡¦¥¨¥ó¥È¥ê (4k ¥Ð¥¤¥È¡¦¥Ú¡¼¥¸) | * åãÔ妾å⥯å㥵åã¬å¦¾åãÌå¦å㥵å⥣å㥦åã°å¦¬ (4k åãÀ夦åã°å¦½åãÔ妾å⥯) | 
 | * | * | 
 | *  31                                    12 11   9 8 7 6 5  4   3   2   1  0 | *  31                                    12 11   9 8 7 6 5  4   3   2   1  0 | 
 | * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+ | * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+ | 
| * |        ¡¦¥ì¡£¥·¡¦¥¯¡¢¥Û¡¦¥ë¡£¥·¡¦¥±¡£¥ò¡¦¡Ö¡¦¥Î¡¦ø§¥±        |¥µ¥Í¥Ø¥à¥¤¥È|G|0|D|A|PCD|PWT|U/S|R/W|P| | * |        åãÔ妾å⥯åá¥çåãÒ妾å⥱å㥵åâ¡Öåã²å¦®å⥱        |è¿¥½íô¥£éï¥Ã|G|-|D|A|PCD|PWT|U/S|R/W|P| | 
 | * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+ | * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+ | 
 | *                                              |   | | | |  |   |   |   |  | | *                                              |   | | | |  |   |   |   |  | | 
| *  9-11: ¡¦¥¡¦¥±¡¦¥Ë¡¦à£¥ò¡¦¥é¡¦ú§¡¼¡¦ò§¡«¡¢¥ã¥µ¥Í¥Ø¥à¥¤¥È¥Ì¥¹ -------+   | | | |  |   |   |   |  | | *  9-11: ¥·¥¹¥Æ¥à¡¦¥×¥í¥°¥é¥Þ¤¬»ÈÍѲÄǽ -------+   | | | |  |   |   |   |  | | 
| *     8: ¡¦¡¼¡¦ú£¥·¡¦¥ß¡¦ö£¥ò¡¦¥ì¡£¥·¡¦¥¯ -----------------------+ | | |  |   |   |   |  | | *     8: ¥°¥í¡¼¥Ð¥ë¡¦¥Ú¡¼¥¸ -----------------------+ | | |  |   |   |   |  | | 
| *     7: ¥Ø¥¹¥Õ(0) -----------------------------------+ | |  |   |   |   |  | | *     7: ͽÌó (-) -----------------------------------+ | |  |   |   |   |  | | 
| *     6: ¥À¡¼¥Æ¥£ -------------------------------------+ |  |   |   |   |  | | *     6: ¥À¡¼¥Æ¥£ -------------------------------------+ |  |   |   |   |  | | 
| *     5: ¥¢¥¯¥»¥¹ ---------------------------------------+  |   |   |   |  | | *     5: ¥¢¥¯¥»¥¹ ---------------------------------------+  |   |   |   |  | | 
| *     4: ¥¥ã¥Ã¥·¥å̵¸ú ------------------------------------+   |   |   |  | | *     4: ¥¥ã¥Ã¥·¥å̵¸ú ------------------------------------+   |   |   |  | | 
| *     3: ¥é¥¤¥È¥¹¥ë¡¼ ------------------------------------------+   |   |  | | *     3: ¥é¥¤¥È¥¹¥ë¡¼ ------------------------------------------+   |   |  | | 
| *     2: ¥æ¡¼¥¶¡¿¥¹¡¼¥Ñ¥Ð¥¤¥¶ (0 = ¥¹¡¼¥Ñ¥Ð¥¤¥¶) -------------------+   |  | | *     2: ¥æ¡¼¥¶¡¿¥¹¡¼¥Ñ¥Ð¥¤¥¶ (0 = ¥¹¡¼¥Ñ¥Ð¥¤¥¶) -------------------+   |  | | 
| *     1: ÆÉ¤ß¼è¤ê¡¿½ñ¤¹þ¤ß (0 = ÆÉ¤ß¼è¤ê¤Î¤ß) -------------------------+  | | *     1: ÆÉ¤ß¼è¤ê¡¿½ñ¤¹þ¤ß (0 = ÆÉ¤ß¼è¤ê¤Î¤ß) -------------------------+  | | 
| *     0: ¥Ú¡¼¥¸Â¸ºß -------------------------------------------------------+ | *     0: ¥Ú¡¼¥¸Â¸ºß -------------------------------------------------------+ | 
 | */ | */ | 
 | #define CPU_PTE_BASEADDR_MASK   0xfffff000 | #define CPU_PTE_BASEADDR_MASK   0xfffff000 | 
 | #define CPU_PTE_GLOBAL_PAGE     (1 << 8) | #define CPU_PTE_GLOBAL_PAGE     (1 << 8) | 
 |  | #define CPU_PTE_PAGE_SIZE       (1 << 7) | 
 | #define CPU_PTE_DIRTY           (1 << 6) | #define CPU_PTE_DIRTY           (1 << 6) | 
 | #define CPU_PTE_ACCESS          (1 << 5) | #define CPU_PTE_ACCESS          (1 << 5) | 
 | #define CPU_PTE_CACHE_DISABLE   (1 << 4) | #define CPU_PTE_CACHE_DISABLE   (1 << 4) | 
| Line 122  extern "C" { | Line 121  extern "C" { | 
 | #define CPU_PTE_PRESENT         (1 << 0) | #define CPU_PTE_PRESENT         (1 << 0) | 
 |  |  | 
 |  |  | 
| /* enter/leave paging mode */ | /* | 
| void FASTCALL change_pg(int onoff); | * linear address memory access function | 
|  | */ | 
| /* paging check */ | void MEMCALL cpu_memory_access_la_region(UINT32 address, UINT length, const int ucrw, UINT8 *data); | 
| void MEMCALL paging_check(DWORD laddr, DWORD length, int rw); | UINT32 MEMCALL laddr2paddr(const UINT32 laddr, const int ucrw); | 
|  | #define laddr_to_paddr(laddr, ucrw) \ | 
| /* paging_check(): rw */ | (!CPU_STAT_PAGING) ? (laddr) : (laddr2paddr((laddr), (ucrw))) | 
| #define CPU_PAGING_PAGE_READ    (0 << 0) |  | 
| #define CPU_PAGING_PAGE_WRITE   (1 << 0) |  | 
|  | /* ucrw */ | 
| /* | #define CPU_PAGE_WRITE          (1 << 0) | 
| * linear address function | #define CPU_PAGE_CODE           (1 << 1) | 
| */ | #define CPU_PAGE_DATA           (1 << 2) | 
| DWORD MEMCALL cpu_linear_memory_read(DWORD address, DWORD length, int code); | #define CPU_PAGE_USER_MODE      (1 << 3)        /* == CPU_MODE_USER */ | 
| void MEMCALL cpu_linear_memory_write(DWORD address, DWORD length, DWORD value); | #define CPU_PAGE_READ_CODE      (CPU_PAGE_CODE) | 
|  | #define CPU_PAGE_READ_DATA      (CPU_PAGE_DATA) | 
| /* cpu_linear_memory_read(): code */ | #define CPU_PAGE_WRITE_DATA     (CPU_PAGE_WRITE|CPU_PAGE_DATA) | 
| #define CPU_PAGING_PAGE_CODE    (1 << 1) |  | 
| #define CPU_PAGING_PAGE_DATA    (1 << 2) | UINT8 MEMCALL cpu_memory_access_la_RMW_b(UINT32 laddr, UINT32 (CPUCALL *func)(UINT32, void *), void *arg); | 
|  | UINT16 MEMCALL cpu_memory_access_la_RMW_w(UINT32 laddr, UINT32 (CPUCALL *func)(UINT32, void *), void *arg); | 
| #define cpu_lmemoryread(a) \ | UINT32 MEMCALL cpu_memory_access_la_RMW_d(UINT32 laddr, UINT32 (CPUCALL *func)(UINT32, void *), void *arg); | 
| (CPU_STAT_PAGING) ? \ | UINT8 MEMCALL cpu_linear_memory_read_b(UINT32 laddr, const int ucrw); | 
| (BYTE)cpu_linear_memory_read(a, 1, FALSE) : \ | UINT16 MEMCALL cpu_linear_memory_read_w(UINT32 laddr, const int ucrw); | 
| cpu_memoryread(a); | UINT32 MEMCALL cpu_linear_memory_read_d(UINT32 laddr, const int ucrw); | 
| #define cpu_lmemoryread_w(a) \ | UINT64 MEMCALL cpu_linear_memory_read_q(UINT32 laddr, const int ucrw); | 
| (CPU_STAT_PAGING) ? \ | REG80 MEMCALL cpu_linear_memory_read_f(UINT32 laddr, const int ucrw); | 
| (WORD)cpu_linear_memory_read(a, 2, FALSE) : \ | void MEMCALL cpu_linear_memory_write_b(UINT32 laddr, UINT8 value, const int user_mode); | 
| cpu_memoryread_w(a); | void MEMCALL cpu_linear_memory_write_w(UINT32 laddr, UINT16 value, const int user_mode); | 
| #define cpu_lmemoryread_d(a) \ | void MEMCALL cpu_linear_memory_write_d(UINT32 laddr, UINT32 value, const int user_mode); | 
| (CPU_STAT_PAGING) ? \ | void MEMCALL cpu_linear_memory_write_q(UINT32 laddr, UINT64 value, const int user_mode); | 
| cpu_linear_memory_read(a, 4, FALSE) : \ | void MEMCALL cpu_linear_memory_write_f(UINT32 laddr, const REG80 *value, const int user_mode); | 
| cpu_memoryread_d(a); |  | 
|  | #define cpu_lmemoryread(a,pl) \ | 
| #define cpu_lmemorywrite(a,v) \ | (!CPU_STAT_PAGING) ? \ | 
| (CPU_STAT_PAGING) ? \ | cpu_memoryread(a) : \ | 
| cpu_linear_memory_write(a, 1, v) : \ | cpu_linear_memory_read_b(a,CPU_PAGE_READ_DATA | (pl)) | 
| cpu_memorywrite(a,v); | #define cpu_lmemoryread_b(a,pl) cpu_lmemoryread(a,pl) | 
| #define cpu_lmemorywrite_w(a,v) \ | #define cpu_lmemoryread_w(a,pl) \ | 
| (CPU_STAT_PAGING) ? \ | (!CPU_STAT_PAGING) ? \ | 
| cpu_linear_memory_write(a, 2, v) : \ | cpu_memoryread_w(a) : \ | 
| cpu_memorywrite_w(a,v); | cpu_linear_memory_read_w(a,CPU_PAGE_READ_DATA | (pl)) | 
| #define cpu_lmemorywrite_d(a,v) \ | #define cpu_lmemoryread_d(a,pl) \ | 
| (CPU_STAT_PAGING) ? \ | (!CPU_STAT_PAGING) ? \ | 
| cpu_linear_memory_write(a, 4, v) : \ | cpu_memoryread_d(a) : \ | 
| cpu_memorywrite_d(a,v); | cpu_linear_memory_read_d(a,CPU_PAGE_READ_DATA | (pl)) | 
|  | #define cpu_lmemoryread_q(a,pl) \ | 
| #define cpu_lcmemoryread(a) \ | (!CPU_STAT_PAGING) ? \ | 
| (CPU_STAT_PAGING) ? \ | cpu_memoryread_q(a) : \ | 
| (BYTE)cpu_linear_memory_read(a, 1, TRUE) : \ | cpu_linear_memory_read_q(a,CPU_PAGE_READ_DATA | (pl)) | 
| cpu_memoryread(a); |  | 
| #define cpu_lcmemoryread_w(a) \ | #define cpu_lmemorywrite(a,v,pl) \ | 
| (CPU_STAT_PAGING) ? \ | (!CPU_STAT_PAGING) ? \ | 
| (WORD)cpu_linear_memory_read(a, 2, TRUE) : \ | cpu_memorywrite(a,v) : cpu_linear_memory_write_b(a,v,pl) | 
| cpu_memoryread_w(a); | #define cpu_lmemorywrite_b(a,v,pl) cpu_lmemorywrite(a,v,pl) | 
| #define cpu_lcmemoryread_d(a) \ | #define cpu_lmemorywrite_w(a,v,pl) \ | 
| (CPU_STAT_PAGING) ? \ | (!CPU_STAT_PAGING) ? \ | 
| cpu_linear_memory_read(a, 4, TRUE) : \ | cpu_memorywrite_w(a,v) : cpu_linear_memory_write_w(a,v,pl) | 
| cpu_memoryread_d(a); | #define cpu_lmemorywrite_d(a,v,pl) \ | 
|  | (!CPU_STAT_PAGING) ? \ | 
| #define set_CR3(cr3) \ | cpu_memorywrite_d(a,v) : cpu_linear_memory_write_d(a,v,pl) | 
| do { \ | #define cpu_lmemorywrite_q(a,v,pl) \ | 
| CPU_CR3 = (cr3) & CPU_CR3_MASK; \ | (!CPU_STAT_PAGING) ? \ | 
| tlb_flush(FALSE); \ | cpu_memorywrite_q(a,v) : cpu_linear_memory_write_q(a,v,pl) | 
| } while (/*CONSTCOND*/ 0) |  | 
|  | /* | 
|  | * linear address memory access with superviser mode | 
|  | */ | 
|  | #define cpu_kmemoryread(a)      cpu_lmemoryread(a,CPU_MODE_SUPERVISER) | 
|  | #define cpu_kmemoryread_w(a)    cpu_lmemoryread_w(a,CPU_MODE_SUPERVISER) | 
|  | #define cpu_kmemoryread_d(a)    cpu_lmemoryread_d(a,CPU_MODE_SUPERVISER) | 
|  | #define cpu_kmemorywrite(a,v)   cpu_lmemorywrite(a,v,CPU_MODE_SUPERVISER) | 
|  | #define cpu_kmemorywrite_w(a,v) cpu_lmemorywrite_w(a,v,CPU_MODE_SUPERVISER) | 
|  | #define cpu_kmemorywrite_d(a,v) cpu_lmemorywrite_d(a,v,CPU_MODE_SUPERVISER) | 
 |  |  | 
 |  |  | 
 | /* | /* | 
 | * TLB function | * TLB function | 
 | */ | */ | 
| void tlb_init(); | typedef struct { | 
| void tlb_flush(BOOL allflush); | UINT32  tag;    /* linear address */ | 
| void tlb_flush_page(DWORD vaddr); | #define TLB_ENTRY_TAG_VALID             (1 << 0) | 
|  | /*      pde & pte & CPU_PTE_WRITABLE    (1 << 1)        */ | 
|  | /*      pde & pte & CPU_PTE_USER_MODE   (1 << 2)        */ | 
|  | #define TLB_ENTRY_TAG_DIRTY             CPU_PTE_DIRTY           /* (1 << 6) */ | 
|  | #define TLB_ENTRY_TAG_GLOBAL            CPU_PTE_GLOBAL_PAGE     /* (1 << 8) */ | 
|  | #define TLB_ENTRY_TAG_MAX_SHIFT         12 | 
|  |  | 
|  | UINT32  paddr;  /* physical address */ | 
|  |  | 
|  | UINT8   *memp;  /* shortcut for pre-fetch queue */ | 
|  | } TLB_ENTRY_T; | 
|  |  | 
|  | void tlb_init(void); | 
|  | void MEMCALL tlb_flush(BOOL allflush); | 
|  | void MEMCALL tlb_flush_page(UINT32 laddr); | 
|  | TLB_ENTRY_T* MEMCALL tlb_lookup(const UINT32 laddr, const int ucrw); | 
 |  |  | 
 | #ifdef __cplusplus | #ifdef __cplusplus | 
 | } | } |