--- np2/i386c/ia32/paging.h 2004/02/04 13:24:35 1.7 +++ np2/i386c/ia32/paging.h 2011/01/15 17:17:23 1.23 @@ -1,5 +1,3 @@ -/* $Id: paging.h,v 1.7 2004/02/04 13:24:35 monaka Exp $ */ - /* * Copyright (c) 2003 NONAKA Kimihiro * All rights reserved. @@ -12,8 +10,6 @@ * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES @@ -39,13 +35,13 @@ extern "C" { * * 31 12 11 9 8 7 6 5 4 3 2 1 0 * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+ - * | ページ・テーブルのベース・アドレス |使用可|G|PS|0|A|PCD|PWT|U/S|R/W|P| + * | ページ・テーブルのベース・アドレス |使用可|G|PS|-|A|PCD|PWT|U/S|R/W|P| * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+ * | | | | | | | | | | * 9-11: システム・プログラマが使用可能 --------+ | | | | | | | | | * 8: グローバル・ページ(無視される) ------------+ | | | | | | | | * 7: ページ・サイズ (0 = 4k バイトページ) ---------+ | | | | | | | - * 6: 予約 (0) ---------------------------------------+ | | | | | | + * 6: 予約 (-) ---------------------------------------+ | | | | | | * 5: アクセス -----------------------------------------+ | | | | | * 4: キャッシュ無効 --------------------------------------+ | | | | * 3: ライトスルー --------------------------------------------+ | | | @@ -54,7 +50,9 @@ extern "C" { * 0: ページ存在 ---------------------------------------------------------+ */ #define CPU_PDE_BASEADDR_MASK 0xfffff000 +#define CPU_PDE_GLOBAL_PAGE (1 << 8) #define CPU_PDE_PAGE_SIZE (1 << 7) +#define CPU_PDE_DIRTY (1 << 6) #define CPU_PDE_ACCESS (1 << 5) #define CPU_PDE_CACHE_DISABLE (1 << 4) #define CPU_PDE_WRITE_THROUGH (1 << 3) @@ -97,12 +95,12 @@ extern "C" { * * 31 12 11 9 8 7 6 5 4 3 2 1 0 * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+ - * | ページのベース・アドレス |使用可|G|0|D|A|PCD|PWT|U/S|R/W|P| + * | ページのベース・アドレス |使用可|G|-|D|A|PCD|PWT|U/S|R/W|P| * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+ * | | | | | | | | | | * 9-11: システム・プログラマが使用可能 -------+ | | | | | | | | | * 8: グローバル・ページ -----------------------+ | | | | | | | | - * 7: 予約 (0) -----------------------------------+ | | | | | | | + * 7: 予約 (-) -----------------------------------+ | | | | | | | * 6: ダーティ -------------------------------------+ | | | | | | * 5: アクセス ---------------------------------------+ | | | | | * 4: キャッシュ無効 ------------------------------------+ | | | | @@ -113,6 +111,7 @@ extern "C" { */ #define CPU_PTE_BASEADDR_MASK 0xfffff000 #define CPU_PTE_GLOBAL_PAGE (1 << 8) +#define CPU_PTE_PAGE_SIZE (1 << 7) #define CPU_PTE_DIRTY (1 << 6) #define CPU_PTE_ACCESS (1 << 5) #define CPU_PTE_CACHE_DISABLE (1 << 4) @@ -121,67 +120,73 @@ extern "C" { #define CPU_PTE_WRITABLE (1 << 1) #define CPU_PTE_PRESENT (1 << 0) -/* paging_check(): rw */ -#define CPU_PAGE_READ (0 << 0) + +/* + * linear address memory access function + */ +void MEMCALL cpu_memory_access_la_region(UINT32 address, UINT length, const int ucrw, UINT8 *data); +UINT32 MEMCALL laddr2paddr(const UINT32 laddr, const int ucrw); +#define laddr_to_paddr(laddr, ucrw) \ + (!CPU_STAT_PAGING) ? (laddr) : (laddr2paddr((laddr), (ucrw))) + + +/* ucrw */ #define CPU_PAGE_WRITE (1 << 0) #define CPU_PAGE_CODE (1 << 1) #define CPU_PAGE_DATA (1 << 2) -#define CPU_PAGE_READ_CODE (CPU_PAGE_READ|CPU_PAGE_CODE) -#define CPU_PAGE_READ_DATA (CPU_PAGE_READ|CPU_PAGE_DATA) +#define CPU_PAGE_USER_MODE (1 << 3) /* == CPU_MODE_USER */ +#define CPU_PAGE_READ_CODE (CPU_PAGE_CODE) +#define CPU_PAGE_READ_DATA (CPU_PAGE_DATA) #define CPU_PAGE_WRITE_DATA (CPU_PAGE_WRITE|CPU_PAGE_DATA) - -/* - * linear address function - */ -DWORD MEMCALL cpu_linear_memory_read(DWORD address, DWORD length, int code, int user_mode); -void MEMCALL cpu_linear_memory_write(DWORD address, DWORD value, DWORD length, int user_mode); -void MEMCALL paging_check(DWORD laddr, DWORD length, int crw, int user_mode); +UINT8 MEMCALL cpu_memory_access_la_RMW_b(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg); +UINT16 MEMCALL cpu_memory_access_la_RMW_w(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg); +UINT32 MEMCALL cpu_memory_access_la_RMW_d(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg); +UINT8 MEMCALL cpu_linear_memory_read_b(UINT32 laddr, const int ucrw); +UINT16 MEMCALL cpu_linear_memory_read_w(UINT32 laddr, const int ucrw); +UINT32 MEMCALL cpu_linear_memory_read_d(UINT32 laddr, const int ucrw); +UINT64 MEMCALL cpu_linear_memory_read_q(UINT32 laddr, const int ucrw); +REG80 MEMCALL cpu_linear_memory_read_f(UINT32 laddr, const int ucrw); +void MEMCALL cpu_linear_memory_write_b(UINT32 laddr, UINT8 value, const int user_mode); +void MEMCALL cpu_linear_memory_write_w(UINT32 laddr, UINT16 value, const int user_mode); +void MEMCALL cpu_linear_memory_write_d(UINT32 laddr, UINT32 value, const int user_mode); +void MEMCALL cpu_linear_memory_write_q(UINT32 laddr, UINT64 value, const int user_mode); +void MEMCALL cpu_linear_memory_write_f(UINT32 laddr, const REG80 *value, const int user_mode); #define cpu_lmemoryread(a,pl) \ (!CPU_STAT_PAGING) ? \ cpu_memoryread(a) : \ - (BYTE)cpu_linear_memory_read(a,1,CPU_PAGE_READ_DATA,pl) + cpu_linear_memory_read_b(a,CPU_PAGE_READ_DATA | (pl)) +#define cpu_lmemoryread_b(a,pl) cpu_lmemoryread(a,pl) #define cpu_lmemoryread_w(a,pl) \ (!CPU_STAT_PAGING) ? \ cpu_memoryread_w(a) : \ - (WORD)cpu_linear_memory_read(a,2,CPU_PAGE_READ_DATA,pl) + cpu_linear_memory_read_w(a,CPU_PAGE_READ_DATA | (pl)) #define cpu_lmemoryread_d(a,pl) \ (!CPU_STAT_PAGING) ? \ cpu_memoryread_d(a) : \ - cpu_linear_memory_read(a,4,CPU_PAGE_READ_DATA,pl) + cpu_linear_memory_read_d(a,CPU_PAGE_READ_DATA | (pl)) +#define cpu_lmemoryread_q(a,pl) \ + (!CPU_STAT_PAGING) ? \ + cpu_memoryread_q(a) : \ + cpu_linear_memory_read_q(a,CPU_PAGE_READ_DATA | (pl)) #define cpu_lmemorywrite(a,v,pl) \ (!CPU_STAT_PAGING) ? \ - cpu_memorywrite(a,v) : \ - cpu_linear_memory_write(a,v,1,pl) + cpu_memorywrite(a,v) : cpu_linear_memory_write_b(a,v,pl) +#define cpu_lmemorywrite_b(a,v,pl) cpu_lmemorywrite(a,v,pl) #define cpu_lmemorywrite_w(a,v,pl) \ (!CPU_STAT_PAGING) ? \ - cpu_memorywrite_w(a,v) : \ - cpu_linear_memory_write(a,v,2,pl) + cpu_memorywrite_w(a,v) : cpu_linear_memory_write_w(a,v,pl) #define cpu_lmemorywrite_d(a,v,pl) \ (!CPU_STAT_PAGING) ? \ - cpu_memorywrite_d(a,v) : \ - cpu_linear_memory_write(a,v,4,pl) - -/* - * access code segment linear memory - */ -#define cpu_lcmemoryread(a) \ - (!CPU_STAT_PAGING) ? \ - cpu_memoryread(a) : \ - (BYTE)cpu_linear_memory_read(a,1,CPU_PAGE_READ_CODE,CPU_IS_USER_MODE()) -#define cpu_lcmemoryread_w(a) \ - (!CPU_STAT_PAGING) ? \ - cpu_memoryread_w(a) : \ - (WORD)cpu_linear_memory_read(a,2,CPU_PAGE_READ_CODE,CPU_IS_USER_MODE()) -#define cpu_lcmemoryread_d(a) \ + cpu_memorywrite_d(a,v) : cpu_linear_memory_write_d(a,v,pl) +#define cpu_lmemorywrite_q(a,v,pl) \ (!CPU_STAT_PAGING) ? \ - cpu_memoryread_d(a) : \ - cpu_linear_memory_read(a,4,CPU_PAGE_READ_CODE,CPU_IS_USER_MODE()) + cpu_memorywrite_q(a,v) : cpu_linear_memory_write_q(a,v,pl) /* - * access linear memory with superviser mode + * linear address memory access with superviser mode */ #define cpu_kmemoryread(a) cpu_lmemoryread(a,CPU_MODE_SUPERVISER) #define cpu_kmemoryread_w(a) cpu_lmemoryread_w(a,CPU_MODE_SUPERVISER) @@ -192,27 +197,33 @@ void MEMCALL paging_check(DWORD laddr, D /* - * CR3 (Page Directory Entry base physical address) + * TLB function */ -#define set_CR3(cr3) \ -do { \ - CPU_CR3 = (cr3) & CPU_CR3_MASK; \ - CPU_STAT_PDE_BASE = CPU_CR3 & CPU_CR3_PD_MASK; \ - tlb_flush(FALSE); \ -} while (/*CONSTCOND*/ 0) +typedef struct { + UINT32 tag; /* linear address */ +#define TLB_ENTRY_TAG_VALID (1 << 0) +/* pde & pte & CPU_PTE_WRITABLE (1 << 1) */ +/* pde & pte & CPU_PTE_USER_MODE (1 << 2) */ +#define TLB_ENTRY_TAG_DIRTY CPU_PTE_DIRTY /* (1 << 6) */ +#define TLB_ENTRY_TAG_GLOBAL CPU_PTE_GLOBAL_PAGE /* (1 << 8) */ +#define TLB_ENTRY_TAG_MAX_SHIFT 12 + + UINT32 paddr; /* physical address */ + + UINT8 *memp; /* shortcut for pre-fetch queue */ +} TLB_ENTRY_T; -/* - * TLB function - */ #if defined(IA32_SUPPORT_TLB) -void tlb_init(); -void tlb_flush(BOOL allflush); -void tlb_flush_page(DWORD vaddr); +void tlb_init(void); +void MEMCALL tlb_flush(BOOL allflush); +void MEMCALL tlb_flush_page(UINT32 laddr); +TLB_ENTRY_T* MEMCALL tlb_lookup(const UINT32 laddr, const int ucrw); #else #define tlb_init() -#define tlb_flush(allflush) (void)allflush -#define tlb_flush_page(vaddr) (void)vaddr +#define tlb_flush(allflush) (void)(allflush) +#define tlb_flush_page(la) (void)(la) +#define tlb_lookup(la, ucrw) NULL #endif #ifdef __cplusplus