--- np2/i386c/ia32/paging.h 2004/06/15 13:50:13 1.18 +++ np2/i386c/ia32/paging.h 2011/12/29 13:32:12 1.27 @@ -1,5 +1,3 @@ -/* $Id: paging.h,v 1.18 2004/06/15 13:50:13 monaka Exp $ */ - /* * Copyright (c) 2003 NONAKA Kimihiro * All rights reserved. @@ -12,8 +10,6 @@ * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES @@ -35,23 +31,23 @@ extern "C" { #endif /* - * ¥Ú¡¼¥¸¡¦¥Ç¥£¥ì¥¯¥È¥ê¡¦¥¨¥ó¥È¥ê (4K ¥Ð¥¤¥È¥Ú¡¼¥¸»ÈÍÑ»þ) + * ¥Ú¡¼¥¸¡¦¥Ç¥£¥ì¥¯¥È¥ê¡¦¥¨¥ó¥È¥ê (4K ¥Ð¥¤¥È¥Ú¡¼¥¸»ÈÍÑ»þ) * * 31 12 11 9 8 7 6 5 4 3 2 1 0 * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+ - * | ¡¦¥ì¡£¥·¡¦¥¯¡£¥ò¡¦¥Ë¡£¥·¡¦¥è¡¦ö¦¥Û¡¦¥ë¡£¥·¡¦¥±¡£¥ò¡¦¡Ö¡¦¥Î¡¦ø§¥± |¥µ¥Í¥Ø¥à¥¤¥È|G|PS|-|A|PCD|PWT|U/S|R/W|P| + * | åãÔ妾å⥯å㥵åã¬å¦¾åãÌ妭åá¥çåãÒ妾å⥱å㥵åâ¡Öåã²å¦®å⥱ |è¿¥½íô¥£éï¥Ã|G|PS|-|A|PCD|PWT|U/S|R/W|P| * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+ * | | | | | | | | | | - * 9-11: ¡¦¥­¡¦¥±¡¦¥Ë¡¦à£¥ò¡¦¥é¡¦ú§¡¼¡¦ò§¡«¡¢¥ã¥µ¥Í¥Ø¥à¥¤¥È¥Ì¥¹ --------+ | | | | | | | | | - * 8: ¡¦¡¼¡¦ú£¥·¡¦¥ß¡¦ö£¥ò¡¦¥ì¡£¥·¡¦¥¯(¥Õ¥ª¥µö¦¥ª¡¢ø¦ ------------+ | | | | | | | | - * 7: ¥Ú¡¼¥¸¡¦¥µ¥¤¥º (0 = 4k ¥Ð¥¤¥È¥Ú¡¼¥¸) ---------+ | | | | | | | - * 6: ͽÌó (-) ---------------------------------------+ | | | | | | - * 5: ¥¢¥¯¥»¥¹ -----------------------------------------+ | | | | | - * 4: ¥­¥ã¥Ã¥·¥å̵¸ú --------------------------------------+ | | | | - * 3: ¥é¥¤¥È¥¹¥ë¡¼ --------------------------------------------+ | | | - * 2: ¥æ¡¼¥¶¡¿¥¹¡¼¥Ñ¥Ð¥¤¥¶ (0 = ¥¹¡¼¥Ñ¥Ð¥¤¥¶) ---------------------+ | | - * 1: ÆÉ¤ß¼è¤ê¡¿½ñ¤­¹þ¤ß (0 = ÆÉ¤ß¼è¤ê¤Î¤ß) ---------------------------+ | - * 0: ¥Ú¡¼¥¸Â¸ºß ---------------------------------------------------------+ + * 9-11: ¥·¥¹¥Æ¥à¡¦¥×¥í¥°¥é¥Þ¤¬»ÈÍѲÄǽ --------+ | | | | | | | | | + * 8: ¥°¥í¡¼¥Ð¥ë¡¦¥Ú¡¼¥¸(̵»ë¤µ¤ì¤ë) ------------+ | | | | | | | | + * 7: ¥Ú¡¼¥¸¡¦¥µ¥¤¥º (0 = 4k ¥Ð¥¤¥È¥Ú¡¼¥¸) ---------+ | | | | | | | + * 6: ͽÌó (-) ---------------------------------------+ | | | | | | + * 5: ¥¢¥¯¥»¥¹ -----------------------------------------+ | | | | | + * 4: ¥­¥ã¥Ã¥·¥å̵¸ú --------------------------------------+ | | | | + * 3: ¥é¥¤¥È¥¹¥ë¡¼ --------------------------------------------+ | | | + * 2: ¥æ¡¼¥¶¡¿¥¹¡¼¥Ñ¥Ð¥¤¥¶ (0 = ¥¹¡¼¥Ñ¥Ð¥¤¥¶) ---------------------+ | | + * 1: ÆÉ¤ß¼è¤ê¡¿½ñ¤­¹þ¤ß (0 = ÆÉ¤ß¼è¤ê¤Î¤ß) ---------------------------+ | + * 0: ¥Ú¡¼¥¸Â¸ºß ---------------------------------------------------------+ */ #define CPU_PDE_BASEADDR_MASK 0xfffff000 #define CPU_PDE_GLOBAL_PAGE (1 << 8) @@ -65,23 +61,23 @@ extern "C" { #define CPU_PDE_PRESENT (1 << 0) /* - * ¥Ú¡¼¥¸¡¦¥Ç¥£¥ì¥¯¥È¥ê¡¦¥¨¥ó¥È¥ê (4M ¥Ð¥¤¥È¥Ú¡¼¥¸»ÈÍÑ»þ) + * ¥Ú¡¼¥¸¡¦¥Ç¥£¥ì¥¯¥È¥ê¡¦¥¨¥ó¥È¥ê (4M ¥Ð¥¤¥È¥Ú¡¼¥¸»ÈÍÑ»þ) * * 31 22 21 12 11 9 8 7 6 5 4 3 2 1 0 * +----------------------------+-----------+------+-+--+-+-+---+---+---+---+-+ - * |¥Ú¡¼¥¸¥Æ¡¼¥Ö¥ë¤ÎʪÍý¥¢¥É¥ì¥¹| ͽÌóºÑ¤ß |»ÈÍѲÄ|G|PS|D|A|PCD|PWT|U/S|R/W|P| + * |åãÔ妾å⥯åã¬å¦¾åãÌ妭åá¥çí饥íð¬å¤¤åã²å¦®å⥱| 輰饨¨è¥¯°å¢Á |è¿¥½íô¥£éï¥Ã|G|PS|D|A|PCD|PWT|U/S|R/W|P| * +----------------------------+-----------+------+-+--+-+-+---+---+---+---+-+ * | | | | | | | | | | - * 9-11: ¡¦¥­¡¦¥±¡¦¥Ë¡¦à£¥ò¡¦¥é¡¦ú§¡¼¡¦ò§¡«¡¢¥ã¥µ¥Í¥Ø¥à¥¤¥È¥Ì¥¹ --------+ | | | | | | | | | - * 8: ¡¦¡¼¡¦ú£¥·¡¦¥ß¡¦ö£¥ò¡¦¥ì¡£¥·¡¦¥¯ ------------------------+ | | | | | | | | - * 7: ¡¦¥ì¡£¥·¡¦¥¯¡£¥ò¡¦¥ª¡¦¡¢¡¦¥³ (1 = 4M ¡¦¥ß¡¦¡¢¡¦¥Í¡¦¥ì¡£¥·¡¦¥¯) ---------+ | | | | | | | - * 6: ¡¦¥¿¡£¥·¡¦¥Ë¡¦¡× ---------------------------------------+ | | | | | | - * 5: ¡¦¡Ö¡¦¥Ã¡¦¥µ¡¦¥± -----------------------------------------+ | | | | | - * 4: ¡¦¥å¡¦æ§¥Æ¡¦¥­¡¦êÎ¥ª¥¯--------------------------------------+ | | | | - * 3: ¡¦ò§¡¢¡¦¥Í¡¦¥±¡¦ö£¥· --------------------------------------------+ | | | - * 2: ¡¦ì£¥·¡¦¥«¡£¥½¡¦¥±¡£¥·¡¦¥à¡¦¥ß¡¦¡¢¡¦¥« (0 = ¡¦¥±¡£¥·¡¦¥à¡¦¥ß¡¦¡¢¡¦¥«) ---------------------+ | | - * 1: ¥Ë¥Î¡¢¡¬¥·ð¦ô£¥½¥¹ñ¤­¹þ¤(0 = ÆÉ¤ß¼è¤ê¤Î¤ß) ---------------------------+ | - * 0: ¥Ú¡¼¥¸Â¸ºß ---------------------------------------------------------+ + * 9-11: ¥·¥¹¥Æ¥à¡¦¥×¥í¥°¥é¥Þ¤¬»ÈÍѲÄǽ --------+ | | | | | | | | | + * 8: ¥°¥í¡¼¥Ð¥ë¡¦¥Ú¡¼¥¸ ------------------------+ | | | | | | | | + * 7: ¥Ú¡¼¥¸¡¦¥µ¥¤¥º (1 = 4M ¥Ð¥¤¥È¥Ú¡¼¥¸) ---------+ | | | | | | | + * 6: ¥À¡¼¥Æ¥£ ---------------------------------------+ | | | | | | + * 5: ¥¢¥¯¥»¥¹ -----------------------------------------+ | | | | | + * 4: ¥­¥ã¥Ã¥·¥å̵¸ú --------------------------------------+ | | | | + * 3: ¥é¥¤¥È¥¹¥ë¡¼ --------------------------------------------+ | | | + * 2: ¥æ¡¼¥¶¡¿¥¹¡¼¥Ñ¥Ð¥¤¥¶ (0 = ¥¹¡¼¥Ñ¥Ð¥¤¥¶) ---------------------+ | | + * 1: ÆÉ¤ß¼è¤ê¡¿½ñ¤­¹þ¤ß (0 = ÆÉ¤ß¼è¤ê¤Î¤ß) ---------------------------+ | + * 0: ¥Ú¡¼¥¸Â¸ºß ---------------------------------------------------------+ */ #define CPU_PDE_4M_BASEADDR_MASK 0xffc00000 #define CPU_PDE_4M_GLOBAL_PAGE (1 << 8) @@ -95,23 +91,23 @@ extern "C" { #define CPU_PDE_4M_PRESENT (1 << 0) /* - * ¥Ú¡¼¥¸¡¦¥Æ¡¼¥Ö¥ë¡¦¥¨¥ó¥È¥ê (4k ¥Ð¥¤¥È¡¦¥Ú¡¼¥¸) + * åãÔ妾å⥯å㥵åã¬å¦¾åãÌ妭å㥵å⥣å㥦åã°å¦¬ (4k åãÀ夦åã°å¦½åãÔ妾å⥯) * * 31 12 11 9 8 7 6 5 4 3 2 1 0 * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+ - * | ¡¦¥ì¡£¥·¡¦¥¯¡¢¥Û¡¦¥ë¡£¥·¡¦¥±¡£¥ò¡¦¡Ö¡¦¥Î¡¦ø§¥± |¥µ¥Í¥Ø¥à¥¤¥È|G|-|D|A|PCD|PWT|U/S|R/W|P| + * | åãÔ妾å⥯åá¥çåãÒ妾å⥱å㥵åâ¡Öåã²å¦®å⥱ |è¿¥½íô¥£éï¥Ã|G|-|D|A|PCD|PWT|U/S|R/W|P| * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+ * | | | | | | | | | | - * 9-11: ¡¦¥­¡¦¥±¡¦¥Ë¡¦à£¥ò¡¦¥é¡¦ú§¡¼¡¦ò§¡«¡¢¥ã¥µ¥Í¥Ø¥à¥¤¥È¥Ì¥¹ -------+ | | | | | | | | | - * 8: ¡¦¡¼¡¦ú£¥·¡¦¥ß¡¦ö£¥ò¡¦¥ì¡£¥·¡¦¥¯ -----------------------+ | | | | | | | | - * 7: ¥Ø¥¹¥Õ(-) -----------------------------------+ | | | | | | | - * 6: ¥À¡¼¥Æ¥£ -------------------------------------+ | | | | | | - * 5: ¥¢¥¯¥»¥¹ ---------------------------------------+ | | | | | - * 4: ¥­¥ã¥Ã¥·¥å̵¸ú ------------------------------------+ | | | | - * 3: ¥é¥¤¥È¥¹¥ë¡¼ ------------------------------------------+ | | | - * 2: ¥æ¡¼¥¶¡¿¥¹¡¼¥Ñ¥Ð¥¤¥¶ (0 = ¥¹¡¼¥Ñ¥Ð¥¤¥¶) -------------------+ | | - * 1: ÆÉ¤ß¼è¤ê¡¿½ñ¤­¹þ¤ß (0 = ÆÉ¤ß¼è¤ê¤Î¤ß) -------------------------+ | - * 0: ¥Ú¡¼¥¸Â¸ºß -------------------------------------------------------+ + * 9-11: ¥·¥¹¥Æ¥à¡¦¥×¥í¥°¥é¥Þ¤¬»ÈÍѲÄǽ -------+ | | | | | | | | | + * 8: ¥°¥í¡¼¥Ð¥ë¡¦¥Ú¡¼¥¸ -----------------------+ | | | | | | | | + * 7: ͽÌó (-) -----------------------------------+ | | | | | | | + * 6: ¥À¡¼¥Æ¥£ -------------------------------------+ | | | | | | + * 5: ¥¢¥¯¥»¥¹ ---------------------------------------+ | | | | | + * 4: ¥­¥ã¥Ã¥·¥å̵¸ú ------------------------------------+ | | | | + * 3: ¥é¥¤¥È¥¹¥ë¡¼ ------------------------------------------+ | | | + * 2: ¥æ¡¼¥¶¡¿¥¹¡¼¥Ñ¥Ð¥¤¥¶ (0 = ¥¹¡¼¥Ñ¥Ð¥¤¥¶) -------------------+ | | + * 1: ÆÉ¤ß¼è¤ê¡¿½ñ¤­¹þ¤ß (0 = ÆÉ¤ß¼è¤ê¤Î¤ß) -------------------------+ | + * 0: ¥Ú¡¼¥¸Â¸ºß -------------------------------------------------------+ */ #define CPU_PTE_BASEADDR_MASK 0xfffff000 #define CPU_PTE_GLOBAL_PAGE (1 << 8) @@ -128,8 +124,11 @@ extern "C" { /* * linear address memory access function */ -void MEMCALL cpu_memory_access_la_region(UINT32 address, UINT length, const int ucrw, BYTE *data); -void MEMCALL paging_check(UINT32 laddr, UINT length, const int ucrw); +void MEMCALL cpu_memory_access_la_region(UINT32 address, UINT length, const int ucrw, UINT8 *data); +UINT32 MEMCALL laddr2paddr(const UINT32 laddr, const int ucrw); +#define laddr_to_paddr(laddr, ucrw) \ + (!CPU_STAT_PAGING) ? (laddr) : (laddr2paddr((laddr), (ucrw))) + /* ucrw */ #define CPU_PAGE_WRITE (1 << 0) @@ -140,17 +139,19 @@ void MEMCALL paging_check(UINT32 laddr, #define CPU_PAGE_READ_DATA (CPU_PAGE_DATA) #define CPU_PAGE_WRITE_DATA (CPU_PAGE_WRITE|CPU_PAGE_DATA) -#if defined(IA32_PAGING_EACHSIZE) - -UINT8 MEMCALL cpu_memory_access_la_RMW_b(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg) GCC_ATTR_REGPARM; -UINT16 MEMCALL cpu_memory_access_la_RMW_w(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg) GCC_ATTR_REGPARM; -UINT32 MEMCALL cpu_memory_access_la_RMW_d(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg) GCC_ATTR_REGPARM; -UINT8 MEMCALL cpu_linear_memory_read_b(UINT32 laddr, const int ucrw) GCC_ATTR_REGPARM; -UINT16 MEMCALL cpu_linear_memory_read_w(UINT32 laddr, const int ucrw) GCC_ATTR_REGPARM; -UINT32 MEMCALL cpu_linear_memory_read_d(UINT32 laddr, const int ucrw) GCC_ATTR_REGPARM; -void MEMCALL cpu_linear_memory_write_b(UINT32 laddr, UINT8 value, const int user_mode) GCC_ATTR_REGPARM; -void MEMCALL cpu_linear_memory_write_w(UINT32 laddr, UINT16 value, const int user_mode) GCC_ATTR_REGPARM; -void MEMCALL cpu_linear_memory_write_d(UINT32 laddr, UINT32 value, const int user_mode) GCC_ATTR_REGPARM; +UINT8 MEMCALL cpu_memory_access_la_RMW_b(UINT32 laddr, UINT32 (CPUCALL *func)(UINT32, void *), void *arg); +UINT16 MEMCALL cpu_memory_access_la_RMW_w(UINT32 laddr, UINT32 (CPUCALL *func)(UINT32, void *), void *arg); +UINT32 MEMCALL cpu_memory_access_la_RMW_d(UINT32 laddr, UINT32 (CPUCALL *func)(UINT32, void *), void *arg); +UINT8 MEMCALL cpu_linear_memory_read_b(UINT32 laddr, const int ucrw); +UINT16 MEMCALL cpu_linear_memory_read_w(UINT32 laddr, const int ucrw); +UINT32 MEMCALL cpu_linear_memory_read_d(UINT32 laddr, const int ucrw); +UINT64 MEMCALL cpu_linear_memory_read_q(UINT32 laddr, const int ucrw); +REG80 MEMCALL cpu_linear_memory_read_f(UINT32 laddr, const int ucrw); +void MEMCALL cpu_linear_memory_write_b(UINT32 laddr, UINT8 value, const int user_mode); +void MEMCALL cpu_linear_memory_write_w(UINT32 laddr, UINT16 value, const int user_mode); +void MEMCALL cpu_linear_memory_write_d(UINT32 laddr, UINT32 value, const int user_mode); +void MEMCALL cpu_linear_memory_write_q(UINT32 laddr, UINT64 value, const int user_mode); +void MEMCALL cpu_linear_memory_write_f(UINT32 laddr, const REG80 *value, const int user_mode); #define cpu_lmemoryread(a,pl) \ (!CPU_STAT_PAGING) ? \ @@ -165,6 +166,10 @@ void MEMCALL cpu_linear_memory_write_d(U (!CPU_STAT_PAGING) ? \ cpu_memoryread_d(a) : \ cpu_linear_memory_read_d(a,CPU_PAGE_READ_DATA | (pl)) +#define cpu_lmemoryread_q(a,pl) \ + (!CPU_STAT_PAGING) ? \ + cpu_memoryread_q(a) : \ + cpu_linear_memory_read_q(a,CPU_PAGE_READ_DATA | (pl)) #define cpu_lmemorywrite(a,v,pl) \ (!CPU_STAT_PAGING) ? \ @@ -176,53 +181,9 @@ void MEMCALL cpu_linear_memory_write_d(U #define cpu_lmemorywrite_d(a,v,pl) \ (!CPU_STAT_PAGING) ? \ cpu_memorywrite_d(a,v) : cpu_linear_memory_write_d(a,v,pl) - -#else /* !IA32_PAGING_EACHSIZE */ - -UINT32 MEMCALL cpu_memory_access_la_RMW(UINT32 laddr, UINT length, UINT32 (*func)(UINT32, void *), void *arg) GCC_ATTR_REGPARM; -#define cpu_memory_access_la_RMW_b(l,f,a) cpu_memory_access_la_RMW(l,1,f,a) -#define cpu_memory_access_la_RMW_w(l,f,a) cpu_memory_access_la_RMW(l,2,f,a) -#define cpu_memory_access_la_RMW_d(l,f,a) cpu_memory_access_la_RMW(l,4,f,a) - -UINT32 MEMCALL cpu_linear_memory_read(UINT32 address, UINT length, const int ucrw) GCC_ATTR_REGPARM; -#define cpu_linear_memory_read_b(a,pl) cpu_linear_memory_read(a,1,pl) -#define cpu_linear_memory_read_w(a,pl) cpu_linear_memory_read(a,2,pl) -#define cpu_linear_memory_read_d(a,pl) cpu_linear_memory_read(a,4,pl) - -void MEMCALL cpu_linear_memory_write(UINT32 address, UINT32 value, UINT length, const int user_mode) GCC_ATTR_REGPARM; -#define cpu_linear_memory_write_b(a,v,pl) cpu_linear_memory_write(a,v,1,pl) -#define cpu_linear_memory_write_w(a,v,pl) cpu_linear_memory_write(a,v,2,pl) -#define cpu_linear_memory_write_d(a,v,pl) cpu_linear_memory_write(a,v,4,pl) - -#define cpu_lmemoryread(a,pl) \ +#define cpu_lmemorywrite_q(a,v,pl) \ (!CPU_STAT_PAGING) ? \ - cpu_memoryread(a) : \ - (UINT8)cpu_linear_memory_read(a,1,CPU_PAGE_READ_DATA | (pl)) -#define cpu_lmemoryread_b(a,pl) cpu_lmemoryread(a,pl) -#define cpu_lmemoryread_w(a,pl) \ - (!CPU_STAT_PAGING) ? \ - cpu_memoryread_w(a) : \ - (UINT16)cpu_linear_memory_read(a,2,CPU_PAGE_READ_DATA | (pl)) -#define cpu_lmemoryread_d(a,pl) \ - (!CPU_STAT_PAGING) ? \ - cpu_memoryread_d(a) : \ - cpu_linear_memory_read(a,4,CPU_PAGE_READ_DATA | (pl)) - -#define cpu_lmemorywrite(a,v,pl) \ - (!CPU_STAT_PAGING) ? \ - cpu_memorywrite(a,v) : \ - cpu_linear_memory_write(a,v,1,pl) -#define cpu_lmemorywrite_b(a,v,pl) cpu_lmemorywrite(a,v,pl) -#define cpu_lmemorywrite_w(a,v,pl) \ - (!CPU_STAT_PAGING) ? \ - cpu_memorywrite_w(a,v) : \ - cpu_linear_memory_write(a,v,2,pl) -#define cpu_lmemorywrite_d(a,v,pl) \ - (!CPU_STAT_PAGING) ? \ - cpu_memorywrite_d(a,v) : \ - cpu_linear_memory_write(a,v,4,pl) - -#endif /* IA32_PAGING_EACHSIZE */ + cpu_memorywrite_q(a,v) : cpu_linear_memory_write_q(a,v,pl) /* * linear address memory access with superviser mode @@ -236,18 +197,6 @@ void MEMCALL cpu_linear_memory_write(UIN /* - * CR3 (Page Directory Entry base physical address) - */ -#define set_CR3(cr3) \ -do { \ - VERBOSE(("set_CR3: old = %08x, new = 0x%08x", CPU_CR3, (cr3) & CPU_CR3_MASK)); \ - CPU_CR3 = (cr3) & CPU_CR3_MASK; \ - CPU_STAT_PDE_BASE = CPU_CR3 & CPU_CR3_PD_MASK; \ - tlb_flush(FALSE); \ -} while (/*CONSTCOND*/ 0) - - -/* * TLB function */ typedef struct { @@ -264,18 +213,10 @@ typedef struct { UINT8 *memp; /* shortcut for pre-fetch queue */ } TLB_ENTRY_T; - -#if defined(IA32_SUPPORT_TLB) void tlb_init(void); -void MEMCALL tlb_flush(BOOL allflush) GCC_ATTR_REGPARM; -void MEMCALL tlb_flush_page(UINT32 laddr) GCC_ATTR_REGPARM; -TLB_ENTRY_T* MEMCALL tlb_lookup(const UINT32 laddr, const int ucrw) GCC_ATTR_REGPARM; -#else -#define tlb_init() -#define tlb_flush(allflush) (void)(allflush) -#define tlb_flush_page(la) (void)(la) -#define tlb_lookup(la, ucrw) NULL -#endif +void MEMCALL tlb_flush(BOOL allflush); +void MEMCALL tlb_flush_page(UINT32 laddr); +TLB_ENTRY_T* MEMCALL tlb_lookup(const UINT32 laddr, const int ucrw); #ifdef __cplusplus }