--- np2/i386c/ia32/paging.h 2004/03/05 14:17:35 1.12 +++ np2/i386c/ia32/paging.h 2012/01/23 06:01:44 1.29 @@ -1,5 +1,3 @@ -/* $Id: paging.h,v 1.12 2004/03/05 14:17:35 monaka Exp $ */ - /* * Copyright (c) 2003 NONAKA Kimihiro * All rights reserved. @@ -12,8 +10,6 @@ * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES @@ -35,23 +31,23 @@ extern "C" { #endif /* - * ¥Ú¡¼¥¸¡¦¥Ç¥£¥ì¥¯¥È¥ê¡¦¥¨¥ó¥È¥ê (4K ¥Ð¥¤¥È¥Ú¡¼¥¸»ÈÍÑ»þ) + * ¥Ú¡¼¥¸¡¦¥Ç¥£¥ì¥¯¥È¥ê¡¦¥¨¥ó¥È¥ê (4K ¥Ð¥¤¥È¥Ú¡¼¥¸»ÈÍÑ»þ) * * 31 12 11 9 8 7 6 5 4 3 2 1 0 * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+ - * | ¡¦¥ì¡£¥·¡¦¥¯¡£¥ò¡¦¥Ë¡£¥·¡¦¥è¡¦ö¦¥Û¡¦¥ë¡£¥·¡¦¥±¡£¥ò¡¦¡Ö¡¦¥Î¡¦ø§¥± |¥µ¥Í¥Ø¥à¥¤¥È|G|PS|-|A|PCD|PWT|U/S|R/W|P| + * | åãÔ妾å⥯å㥵åã¬å¦¾åãÌ妭åá¥çåãÒ妾å⥱å㥵åâ¡Öåã²å¦®å⥱ |è¿¥½íô¥£éï¥Ã|G|PS|-|A|PCD|PWT|U/S|R/W|P| * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+ * | | | | | | | | | | - * 9-11: ¡¦¥­¡¦¥±¡¦¥Ë¡¦à£¥ò¡¦¥é¡¦ú§¡¼¡¦ò§¡«¡¢¥ã¥µ¥Í¥Ø¥à¥¤¥È¥Ì¥¹ --------+ | | | | | | | | | - * 8: ¡¦¡¼¡¦ú£¥·¡¦¥ß¡¦ö£¥ò¡¦¥ì¡£¥·¡¦¥¯(¥Õ¥ª¥µö¦¥ª¡¢ø¦ ------------+ | | | | | | | | - * 7: ¥Ú¡¼¥¸¡¦¥µ¥¤¥º (0 = 4k ¥Ð¥¤¥È¥Ú¡¼¥¸) ---------+ | | | | | | | - * 6: ͽÌó (-) ---------------------------------------+ | | | | | | - * 5: ¥¢¥¯¥»¥¹ -----------------------------------------+ | | | | | - * 4: ¥­¥ã¥Ã¥·¥å̵¸ú --------------------------------------+ | | | | - * 3: ¥é¥¤¥È¥¹¥ë¡¼ --------------------------------------------+ | | | - * 2: ¥æ¡¼¥¶¡¿¥¹¡¼¥Ñ¥Ð¥¤¥¶ (0 = ¥¹¡¼¥Ñ¥Ð¥¤¥¶) ---------------------+ | | - * 1: ÆÉ¤ß¼è¤ê¡¿½ñ¤­¹þ¤ß (0 = ÆÉ¤ß¼è¤ê¤Î¤ß) ---------------------------+ | - * 0: ¥Ú¡¼¥¸Â¸ºß ---------------------------------------------------------+ + * 9-11: ¥·¥¹¥Æ¥à¡¦¥×¥í¥°¥é¥Þ¤¬»ÈÍѲÄǽ --------+ | | | | | | | | | + * 8: ¥°¥í¡¼¥Ð¥ë¡¦¥Ú¡¼¥¸(̵»ë¤µ¤ì¤ë) ------------+ | | | | | | | | + * 7: ¥Ú¡¼¥¸¡¦¥µ¥¤¥º (0 = 4k ¥Ð¥¤¥È¥Ú¡¼¥¸) ---------+ | | | | | | | + * 6: ͽÌó (-) ---------------------------------------+ | | | | | | + * 5: ¥¢¥¯¥»¥¹ -----------------------------------------+ | | | | | + * 4: ¥­¥ã¥Ã¥·¥å̵¸ú --------------------------------------+ | | | | + * 3: ¥é¥¤¥È¥¹¥ë¡¼ --------------------------------------------+ | | | + * 2: ¥æ¡¼¥¶¡¿¥¹¡¼¥Ñ¥Ð¥¤¥¶ (0 = ¥¹¡¼¥Ñ¥Ð¥¤¥¶) ---------------------+ | | + * 1: ÆÉ¤ß¼è¤ê¡¿½ñ¤­¹þ¤ß (0 = ÆÉ¤ß¼è¤ê¤Î¤ß) ---------------------------+ | + * 0: ¥Ú¡¼¥¸Â¸ºß ---------------------------------------------------------+ */ #define CPU_PDE_BASEADDR_MASK 0xfffff000 #define CPU_PDE_GLOBAL_PAGE (1 << 8) @@ -65,23 +61,23 @@ extern "C" { #define CPU_PDE_PRESENT (1 << 0) /* - * ¥Ú¡¼¥¸¡¦¥Ç¥£¥ì¥¯¥È¥ê¡¦¥¨¥ó¥È¥ê (4M ¥Ð¥¤¥È¥Ú¡¼¥¸»ÈÍÑ»þ) + * ¥Ú¡¼¥¸¡¦¥Ç¥£¥ì¥¯¥È¥ê¡¦¥¨¥ó¥È¥ê (4M ¥Ð¥¤¥È¥Ú¡¼¥¸»ÈÍÑ»þ) * * 31 22 21 12 11 9 8 7 6 5 4 3 2 1 0 * +----------------------------+-----------+------+-+--+-+-+---+---+---+---+-+ - * |¥Ú¡¼¥¸¥Æ¡¼¥Ö¥ë¤ÎʪÍý¥¢¥É¥ì¥¹| ͽÌóºÑ¤ß |»ÈÍѲÄ|G|PS|D|A|PCD|PWT|U/S|R/W|P| + * |åãÔ妾å⥯åã¬å¦¾åãÌ妭åá¥çí饥íð¬å¤¤åã²å¦®å⥱| 輰饨¨è¥¯°å¢Á |è¿¥½íô¥£éï¥Ã|G|PS|D|A|PCD|PWT|U/S|R/W|P| * +----------------------------+-----------+------+-+--+-+-+---+---+---+---+-+ * | | | | | | | | | | - * 9-11: ¡¦¥­¡¦¥±¡¦¥Ë¡¦à£¥ò¡¦¥é¡¦ú§¡¼¡¦ò§¡«¡¢¥ã¥µ¥Í¥Ø¥à¥¤¥È¥Ì¥¹ --------+ | | | | | | | | | - * 8: ¡¦¡¼¡¦ú£¥·¡¦¥ß¡¦ö£¥ò¡¦¥ì¡£¥·¡¦¥¯ ------------------------+ | | | | | | | | - * 7: ¡¦¥ì¡£¥·¡¦¥¯¡£¥ò¡¦¥ª¡¦¡¢¡¦¥³ (1 = 4M ¡¦¥ß¡¦¡¢¡¦¥Í¡¦¥ì¡£¥·¡¦¥¯) ---------+ | | | | | | | - * 6: ¡¦¥¿¡£¥·¡¦¥Ë¡¦¡× ---------------------------------------+ | | | | | | - * 5: ¡¦¡Ö¡¦¥Ã¡¦¥µ¡¦¥± -----------------------------------------+ | | | | | - * 4: ¡¦¥å¡¦æ§¥Æ¡¦¥­¡¦êÎ¥ª¥¯--------------------------------------+ | | | | - * 3: ¡¦ò§¡¢¡¦¥Í¡¦¥±¡¦ö£¥· --------------------------------------------+ | | | - * 2: ¡¦ì£¥·¡¦¥«¡£¥½¡¦¥±¡£¥·¡¦¥à¡¦¥ß¡¦¡¢¡¦¥« (0 = ¡¦¥±¡£¥·¡¦¥à¡¦¥ß¡¦¡¢¡¦¥«) ---------------------+ | | - * 1: ¥Ë¥Î¡¢¡¬¥·ð¦ô£¥½¥¹ñ¤­¹þ¤(0 = ÆÉ¤ß¼è¤ê¤Î¤ß) ---------------------------+ | - * 0: ¥Ú¡¼¥¸Â¸ºß ---------------------------------------------------------+ + * 9-11: ¥·¥¹¥Æ¥à¡¦¥×¥í¥°¥é¥Þ¤¬»ÈÍѲÄǽ --------+ | | | | | | | | | + * 8: ¥°¥í¡¼¥Ð¥ë¡¦¥Ú¡¼¥¸ ------------------------+ | | | | | | | | + * 7: ¥Ú¡¼¥¸¡¦¥µ¥¤¥º (1 = 4M ¥Ð¥¤¥È¥Ú¡¼¥¸) ---------+ | | | | | | | + * 6: ¥À¡¼¥Æ¥£ ---------------------------------------+ | | | | | | + * 5: ¥¢¥¯¥»¥¹ -----------------------------------------+ | | | | | + * 4: ¥­¥ã¥Ã¥·¥å̵¸ú --------------------------------------+ | | | | + * 3: ¥é¥¤¥È¥¹¥ë¡¼ --------------------------------------------+ | | | + * 2: ¥æ¡¼¥¶¡¿¥¹¡¼¥Ñ¥Ð¥¤¥¶ (0 = ¥¹¡¼¥Ñ¥Ð¥¤¥¶) ---------------------+ | | + * 1: ÆÉ¤ß¼è¤ê¡¿½ñ¤­¹þ¤ß (0 = ÆÉ¤ß¼è¤ê¤Î¤ß) ---------------------------+ | + * 0: ¥Ú¡¼¥¸Â¸ºß ---------------------------------------------------------+ */ #define CPU_PDE_4M_BASEADDR_MASK 0xffc00000 #define CPU_PDE_4M_GLOBAL_PAGE (1 << 8) @@ -95,23 +91,23 @@ extern "C" { #define CPU_PDE_4M_PRESENT (1 << 0) /* - * ¥Ú¡¼¥¸¡¦¥Æ¡¼¥Ö¥ë¡¦¥¨¥ó¥È¥ê (4k ¥Ð¥¤¥È¡¦¥Ú¡¼¥¸) + * åãÔ妾å⥯å㥵åã¬å¦¾åãÌ妭å㥵å⥣å㥦åã°å¦¬ (4k åãÀ夦åã°å¦½åãÔ妾å⥯) * * 31 12 11 9 8 7 6 5 4 3 2 1 0 * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+ - * | ¡¦¥ì¡£¥·¡¦¥¯¡¢¥Û¡¦¥ë¡£¥·¡¦¥±¡£¥ò¡¦¡Ö¡¦¥Î¡¦ø§¥± |¥µ¥Í¥Ø¥à¥¤¥È|G|-|D|A|PCD|PWT|U/S|R/W|P| + * | åãÔ妾å⥯åá¥çåãÒ妾å⥱å㥵åâ¡Öåã²å¦®å⥱ |è¿¥½íô¥£éï¥Ã|G|-|D|A|PCD|PWT|U/S|R/W|P| * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+ * | | | | | | | | | | - * 9-11: ¡¦¥­¡¦¥±¡¦¥Ë¡¦à£¥ò¡¦¥é¡¦ú§¡¼¡¦ò§¡«¡¢¥ã¥µ¥Í¥Ø¥à¥¤¥È¥Ì¥¹ -------+ | | | | | | | | | - * 8: ¡¦¡¼¡¦ú£¥·¡¦¥ß¡¦ö£¥ò¡¦¥ì¡£¥·¡¦¥¯ -----------------------+ | | | | | | | | - * 7: ¥Ø¥¹¥Õ(-) -----------------------------------+ | | | | | | | - * 6: ¥À¡¼¥Æ¥£ -------------------------------------+ | | | | | | - * 5: ¥¢¥¯¥»¥¹ ---------------------------------------+ | | | | | - * 4: ¥­¥ã¥Ã¥·¥å̵¸ú ------------------------------------+ | | | | - * 3: ¥é¥¤¥È¥¹¥ë¡¼ ------------------------------------------+ | | | - * 2: ¥æ¡¼¥¶¡¿¥¹¡¼¥Ñ¥Ð¥¤¥¶ (0 = ¥¹¡¼¥Ñ¥Ð¥¤¥¶) -------------------+ | | - * 1: ÆÉ¤ß¼è¤ê¡¿½ñ¤­¹þ¤ß (0 = ÆÉ¤ß¼è¤ê¤Î¤ß) -------------------------+ | - * 0: ¥Ú¡¼¥¸Â¸ºß -------------------------------------------------------+ + * 9-11: ¥·¥¹¥Æ¥à¡¦¥×¥í¥°¥é¥Þ¤¬»ÈÍѲÄǽ -------+ | | | | | | | | | + * 8: ¥°¥í¡¼¥Ð¥ë¡¦¥Ú¡¼¥¸ -----------------------+ | | | | | | | | + * 7: ͽÌó (-) -----------------------------------+ | | | | | | | + * 6: ¥À¡¼¥Æ¥£ -------------------------------------+ | | | | | | + * 5: ¥¢¥¯¥»¥¹ ---------------------------------------+ | | | | | + * 4: ¥­¥ã¥Ã¥·¥å̵¸ú ------------------------------------+ | | | | + * 3: ¥é¥¤¥È¥¹¥ë¡¼ ------------------------------------------+ | | | + * 2: ¥æ¡¼¥¶¡¿¥¹¡¼¥Ñ¥Ð¥¤¥¶ (0 = ¥¹¡¼¥Ñ¥Ð¥¤¥¶) -------------------+ | | + * 1: ÆÉ¤ß¼è¤ê¡¿½ñ¤­¹þ¤ß (0 = ÆÉ¤ß¼è¤ê¤Î¤ß) -------------------------+ | + * 0: ¥Ú¡¼¥¸Â¸ºß -------------------------------------------------------+ */ #define CPU_PTE_BASEADDR_MASK 0xfffff000 #define CPU_PTE_GLOBAL_PAGE (1 << 8) @@ -124,102 +120,225 @@ extern "C" { #define CPU_PTE_WRITABLE (1 << 1) #define CPU_PTE_PRESENT (1 << 0) +#define CPU_PAGE_SIZE 0x1000 +#define CPU_PAGE_MASK (CPU_PAGE_SIZE - 1) -/* - * linear address memory access function - */ -void MEMCALL cpu_memory_access_la_region(UINT32 address, UINT length, int crw, int user_mode, BYTE *data); -UINT32 MEMCALL cpu_linear_memory_read(UINT32 address, UINT length, int crw, int user_mode); -void MEMCALL cpu_linear_memory_write(UINT32 address, UINT32 value, UINT length, int user_mode); -void MEMCALL paging_check(UINT32 laddr, UINT length, int crw, int user_mode); - -/* crw */ -#define CPU_PAGE_READ (0 << 0) +/* ucrw */ #define CPU_PAGE_WRITE (1 << 0) #define CPU_PAGE_CODE (1 << 1) #define CPU_PAGE_DATA (1 << 2) -#define CPU_PAGE_READ_CODE (CPU_PAGE_READ|CPU_PAGE_CODE) -#define CPU_PAGE_READ_DATA (CPU_PAGE_READ|CPU_PAGE_DATA) +#define CPU_PAGE_USER_MODE (1 << 3) /* == CPU_MODE_USER */ +#define CPU_PAGE_READ_CODE (CPU_PAGE_CODE) +#define CPU_PAGE_READ_DATA (CPU_PAGE_DATA) #define CPU_PAGE_WRITE_DATA (CPU_PAGE_WRITE|CPU_PAGE_DATA) +UINT8 MEMCALL cpu_memory_access_la_RMW_b(UINT32 laddr, UINT32 (CPUCALL *func)(UINT32, void *), void *arg); +UINT16 MEMCALL cpu_memory_access_la_RMW_w(UINT32 laddr, UINT32 (CPUCALL *func)(UINT32, void *), void *arg); +UINT32 MEMCALL cpu_memory_access_la_RMW_d(UINT32 laddr, UINT32 (CPUCALL *func)(UINT32, void *), void *arg); +UINT8 MEMCALL cpu_linear_memory_read_b(UINT32 laddr, int ucrw); +UINT16 MEMCALL cpu_linear_memory_read_w(UINT32 laddr, int ucrw); +UINT32 MEMCALL cpu_linear_memory_read_d(UINT32 laddr, int ucrw); +UINT64 MEMCALL cpu_linear_memory_read_q(UINT32 laddr, int ucrw); +REG80 MEMCALL cpu_linear_memory_read_f(UINT32 laddr, int ucrw); +void MEMCALL cpu_linear_memory_write_b(UINT32 laddr, UINT8 value, int ucrw); +void MEMCALL cpu_linear_memory_write_w(UINT32 laddr, UINT16 value, int ucrw); +void MEMCALL cpu_linear_memory_write_d(UINT32 laddr, UINT32 value, int ucrw); +void MEMCALL cpu_linear_memory_write_q(UINT32 laddr, UINT64 value, int ucrw); +void MEMCALL cpu_linear_memory_write_f(UINT32 laddr, const REG80 *value, int ucrw); + +/* + * linear address memory access function with TLB + */ +/* RMW */ +STATIC_INLINE UINT8 MEMCALL +cpu_lmemory_RMW_b(UINT32 laddr, UINT32 (CPUCALL *func)(UINT32, void *), void *arg) +{ + UINT32 result; + UINT8 value; + + if (!CPU_STAT_PAGING) { + value = cpu_memoryread_b(laddr); + result = (*func)(value, arg); + cpu_memorywrite_b(laddr, result); + return value; + } + return cpu_memory_access_la_RMW_b(laddr, func, arg); +} + +STATIC_INLINE UINT16 MEMCALL +cpu_lmemory_RMW_w(UINT32 laddr, UINT32 (CPUCALL *func)(UINT32, void *), void *arg) +{ + UINT32 result; + UINT16 value; + + if (!CPU_STAT_PAGING) { + value = cpu_memoryread_w(laddr); + result = (*func)(value, arg); + cpu_memorywrite_w(laddr, result); + return value; + } + return cpu_memory_access_la_RMW_w(laddr, func, arg); +} + +STATIC_INLINE UINT32 MEMCALL +cpu_lmemory_RMW_d(UINT32 laddr, UINT32 (CPUCALL *func)(UINT32, void *), void *arg) +{ + UINT32 result; + UINT32 value; + + if (!CPU_STAT_PAGING) { + value = cpu_memoryread_d(laddr); + result = (*func)(value, arg); + cpu_memorywrite_d(laddr, result); + return value; + } + return cpu_memory_access_la_RMW_d(laddr, func, arg); +} + +/* read */ +STATIC_INLINE UINT8 MEMCALL +cpu_lmemoryread_b(UINT32 laddr, int ucrw) +{ + + if (!CPU_STAT_PAGING) + return cpu_memoryread_b(laddr); + return cpu_linear_memory_read_b(laddr, ucrw); +} +#define cpu_lmemoryread(a,ucrw) cpu_lmemoryread_b((a),(ucrw)) + +STATIC_INLINE UINT16 MEMCALL +cpu_lmemoryread_w(UINT32 laddr, int ucrw) +{ + + if (!CPU_STAT_PAGING) + return cpu_memoryread_w(laddr); + return cpu_linear_memory_read_w(laddr, ucrw); +} + +STATIC_INLINE UINT32 MEMCALL +cpu_lmemoryread_d(UINT32 laddr, int ucrw) +{ + + if (!CPU_STAT_PAGING) + return cpu_memoryread_d(laddr); + return cpu_linear_memory_read_d(laddr, ucrw); +} + +STATIC_INLINE UINT64 +cpu_lmemoryread_q(UINT32 laddr, int ucrw) +{ + + if (!CPU_STAT_PAGING) + return cpu_memoryread_q(laddr); + return cpu_linear_memory_read_q(laddr, ucrw); +} + +STATIC_INLINE REG80 +cpu_lmemoryread_f(UINT32 laddr, int ucrw) +{ + + if (!CPU_STAT_PAGING) + return cpu_memoryread_f(laddr); + return cpu_linear_memory_read_f(laddr, ucrw); +} + +/* write */ +STATIC_INLINE void MEMCALL +cpu_lmemorywrite_b(UINT32 laddr, UINT8 value, int ucrw) +{ + + if (!CPU_STAT_PAGING) { + cpu_memorywrite_b(laddr, value); + return; + } + cpu_linear_memory_write_b(laddr, value, ucrw); +} +#define cpu_lmemorywrite(a,v,ucrw) cpu_lmemorywrite_b((a),(v),(ucrw)) + +STATIC_INLINE void MEMCALL +cpu_lmemorywrite_w(UINT32 laddr, UINT16 value, int ucrw) +{ + + if (!CPU_STAT_PAGING) { + cpu_memorywrite_w(laddr, value); + return; + } + cpu_linear_memory_write_w(laddr, value, ucrw); +} + +STATIC_INLINE void MEMCALL +cpu_lmemorywrite_d(UINT32 laddr, UINT32 value, int ucrw) +{ + + if (!CPU_STAT_PAGING) { + cpu_memorywrite_d(laddr, value); + return; + } + cpu_linear_memory_write_d(laddr, value, ucrw); +} + +STATIC_INLINE void MEMCALL +cpu_lmemorywrite_q(UINT32 laddr, UINT64 value, int ucrw) +{ + + if (!CPU_STAT_PAGING) { + cpu_memorywrite_q(laddr, value); + return; + } + cpu_linear_memory_write_q(laddr, value, ucrw); +} + +STATIC_INLINE void MEMCALL +cpu_lmemorywrite_f(UINT32 laddr, const REG80 *value, int ucrw) +{ + + if (!CPU_STAT_PAGING) { + cpu_memorywrite_f(laddr, value); + return; + } + cpu_linear_memory_write_f(laddr, value, ucrw); +} -#define cpu_lmemoryread(a,pl) \ - (!CPU_STAT_PAGING) ? \ - cpu_memoryread(a) : \ - (UINT8)cpu_linear_memory_read(a,1,CPU_PAGE_READ_DATA,pl) -#define cpu_lmemoryread_w(a,pl) \ - (!CPU_STAT_PAGING) ? \ - cpu_memoryread_w(a) : \ - (UINT16)cpu_linear_memory_read(a,2,CPU_PAGE_READ_DATA,pl) -#define cpu_lmemoryread_d(a,pl) \ - (!CPU_STAT_PAGING) ? \ - cpu_memoryread_d(a) : \ - cpu_linear_memory_read(a,4,CPU_PAGE_READ_DATA,pl) - -#define cpu_lmemorywrite(a,v,pl) \ - (!CPU_STAT_PAGING) ? \ - cpu_memorywrite(a,v) : \ - cpu_linear_memory_write(a,v,1,pl) -#define cpu_lmemorywrite_w(a,v,pl) \ - (!CPU_STAT_PAGING) ? \ - cpu_memorywrite_w(a,v) : \ - cpu_linear_memory_write(a,v,2,pl) -#define cpu_lmemorywrite_d(a,v,pl) \ - (!CPU_STAT_PAGING) ? \ - cpu_memorywrite_d(a,v) : \ - cpu_linear_memory_write(a,v,4,pl) - -/* - * code segment - */ -#define cpu_lcmemoryread(a) \ - (!CPU_STAT_PAGING) ? \ - cpu_memoryread(a) : \ - (UINT8)cpu_linear_memory_read(a,1,CPU_PAGE_READ_CODE,CPU_STAT_USER_MODE) -#define cpu_lcmemoryread_w(a) \ - (!CPU_STAT_PAGING) ? \ - cpu_memoryread_w(a) : \ - (UINT16)cpu_linear_memory_read(a,2,CPU_PAGE_READ_CODE,CPU_STAT_USER_MODE) -#define cpu_lcmemoryread_d(a) \ - (!CPU_STAT_PAGING) ? \ - cpu_memoryread_d(a) : \ - cpu_linear_memory_read(a,4,CPU_PAGE_READ_CODE,CPU_STAT_USER_MODE) /* * linear address memory access with superviser mode */ -#define cpu_kmemoryread(a) cpu_lmemoryread(a,CPU_MODE_SUPERVISER) -#define cpu_kmemoryread_w(a) cpu_lmemoryread_w(a,CPU_MODE_SUPERVISER) -#define cpu_kmemoryread_d(a) cpu_lmemoryread_d(a,CPU_MODE_SUPERVISER) -#define cpu_kmemorywrite(a,v) cpu_lmemorywrite(a,v,CPU_MODE_SUPERVISER) -#define cpu_kmemorywrite_w(a,v) cpu_lmemorywrite_w(a,v,CPU_MODE_SUPERVISER) -#define cpu_kmemorywrite_d(a,v) cpu_lmemorywrite_d(a,v,CPU_MODE_SUPERVISER) - +#define cpu_kmemoryread(a) \ + cpu_lmemoryread((a),CPU_PAGE_READ_DATA|CPU_MODE_SUPERVISER) +#define cpu_kmemoryread_w(a) \ + cpu_lmemoryread_w((a),CPU_PAGE_READ_DATA|CPU_MODE_SUPERVISER) +#define cpu_kmemoryread_d(a) \ + cpu_lmemoryread_d((a),CPU_PAGE_READ_DATA|CPU_MODE_SUPERVISER) +#define cpu_kmemorywrite(a,v) \ + cpu_lmemorywrite((a),(v),CPU_PAGE_WRITE_DATA|CPU_MODE_SUPERVISER) +#define cpu_kmemorywrite_w(a,v) \ + cpu_lmemorywrite_w((a),(v),CPU_PAGE_WRITE_DATA|CPU_MODE_SUPERVISER) +#define cpu_kmemorywrite_d(a,v) \ + cpu_lmemorywrite_d((a),(v),CPU_PAGE_WRITE_DATA|CPU_MODE_SUPERVISER) /* - * CR3 (Page Directory Entry base physical address) - */ -#define set_CR3(cr3) \ -do { \ - VERBOSE(("set_CR3: old = %08x, new = 0x%08x", CPU_CR3, (cr3) & CPU_CR3_MASK)); \ - CPU_CR3 = (cr3) & CPU_CR3_MASK; \ - CPU_STAT_PDE_BASE = CPU_CR3 & CPU_CR3_PD_MASK; \ - tlb_flush(FALSE); \ -} while (/*CONSTCOND*/ 0) + * linear address memory access function + */ +void MEMCALL cpu_memory_access_la_region(UINT32 address, UINT length, int ucrw, UINT8 *data); +UINT32 MEMCALL laddr2paddr(UINT32 laddr, int ucrw); +STATIC_INLINE UINT32 MEMCALL +laddr_to_paddr(UINT32 laddr, int ucrw) +{ + + if (!CPU_STAT_PAGING) + return laddr; + return laddr2paddr(laddr, ucrw); +} /* * TLB function */ -#if defined(IA32_SUPPORT_TLB) +struct tlb_entry; void tlb_init(void); -void tlb_flush(BOOL allflush); -void tlb_flush_page(UINT32 laddr); -#else -#define tlb_init() -#define tlb_flush(allflush) (void)(allflush) -#define tlb_flush_page(laddr) (void)(laddr) -#endif +void MEMCALL tlb_flush(BOOL allflush); +void MEMCALL tlb_flush_page(UINT32 laddr); +struct tlb_entry *MEMCALL tlb_lookup(UINT32 laddr, int ucrw); #ifdef __cplusplus }