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| version 1.10, 2004/02/04 13:24:35 | version 1.11, 2004/02/05 16:43:44 |
|---|---|
| Line 47 load_segreg(int idx, WORD selector, int | Line 47 load_segreg(int idx, WORD selector, int |
| CPU_REGS_SREG(idx) = selector; | CPU_REGS_SREG(idx) = selector; |
| memset(&sd, 0, sizeof(sd)); | memset(&sd, 0, sizeof(sd)); |
| if (idx == CPU_CS_INDEX) { | |
| sd.rpl = CPU_STAT_CPL; | |
| } | |
| sd.u.seg.limit = CPU_STAT_SREGLIMIT(idx); | sd.u.seg.limit = CPU_STAT_SREGLIMIT(idx); |
| CPU_SET_SEGDESC_DEFAULT(&sd, idx, selector); | CPU_SET_SEGDESC_DEFAULT(&sd, idx, selector); |
| CPU_STAT_SREG(idx) = sd; | CPU_STAT_SREG(idx) = sd; |
| if (idx == CPU_CS_INDEX) { | |
| CPU_INST_OP32 = CPU_INST_AS32 = | |
| CPU_STATSAVE.cpu_inst_default.op_32 = | |
| CPU_STATSAVE.cpu_inst_default.as_32 = 0; | |
| } else if (idx == CPU_SS_INDEX) { | |
| CPU_STAT_SS32 = 0; | |
| } | |
| return; | return; |
| } | } |
| Line 70 load_segreg(int idx, WORD selector, int | Line 65 load_segreg(int idx, WORD selector, int |
| ia32_panic("load_segreg: CS"); | ia32_panic("load_segreg: CS"); |
| } | } |
| rv = parse_selector_user(&sel, selector); | rv = parse_selector(&sel, selector); |
| if (rv < 0) { | if (rv < 0) { |
| if ((rv != -2) || (idx == CPU_SS_INDEX)) { | if ((rv != -2) || (idx == CPU_SS_INDEX)) { |
| EXCEPTION(exc, sel.idx); | EXCEPTION(exc, sel.idx); |
| Line 154 load_cs(WORD selector, descriptor_t* sdp | Line 149 load_cs(WORD selector, descriptor_t* sdp |
| CPU_STATSAVE.cpu_inst_default.as_32 = sdp->d; | CPU_STATSAVE.cpu_inst_default.as_32 = sdp->d; |
| CPU_REGS_SREG(CPU_CS_INDEX) = (selector & ~3) | (cpl & 3); | CPU_REGS_SREG(CPU_CS_INDEX) = (selector & ~3) | (cpl & 3); |
| CPU_STAT_SREG(CPU_CS_INDEX) = *sdp; | CPU_STAT_SREG(CPU_CS_INDEX) = *sdp; |
| CPU_STAT_CPL = cpl & 3; | CPU_SET_CPL(cpl & 3); |
| } | } |
| /* | /* |
| Line 166 load_ldtr(WORD selector, int exc) | Line 161 load_ldtr(WORD selector, int exc) |
| selector_t sel; | selector_t sel; |
| int rv; | int rv; |
| rv = parse_selector_user(&sel, selector); | rv = parse_selector(&sel, selector); |
| if (rv < 0 || sel.ldt) { | if (rv < 0 || sel.ldt) { |
| if (rv == -2) { | if (rv == -2) { |
| /* null segment */ | /* null segment */ |
| Line 202 load_ldtr(WORD selector, int exc) | Line 197 load_ldtr(WORD selector, int exc) |
| } | } |
| void | void |
| load_descriptor(descriptor_t *descp, DWORD addr, int user_mode) | load_descriptor(descriptor_t *descp, DWORD addr) |
| { | { |
| DWORD l, h; | DWORD l, h; |
| memset(descp, 0, sizeof(*descp)); | memset(descp, 0, sizeof(*descp)); |
| l = cpu_lmemoryread_d(addr, user_mode); | l = cpu_kmemoryread_d(addr); |
| h = cpu_lmemoryread_d(addr + 4, user_mode); | h = cpu_kmemoryread_d(addr + 4); |
| VERBOSE(("load_descriptor: descriptor address = 0x%08x, h = 0x%08x, l = %08x", addr, h, l)); | VERBOSE(("load_descriptor: descriptor address = 0x%08x, h = 0x%08x, l = %08x", addr, h, l)); |
| descp->flag = 0; | descp->flag = 0; |
| Line 293 load_descriptor(descriptor_t *descp, DWO | Line 288 load_descriptor(descriptor_t *descp, DWO |
| } | } |
| descp->u.seg.segend = descp->u.seg.segbase + descp->u.seg.limit; | descp->u.seg.segend = descp->u.seg.segbase + descp->u.seg.limit; |
| VERBOSE(("load_descriptor: %dbit %sTSS descriptor", descp->d ? 32 : 16, (descp->type & CPU_SYSDESC_TYPE_TSS_BUSY) ? "busy " : "")); | VERBOSE(("load_descriptor: %dbit %sTSS descriptor", descp->d ? 32 : 16, (descp->type & CPU_SYSDESC_TYPE_TSS_BUSY_IND) ? "busy " : "")); |
| VERBOSE(("load_descriptor: TSS base address = 0x%08x, limit = 0x%08x", descp->u.seg.segbase, descp->u.seg.limit)); | VERBOSE(("load_descriptor: TSS base address = 0x%08x, limit = 0x%08x", descp->u.seg.segbase, descp->u.seg.limit)); |
| VERBOSE(("load_descriptor: d = %s, g = %s", descp->d ? "on" : "off", descp->u.seg.g ? "on" : "off")); | VERBOSE(("load_descriptor: d = %s, g = %s", descp->d ? "on" : "off", descp->u.seg.g ? "on" : "off")); |
| break; | break; |
| Line 329 load_descriptor(descriptor_t *descp, DWO | Line 324 load_descriptor(descriptor_t *descp, DWO |
| } | } |
| int | int |
| parse_selector(selector_t* ssp, WORD selector, int user_mode) | parse_selector(selector_t* ssp, WORD selector) |
| { | { |
| DWORD base; | DWORD base; |
| WORD limit; | WORD limit; |
| Line 339 parse_selector(selector_t* ssp, WORD sel | Line 334 parse_selector(selector_t* ssp, WORD sel |
| ssp->idx = selector & ~3; | ssp->idx = selector & ~3; |
| ssp->rpl = selector & 3; | ssp->rpl = selector & 3; |
| ssp->ldt = selector & CPU_SEGMENT_TABLE_IND; | ssp->ldt = selector & CPU_SEGMENT_TABLE_IND; |
| ssp->user_mode = user_mode; | |
| VERBOSE(("parse_selector: selector = %04x, index = %d, RPL = %d, %cDT %c", ssp->selector, ssp->idx >> 3, ssp->rpl, ssp->ldt ? 'L' : 'G', user_mode ? 'u' : 's')); | VERBOSE(("parse_selector: selector = %04x, index = %d, RPL = %d, %cDT", ssp->selector, ssp->idx >> 3, ssp->rpl, ssp->ldt ? 'L' : 'G')); |
| /* descriptor table */ | /* descriptor table */ |
| idx = selector & ~7; | idx = selector & CPU_SEGMENT_SELECTOR_INDEX_MASK; |
| if (ssp->ldt) { | if (ssp->ldt) { |
| /* LDT */ | /* LDT */ |
| if (!CPU_LDTR_DESC.valid) { | if (!CPU_LDTR_DESC.valid) { |
| Line 369 parse_selector(selector_t* ssp, WORD sel | Line 363 parse_selector(selector_t* ssp, WORD sel |
| /* load descriptor */ | /* load descriptor */ |
| ssp->addr = base + idx; | ssp->addr = base + idx; |
| CPU_SET_SEGDESC(&ssp->desc, ssp->addr, ssp->user_mode); | load_descriptor(&ssp->desc, ssp->addr); |
| if (!ssp->desc.valid) { | if (!ssp->desc.valid) { |
| VERBOSE(("parse_selector: segment descriptor is invalid")); | VERBOSE(("parse_selector: segment descriptor is invalid")); |
| return -4; | return -4; |
| Line 391 selector_is_not_present(selector_t *ssp) | Line 385 selector_is_not_present(selector_t *ssp) |
| /* set access bit if code/data segment descriptor */ | /* set access bit if code/data segment descriptor */ |
| if (ssp->desc.s) { | if (ssp->desc.s) { |
| h = cpu_lmemoryread_d(ssp->addr + 4, ssp->user_mode); | h = cpu_kmemoryread_d(ssp->addr + 4); |
| if (!(h & CPU_SEGDESC_H_A)) { | if (!(h & CPU_SEGDESC_H_A)) { |
| h |= CPU_SEGDESC_H_A; | h |= CPU_SEGDESC_H_A; |
| cpu_lmemorywrite_d(ssp->addr + 4, h, ssp->user_mode); | cpu_kmemorywrite_d(ssp->addr + 4, h); |
| } | } |
| } | } |