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| version 1.10, 2004/02/04 13:24:35 | version 1.16, 2004/03/23 22:39:40 |
|---|---|
| Line 33 | Line 33 |
| void | void |
| load_segreg(int idx, WORD selector, int exc) | load_segreg(int idx, UINT16 selector, int exc) |
| { | { |
| selector_t sel; | selector_t sel; |
| int rv; | int rv; |
| Line 47 load_segreg(int idx, WORD selector, int | Line 47 load_segreg(int idx, WORD selector, int |
| CPU_REGS_SREG(idx) = selector; | CPU_REGS_SREG(idx) = selector; |
| memset(&sd, 0, sizeof(sd)); | memset(&sd, 0, sizeof(sd)); |
| if (idx == CPU_CS_INDEX) { | |
| sd.rpl = CPU_STAT_CPL; | |
| } | |
| sd.u.seg.limit = CPU_STAT_SREGLIMIT(idx); | sd.u.seg.limit = CPU_STAT_SREGLIMIT(idx); |
| CPU_SET_SEGDESC_DEFAULT(&sd, idx, selector); | CPU_SET_SEGDESC_DEFAULT(&sd, idx, selector); |
| CPU_STAT_SREG(idx) = sd; | CPU_STAT_SREG(idx) = sd; |
| if (idx == CPU_CS_INDEX) { | |
| CPU_INST_OP32 = CPU_INST_AS32 = | |
| CPU_STATSAVE.cpu_inst_default.op_32 = | |
| CPU_STATSAVE.cpu_inst_default.as_32 = 0; | |
| } else if (idx == CPU_SS_INDEX) { | |
| CPU_STAT_SS32 = 0; | |
| } | |
| return; | return; |
| } | } |
| Line 70 load_segreg(int idx, WORD selector, int | Line 65 load_segreg(int idx, WORD selector, int |
| ia32_panic("load_segreg: CS"); | ia32_panic("load_segreg: CS"); |
| } | } |
| rv = parse_selector_user(&sel, selector); | rv = parse_selector(&sel, selector); |
| if (rv < 0) { | if (rv < 0) { |
| if ((rv != -2) || (idx == CPU_SS_INDEX)) { | if ((rv != -2) || (idx == CPU_SS_INDEX)) { |
| EXCEPTION(exc, sel.idx); | EXCEPTION(exc, sel.idx); |
| Line 82 load_segreg(int idx, WORD selector, int | Line 77 load_segreg(int idx, WORD selector, int |
| switch (idx) { | switch (idx) { |
| case CPU_SS_INDEX: | case CPU_SS_INDEX: |
| if ((CPU_STAT_CPL != sel.rpl) || | if ((CPU_STAT_CPL != sel.rpl) |
| !sel.desc.s || sel.desc.u.seg.c || !sel.desc.u.seg.wr || | || (CPU_STAT_CPL != sel.desc.dpl) |
| (CPU_STAT_CPL != sel.desc.dpl)) { | || !sel.desc.s |
| || sel.desc.u.seg.c | |
| || !sel.desc.u.seg.wr) { | |
| EXCEPTION(exc, sel.idx); | EXCEPTION(exc, sel.idx); |
| } | } |
| Line 134 load_segreg(int idx, WORD selector, int | Line 131 load_segreg(int idx, WORD selector, int |
| * load SS register | * load SS register |
| */ | */ |
| void | void |
| load_ss(WORD selector, descriptor_t* sdp, DWORD cpl) | load_ss(UINT16 selector, const descriptor_t *sd, UINT cpl) |
| { | { |
| CPU_STAT_SS32 = sdp->d; | CPU_STAT_SS32 = sd->d; |
| CPU_REGS_SREG(CPU_SS_INDEX) = (selector & ~3) | (cpl & 3); | CPU_REGS_SREG(CPU_SS_INDEX) = (UINT16)((selector & ~3) | (cpl & 3)); |
| CPU_STAT_SREG(CPU_SS_INDEX) = *sdp; | CPU_STAT_SREG(CPU_SS_INDEX) = *sd; |
| } | } |
| /* | /* |
| * load CS register | * load CS register |
| */ | */ |
| void | void |
| load_cs(WORD selector, descriptor_t* sdp, DWORD cpl) | load_cs(UINT16 selector, const descriptor_t *sd, UINT cpl) |
| { | { |
| CPU_INST_OP32 = CPU_INST_AS32 = | CPU_INST_OP32 = CPU_INST_AS32 = |
| CPU_STATSAVE.cpu_inst_default.op_32 = | CPU_STATSAVE.cpu_inst_default.op_32 = |
| CPU_STATSAVE.cpu_inst_default.as_32 = sdp->d; | CPU_STATSAVE.cpu_inst_default.as_32 = sd->d; |
| CPU_REGS_SREG(CPU_CS_INDEX) = (selector & ~3) | (cpl & 3); | CPU_REGS_SREG(CPU_CS_INDEX) = (UINT16)((selector & ~3) | (cpl & 3)); |
| CPU_STAT_SREG(CPU_CS_INDEX) = *sdp; | CPU_STAT_SREG(CPU_CS_INDEX) = *sd; |
| CPU_STAT_CPL = cpl & 3; | CPU_SET_CPL(cpl & 3); |
| } | } |
| /* | /* |
| * load LDT register | * load LDT register |
| */ | */ |
| void | void |
| load_ldtr(WORD selector, int exc) | load_ldtr(UINT16 selector, int exc) |
| { | { |
| selector_t sel; | selector_t sel; |
| int rv; | int rv; |
| rv = parse_selector_user(&sel, selector); | rv = parse_selector(&sel, selector); |
| if (rv < 0 || sel.ldt) { | if (rv < 0 || sel.ldt) { |
| if (rv == -2) { | if (rv == -2) { |
| /* null segment */ | /* null segment */ |
| Line 202 load_ldtr(WORD selector, int exc) | Line 199 load_ldtr(WORD selector, int exc) |
| } | } |
| void | void |
| load_descriptor(descriptor_t *descp, DWORD addr, int user_mode) | load_descriptor(descriptor_t *descp, UINT32 addr) |
| { | { |
| DWORD l, h; | UINT32 l, h; |
| memset(descp, 0, sizeof(*descp)); | memset(descp, 0, sizeof(*descp)); |
| l = cpu_lmemoryread_d(addr, user_mode); | l = cpu_kmemoryread_d(addr); |
| h = cpu_lmemoryread_d(addr + 4, user_mode); | h = cpu_kmemoryread_d(addr + 4); |
| VERBOSE(("load_descriptor: descriptor address = 0x%08x, h = 0x%08x, l = %08x", addr, h, l)); | VERBOSE(("load_descriptor: descriptor address = 0x%08x, h = 0x%08x, l = %08x", addr, h, l)); |
| descp->flag = 0; | descp->flag = 0; |
| descp->p = (h & CPU_DESC_H_P) == CPU_DESC_H_P; | descp->p = (h & CPU_DESC_H_P) == CPU_DESC_H_P; |
| descp->type = (h & CPU_DESC_H_TYPE) >> 8; | descp->type = (UINT8)((h & CPU_DESC_H_TYPE) >> 8); |
| descp->dpl = (h & CPU_DESC_H_DPL) >> 13; | descp->dpl = (UINT8)((h & CPU_DESC_H_DPL) >> 13); |
| descp->s = (h & CPU_DESC_H_S) == CPU_DESC_H_S; | descp->s = (h & CPU_DESC_H_S) == CPU_DESC_H_S; |
| VERBOSE(("load_descriptor: present = %s, type = %d, DPL = %d", descp->p ? "true" : "false", descp->type, descp->dpl)); | VERBOSE(("load_descriptor: present = %s, type = %d, DPL = %d", descp->p ? "true" : "false", descp->type, descp->dpl)); |
| Line 269 load_descriptor(descriptor_t *descp, DWO | Line 266 load_descriptor(descriptor_t *descp, DWO |
| case CPU_SYSDESC_TYPE_TASK: /* task gate */ | case CPU_SYSDESC_TYPE_TASK: /* task gate */ |
| descp->valid = 1; | descp->valid = 1; |
| descp->u.gate.selector = l >> 16; | descp->u.gate.selector = (UINT16)(l >> 16); |
| VERBOSE(("load_descriptor: task descriptor: selector = 0x%04x", descp->u.gate.selector)); | VERBOSE(("load_descriptor: task descriptor: selector = 0x%04x", descp->u.gate.selector)); |
| break; | break; |
| Line 293 load_descriptor(descriptor_t *descp, DWO | Line 290 load_descriptor(descriptor_t *descp, DWO |
| } | } |
| descp->u.seg.segend = descp->u.seg.segbase + descp->u.seg.limit; | descp->u.seg.segend = descp->u.seg.segbase + descp->u.seg.limit; |
| VERBOSE(("load_descriptor: %dbit %sTSS descriptor", descp->d ? 32 : 16, (descp->type & CPU_SYSDESC_TYPE_TSS_BUSY) ? "busy " : "")); | VERBOSE(("load_descriptor: %dbit %sTSS descriptor", descp->d ? 32 : 16, (descp->type & CPU_SYSDESC_TYPE_TSS_BUSY_IND) ? "busy " : "")); |
| VERBOSE(("load_descriptor: TSS base address = 0x%08x, limit = 0x%08x", descp->u.seg.segbase, descp->u.seg.limit)); | VERBOSE(("load_descriptor: TSS base address = 0x%08x, limit = 0x%08x", descp->u.seg.segbase, descp->u.seg.limit)); |
| VERBOSE(("load_descriptor: d = %s, g = %s", descp->d ? "on" : "off", descp->u.seg.g ? "on" : "off")); | VERBOSE(("load_descriptor: d = %s, g = %s", descp->d ? "on" : "off", descp->u.seg.g ? "on" : "off")); |
| break; | break; |
| Line 307 load_descriptor(descriptor_t *descp, DWO | Line 304 load_descriptor(descriptor_t *descp, DWO |
| if ((h & 0x0000000e0) == 0) { | if ((h & 0x0000000e0) == 0) { |
| descp->valid = 1; | descp->valid = 1; |
| descp->d = (h & CPU_GATEDESC_H_D) ? 1:0; | descp->d = (h & CPU_GATEDESC_H_D) ? 1:0; |
| descp->u.gate.selector = l >> 16; | descp->u.gate.selector = (UINT16)(l >> 16); |
| descp->u.gate.offset = h & 0xffff0000; | descp->u.gate.offset = h & 0xffff0000; |
| descp->u.gate.offset |= l & 0xffff; | descp->u.gate.offset |= l & 0xffff; |
| descp->u.gate.count = h & 0x1f; | descp->u.gate.count = (BYTE)(h & 0x1f); |
| VERBOSE(("load_descriptor: %dbit %s gate descriptor", descp->d ? 32 : 16, ((descp->type & CPU_SYSDESC_TYPE_MASKBIT) == CPU_SYSDESC_TYPE_CALL) ? "call" : (((descp->type & CPU_SYSDESC_TYPE_MASKBIT) == CPU_SYSDESC_TYPE_INTR) ? "interrupt" : "trap"))); | VERBOSE(("load_descriptor: %dbit %s gate descriptor", descp->d ? 32 : 16, ((descp->type & CPU_SYSDESC_TYPE_MASKBIT) == CPU_SYSDESC_TYPE_CALL) ? "call" : (((descp->type & CPU_SYSDESC_TYPE_MASKBIT) == CPU_SYSDESC_TYPE_INTR) ? "interrupt" : "trap"))); |
| VERBOSE(("load_descriptor: selector = 0x%04x, offset = 0x%08x, count = %d, d = %s", descp->u.gate.selector, descp->u.gate.offset, descp->u.gate.count, descp->d ? "on" : "off")); | VERBOSE(("load_descriptor: selector = 0x%04x, offset = 0x%08x, count = %d, d = %s", descp->u.gate.selector, descp->u.gate.offset, descp->u.gate.count, descp->d ? "on" : "off")); |
| Line 322 load_descriptor(descriptor_t *descp, DWO | Line 319 load_descriptor(descriptor_t *descp, DWO |
| case 0: case 8: case 10: case 13: /* reserved */ | case 0: case 8: case 10: case 13: /* reserved */ |
| default: | default: |
| descp->valid = 0; | descp->valid = 0; |
| ia32_panic("load_descriptor: bad descriptor (type = %d)", descp->type); | |
| break; | break; |
| } | } |
| } | } |
| } | } |
| int | int |
| parse_selector(selector_t* ssp, WORD selector, int user_mode) | parse_selector(selector_t *ssp, UINT16 selector) |
| { | { |
| DWORD base; | UINT32 base; |
| WORD limit; | UINT limit; |
| WORD idx; | UINT idx; |
| ssp->selector = selector; | ssp->selector = selector; |
| ssp->idx = selector & ~3; | ssp->idx = selector & ~3; |
| ssp->rpl = selector & 3; | ssp->rpl = selector & 3; |
| ssp->ldt = selector & CPU_SEGMENT_TABLE_IND; | ssp->ldt = (UINT8)(selector & CPU_SEGMENT_TABLE_IND); |
| ssp->user_mode = user_mode; | |
| VERBOSE(("parse_selector: selector = %04x, index = %d, RPL = %d, %cDT %c", ssp->selector, ssp->idx >> 3, ssp->rpl, ssp->ldt ? 'L' : 'G', user_mode ? 'u' : 's')); | VERBOSE(("parse_selector: selector = %04x, index = %d, RPL = %d, %cDT", ssp->selector, ssp->idx >> 3, ssp->rpl, ssp->ldt ? 'L' : 'G')); |
| /* descriptor table */ | /* descriptor table */ |
| idx = selector & ~7; | idx = selector & CPU_SEGMENT_SELECTOR_INDEX_MASK; |
| if (ssp->ldt) { | if (ssp->ldt) { |
| /* LDT */ | /* LDT */ |
| if (!CPU_LDTR_DESC.valid) { | if (!CPU_LDTR_DESC.valid) { |
| Line 369 parse_selector(selector_t* ssp, WORD sel | Line 364 parse_selector(selector_t* ssp, WORD sel |
| /* load descriptor */ | /* load descriptor */ |
| ssp->addr = base + idx; | ssp->addr = base + idx; |
| CPU_SET_SEGDESC(&ssp->desc, ssp->addr, ssp->user_mode); | load_descriptor(&ssp->desc, ssp->addr); |
| if (!ssp->desc.valid) { | if (!ssp->desc.valid) { |
| VERBOSE(("parse_selector: segment descriptor is invalid")); | VERBOSE(("parse_selector: segment descriptor is invalid")); |
| return -4; | return -4; |
| Line 379 parse_selector(selector_t* ssp, WORD sel | Line 374 parse_selector(selector_t* ssp, WORD sel |
| } | } |
| int | int |
| selector_is_not_present(selector_t *ssp) | selector_is_not_present(const selector_t *ssp) |
| { | { |
| DWORD h; | UINT32 h; |
| /* not present */ | /* not present */ |
| if (!ssp->desc.p) { | if (!ssp->desc.p) { |
| Line 391 selector_is_not_present(selector_t *ssp) | Line 386 selector_is_not_present(selector_t *ssp) |
| /* set access bit if code/data segment descriptor */ | /* set access bit if code/data segment descriptor */ |
| if (ssp->desc.s) { | if (ssp->desc.s) { |
| h = cpu_lmemoryread_d(ssp->addr + 4, ssp->user_mode); | h = cpu_kmemoryread_d(ssp->addr + 4); |
| if (!(h & CPU_SEGDESC_H_A)) { | if (!(h & CPU_SEGDESC_H_A)) { |
| h |= CPU_SEGDESC_H_A; | h |= CPU_SEGDESC_H_A; |
| cpu_lmemorywrite_d(ssp->addr + 4, h, ssp->user_mode); | cpu_kmemorywrite_d(ssp->addr + 4, h); |
| } | } |
| } | } |