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| version 1.4, 2004/01/13 16:36:00 | version 1.8, 2004/01/27 15:56:57 |
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| Line 46 load_segreg(int idx, WORD selector, int | Line 46 load_segreg(int idx, WORD selector, int |
| /* real-mode or vm86 mode */ | /* real-mode or vm86 mode */ |
| CPU_REGS_SREG(idx) = selector; | CPU_REGS_SREG(idx) = selector; |
| memset(&sd, 0, sizeof(sd)); | |
| sd.u.seg.limit = CPU_STAT_SREGLIMIT(idx); | sd.u.seg.limit = CPU_STAT_SREGLIMIT(idx); |
| CPU_SET_SEGDESC_DEFAULT(&sd, idx, selector); | CPU_SET_SEGDESC_DEFAULT(&sd, idx, selector); |
| CPU_STAT_SREG(idx) = sd; | CPU_STAT_SREG(idx) = sd; |
| if (idx == CPU_CS_INDEX) { | |
| CPU_INST_OP32 = CPU_INST_AS32 = | |
| CPU_STATSAVE.cpu_inst_default.op_32 = | |
| CPU_STATSAVE.cpu_inst_default.as_32 = 0; | |
| } else if (idx == CPU_SS_INDEX) { | |
| CPU_STAT_SS32 = 0; | |
| } | |
| return; | return; |
| } | } |
| /* | /* |
| * protected mode | * protected mode |
| */ | */ |
| VERBOSE(("load_segreg: idx = %d, selector = %04x, exc = %d", idx, selector, exc)); | VERBOSE(("load_segreg: EIP = %04x:%08x, idx = %d, selector = %04x, exc = %d", CPU_CS, CPU_PREV_EIP, idx, selector, exc)); |
| if (idx == CPU_CS_INDEX) { | if (idx == CPU_CS_INDEX) { |
| ia32_panic("load_segreg: sreg(%d)", idx); | ia32_panic("load_segreg: CS"); |
| } | } |
| rv = parse_selector(&sel, selector); | rv = parse_selector(&sel, selector); |
| Line 85 load_segreg(int idx, WORD selector, int | Line 94 load_segreg(int idx, WORD selector, int |
| EXCEPTION(SS_EXCEPTION, sel.idx); | EXCEPTION(SS_EXCEPTION, sel.idx); |
| } | } |
| CPU_STAT_SS32 = sel.desc.d; | load_ss(sel.selector, &sel.desc, sel.selector & 3); |
| CPU_REGS_SREG(idx) = sel.selector; | |
| CPU_STAT_SREG(idx) = sel.desc; | |
| break; | break; |
| case CPU_ES_INDEX: | case CPU_ES_INDEX: |
| case CPU_DS_INDEX: | case CPU_DS_INDEX: |
| case CPU_FS_INDEX: | case CPU_FS_INDEX: |
| case CPU_GS_INDEX: | case CPU_GS_INDEX: |
| /* !(system segment || non-readble code segment */ | /* !(system segment || non-readable code segment) */ |
| if (!sel.desc.s | if (!sel.desc.s |
| || (sel.desc.u.seg.c && !sel.desc.u.seg.wr)) { | || (sel.desc.u.seg.c && !sel.desc.u.seg.wr)) { |
| EXCEPTION(exc, sel.idx); | EXCEPTION(exc, sel.idx); |
| Line 142 void | Line 149 void |
| load_cs(WORD selector, descriptor_t* sdp, BYTE cpl) | load_cs(WORD selector, descriptor_t* sdp, BYTE cpl) |
| { | { |
| CPU_STATSAVE.cpu_inst_default.op_32 | CPU_INST_OP32 = CPU_INST_AS32 = |
| = CPU_STATSAVE.cpu_inst_default.as_32 = sdp->d; | CPU_STATSAVE.cpu_inst_default.op_32 = |
| CPU_STATSAVE.cpu_inst_default.as_32 = sdp->d; | |
| CPU_REGS_SREG(CPU_CS_INDEX) = (selector & ~3) | (cpl & 3); | CPU_REGS_SREG(CPU_CS_INDEX) = (selector & ~3) | (cpl & 3); |
| CPU_STAT_SREG(CPU_CS_INDEX) = *sdp; | CPU_STAT_SREG(CPU_CS_INDEX) = *sdp; |
| CPU_STAT_CPL = cpl & 3; | CPU_STAT_CPL = cpl & 3; |
| Line 185 load_ldtr(WORD selector, int exc) | Line 193 load_ldtr(WORD selector, int exc) |
| EXCEPTION((exc == TS_EXCEPTION) ? TS_EXCEPTION : NP_EXCEPTION, sel.selector); | EXCEPTION((exc == TS_EXCEPTION) ? TS_EXCEPTION : NP_EXCEPTION, sel.selector); |
| } | } |
| #if defined(MORE_DEBUG) | |
| ldtr_dump(sel.desc.u.seg.segbase, sel.desc.u.seg.limit); | |
| #endif | |
| CPU_LDTR = sel.selector; | CPU_LDTR = sel.selector; |
| CPU_LDTR_DESC = sel.desc; | CPU_LDTR_DESC = sel.desc; |
| } | } |
| Line 193 void | Line 205 void |
| load_descriptor(descriptor_t *descp, DWORD addr) | load_descriptor(descriptor_t *descp, DWORD addr) |
| { | { |
| memset(descp, 0, sizeof(*descp)); | |
| descp->addr = addr; | descp->addr = addr; |
| descp->l = cpu_lmemoryread_d(descp->addr); | descp->l = cpu_lmemoryread_d(descp->addr); |
| descp->h = cpu_lmemoryread_d(descp->addr + 4); | descp->h = cpu_lmemoryread_d(descp->addr + 4); |
| VERBOSE(("load_descriptor: descriptor address = 0x%08x, h = 0x%08x, l = %08x", descp->addr, descp->h, descp->l)); | |
| descp->flag = 0; | descp->flag = 0; |
| Line 204 load_descriptor(descriptor_t *descp, DWO | Line 219 load_descriptor(descriptor_t *descp, DWO |
| descp->dpl = (descp->h & CPU_DESC_H_DPL) >> 13; | descp->dpl = (descp->h & CPU_DESC_H_DPL) >> 13; |
| descp->s = (descp->h & CPU_DESC_H_S) == CPU_DESC_H_S; | descp->s = (descp->h & CPU_DESC_H_S) == CPU_DESC_H_S; |
| VERBOSE(("load_descriptor: present = %s, type = %d, DPL = %d", descp->p ? "true" : "false", descp->type, descp->dpl)); | |
| if (descp->s) { | if (descp->s) { |
| /* code/data */ | /* code/data */ |
| descp->valid = 1; | descp->valid = 1; |
| descp->d = (descp->h & CPU_SEGDESC_H_D) ? 1 : 0; | descp->d = (descp->h & CPU_SEGDESC_H_D) ? 1 : 0; |
| descp->u.seg.c = (descp->h & CPU_SEGDESC_H_D_C) ? 1 : 0; | descp->u.seg.c = (descp->h & CPU_SEGDESC_H_D_C) ? 1 : 0; |
| descp->u.seg.g = (descp->h & CPU_SEGDESC_H_G) ? 1 : 0; | descp->u.seg.g = (descp->h & CPU_SEGDESC_H_G) ? 1 : 0; |
| descp->u.seg.wr = (descp->type & CPU_SEGDESC_TYPE_WR) ? 1 : 0; | descp->u.seg.wr = (descp->type & CPU_SEGDESC_TYPE_WR) ? 1 : 0; |
| Line 217 load_descriptor(descriptor_t *descp, DWO | Line 234 load_descriptor(descriptor_t *descp, DWO |
| descp->u.seg.segbase = (descp->l >> 16) & 0xffff; | descp->u.seg.segbase = (descp->l >> 16) & 0xffff; |
| descp->u.seg.segbase |= (descp->h & 0xff) << 16; | descp->u.seg.segbase |= (descp->h & 0xff) << 16; |
| descp->u.seg.segbase |= descp->h & 0xff000000; | descp->u.seg.segbase |= descp->h & 0xff000000; |
| descp->u.seg.limit = (descp->h & 0xf0000) | (descp->l & 0xffff); | descp->u.seg.limit = (descp->h & 0xf0000) | (descp->l & 0xffff); |
| if (descp->u.seg.g) { | if (descp->u.seg.g) { |
| descp->u.seg.limit <<= 12; | descp->u.seg.limit <<= 12; |
| descp->u.seg.limit |= 0xfff; | descp->u.seg.limit |= 0xfff; |
| } | } |
| descp->u.seg.segend = descp->u.seg.segbase + descp->u.seg.limit; | descp->u.seg.segend = descp->u.seg.segbase + descp->u.seg.limit; |
| VERBOSE(("load_descriptor: %s segment descriptor: addr = 0x%08x, h = 0x%04x, l = %04x, type = %d, DPL = %d, base = 0x%08x, limit = 0x%08x, d = %s, g = %s, %s, %s", descp->u.seg.c ? "code" : "data", descp->addr, descp->h, descp->l, descp->type, descp->dpl, descp->u.seg.segbase, descp->u.seg.limit, descp->d ? "on" : "off", descp->u.seg.g ? "on" : "off", descp->u.seg.c ? (descp->u.seg.wr ? "executable/readable" : "execute-only") : (descp->u.seg.wr ? "writable" : "read-only"), (descp->u.seg.c ? (descp->u.seg.ec ? "conforming" : "non-conforming") : (descp->u.seg.ec ? "expand-down" : "expand-up")))); | VERBOSE(("load_descriptor: %s segment descriptor", descp->u.seg.c ? "code" : "data")); |
| VERBOSE(("load_descriptor: segment base address = 0x%08x, segment limit = 0x%08x", descp->u.seg.segbase, descp->u.seg.limit)); | |
| VERBOSE(("load_descriptor: d = %s, g = %s", descp->d ? "on" : "off", descp->u.seg.g ? "on" : "off")); | |
| VERBOSE(("load_descriptor: %s, %s", descp->u.seg.c ? (descp->u.seg.wr ? "executable/readable" : "execute-only") : (descp->u.seg.wr ? "writable" : "read-only"), (descp->u.seg.c ? (descp->u.seg.ec ? "conforming" : "non-conforming") : (descp->u.seg.ec ? "expand-down" : "expand-up")))); | |
| } else { | } else { |
| /* system */ | /* system */ |
| switch (descp->type) { | switch (descp->type) { |
| case CPU_SYSDESC_TYPE_LDT: /* LDT */ | case CPU_SYSDESC_TYPE_LDT: /* LDT */ |
| descp->valid = 1; | descp->valid = 1; |
| descp->u.seg.g = (descp->h & CPU_SEGDESC_H_G) ? 1 : 0; | |
| descp->u.seg.segbase = descp->h & 0xff000000; | descp->u.seg.segbase = descp->h & 0xff000000; |
| descp->u.seg.segbase |= (descp->h & 0xff) << 16; | descp->u.seg.segbase |= (descp->h & 0xff) << 16; |
| descp->u.seg.segbase |= descp->l >> 16; | descp->u.seg.segbase |= descp->l >> 16; |
| descp->u.seg.limit = descp->h & 0xf0000; | descp->u.seg.limit = descp->h & 0xf0000; |
| descp->u.seg.limit |= descp->l & 0xffff; | descp->u.seg.limit |= descp->l & 0xffff; |
| if (descp->u.seg.g) { | |
| descp->u.seg.limit <<= 12; | |
| descp->u.seg.limit |= 0xfff; | |
| } | |
| descp->u.seg.segend = descp->u.seg.segbase + descp->u.seg.limit; | |
| VERBOSE(("load_descriptor: LDT descriptor")); | VERBOSE(("load_descriptor: LDT descriptor")); |
| VERBOSE(("load_descriptor: LDT base address = 0x%08x, limit size = 0x%08x", descp->u.seg.segbase, descp->u.seg.limit)); | |
| break; | break; |
| case CPU_SYSDESC_TYPE_TASK: | case CPU_SYSDESC_TYPE_TASK: /* task gate */ |
| descp->valid = 1; | descp->valid = 1; |
| descp->u.gate.selector = descp->l >> 16; | descp->u.gate.selector = descp->l >> 16; |
| VERBOSE(("load_descriptor: task descriptor: selector = 0x%04x", descp->u.gate.selector)); | VERBOSE(("load_descriptor: task descriptor: selector = 0x%04x", descp->u.gate.selector)); |
| break; | break; |
| case CPU_SYSDESC_TYPE_TSS_16: /* 286 TSS */ | case CPU_SYSDESC_TYPE_TSS_16: /* 286 TSS */ |
| case CPU_SYSDESC_TYPE_TSS_BUSY_16: /* 286 TSS Busy */ | case CPU_SYSDESC_TYPE_TSS_BUSY_16: /* 286 TSS Busy */ |
| descp->valid = 1; | |
| descp->u.seg.segbase |= (descp->h & 0xff) << 16; | |
| descp->u.seg.segbase |= descp->l >> 16; | |
| descp->u.seg.limit = descp->h & 0xf0000; | |
| descp->u.seg.limit |= descp->l & 0xffff; | |
| descp->u.seg.segend = descp->u.seg.segbase + descp->u.seg.limit; | |
| VERBOSE(("load_descriptor: 16bit %sTSS descriptor: base = 0x%08x, limit = 0x%08x", (descp->type & CPU_SYSDESC_TYPE_TSS_BUSY) ? "busy " : "", descp->u.seg.segbase, descp->u.seg.limit)); | |
| break; | |
| case CPU_SYSDESC_TYPE_CALL_16: /* 286 call gate */ | |
| case CPU_SYSDESC_TYPE_INTR_16: /* 286 interrupt gate */ | |
| case CPU_SYSDESC_TYPE_TRAP_16: /* 286 trap gate */ | |
| if ((descp->h & 0x0000000e0) == 0) { | |
| descp->valid = 1; | |
| descp->u.gate.selector = descp->l >> 16; | |
| descp->u.gate.offset = descp->l & 0xffff; | |
| descp->u.gate.count = descp->h & 0x1f; | |
| VERBOSE(("load_descriptor: 16bit %s gate descriptor: selector = 0x%04x, offset = 0x%08x, count = %d", (descp->type == CPU_SYSDESC_TYPE_CALL_16) ? "call" : ((descp->type == CPU_SYSDESC_TYPE_INTR_16) ? "interrupt" : "trap"), descp->u.gate.selector, descp->u.gate.offset, descp->u.gate.count)); | |
| } else { | |
| ia32_panic("load_descriptor: 286 gate is invalid"); | |
| } | |
| break; | |
| case CPU_SYSDESC_TYPE_TSS_32: /* 386 TSS */ | case CPU_SYSDESC_TYPE_TSS_32: /* 386 TSS */ |
| case CPU_SYSDESC_TYPE_TSS_BUSY_32: /* 386 TSS Busy */ | case CPU_SYSDESC_TYPE_TSS_BUSY_32: /* 386 TSS Busy */ |
| descp->valid = 1; | descp->valid = 1; |
| descp->d = (descp->h & CPU_SEGDESC_H_D) ? 1 : 0; | descp->d = (descp->h & CPU_GATEDESC_H_D) ? 1 : 0; |
| descp->u.seg.g = (descp->h & CPU_SEGDESC_H_G) ? 1 : 0; | descp->u.seg.g = (descp->h & CPU_SEGDESC_H_G) ? 1 : 0; |
| descp->u.seg.segbase = descp->h & 0xff000000; | descp->u.seg.segbase = descp->h & 0xff000000; |
| descp->u.seg.segbase |= (descp->h & 0xff) << 16; | descp->u.seg.segbase |= (descp->h & 0xff) << 16; |
| descp->u.seg.segbase |= descp->l >> 16; | descp->u.seg.segbase |= descp->l >> 16; |
| Line 285 load_descriptor(descriptor_t *descp, DWO | Line 291 load_descriptor(descriptor_t *descp, DWO |
| descp->u.seg.limit <<= 12; | descp->u.seg.limit <<= 12; |
| descp->u.seg.limit |= 0xfff; | descp->u.seg.limit |= 0xfff; |
| } | } |
| VERBOSE(("load_descriptor: 32bit %sTSS descriptor: base = 0x%08x, limit = 0x%08x, d = %s, g = %s", (descp->type & CPU_SYSDESC_TYPE_TSS_BUSY) ? "busy " : "", descp->u.seg.segbase, descp->u.seg.limit, descp->d ? "on" : "off", descp->u.seg.g ? "on" : "off")); | descp->u.seg.segend = descp->u.seg.segbase + descp->u.seg.limit; |
| VERBOSE(("load_descriptor: %dbit %sTSS descriptor", descp->d ? 32 : 16, (descp->type & CPU_SYSDESC_TYPE_TSS_BUSY) ? "busy " : "")); | |
| VERBOSE(("load_descriptor: TSS base address = 0x%08x, limit = 0x%08x", descp->u.seg.segbase, descp->u.seg.limit)); | |
| VERBOSE(("load_descriptor: d = %s, g = %s", descp->d ? "on" : "off", descp->u.seg.g ? "on" : "off")); | |
| break; | break; |
| case CPU_SYSDESC_TYPE_CALL_16: /* 286 call gate */ | |
| case CPU_SYSDESC_TYPE_INTR_16: /* 286 interrupt gate */ | |
| case CPU_SYSDESC_TYPE_TRAP_16: /* 286 trap gate */ | |
| case CPU_SYSDESC_TYPE_CALL_32: /* 386 call gate */ | case CPU_SYSDESC_TYPE_CALL_32: /* 386 call gate */ |
| case CPU_SYSDESC_TYPE_INTR_32: /* 386 interrupt gate */ | case CPU_SYSDESC_TYPE_INTR_32: /* 386 interrupt gate */ |
| case CPU_SYSDESC_TYPE_TRAP_32: /* 386 trap gate */ | case CPU_SYSDESC_TYPE_TRAP_32: /* 386 trap gate */ |
| Line 298 load_descriptor(descriptor_t *descp, DWO | Line 311 load_descriptor(descriptor_t *descp, DWO |
| descp->u.gate.offset = descp->h & 0xffff0000; | descp->u.gate.offset = descp->h & 0xffff0000; |
| descp->u.gate.offset |= descp->l & 0xffff; | descp->u.gate.offset |= descp->l & 0xffff; |
| descp->u.gate.count = descp->h & 0x1f; | descp->u.gate.count = descp->h & 0x1f; |
| VERBOSE(("load_descriptor: 32bit %s gate descriptor: selector = 0x%04x, offset = 0x%08x, count = %d, d = %s", (descp->type == CPU_SYSDESC_TYPE_CALL_16) ? "call" : ((descp->type == CPU_SYSDESC_TYPE_INTR_16) ? "interrupt" : "trap"), descp->u.gate.selector, descp->u.gate.offset, descp->u.gate.count, descp->d ? "on" : "off")); | |
| VERBOSE(("load_descriptor: %dbit %s gate descriptor", descp->d ? 32 : 16, ((descp->type & CPU_SYSDESC_TYPE_MASKBIT) == CPU_SYSDESC_TYPE_CALL) ? "call" : (((descp->type & CPU_SYSDESC_TYPE_MASKBIT) == CPU_SYSDESC_TYPE_INTR) ? "interrupt" : "trap"))); | |
| VERBOSE(("load_descriptor: selector = 0x%04x, offset = 0x%08x, count = %d, d = %s", descp->u.gate.selector, descp->u.gate.offset, descp->u.gate.count, descp->d ? "on" : "off")); | |
| } else { | } else { |
| ia32_panic("load_descriptor: 286 gate is invalid"); | ia32_panic("load_descriptor: 386 gate is invalid"); |
| } | } |
| break; | break; |
| case 0: case 8: case 10: case 13: /* reserved */ | case 0: case 8: case 10: case 13: /* reserved */ |
| default: | default: |
| descp->valid = 0; | descp->valid = 0; |
| ia32_panic("bad segment descriptor (%d)", descp->type); | ia32_panic("load_descriptor: bad descriptor (type = %d)", descp->type); |
| break; | break; |
| } | } |
| } | } |