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| version 1.11, 2004/02/09 16:12:54 | version 1.16, 2004/03/08 12:56:22 |
|---|---|
| Line 33 | Line 33 |
| void | void |
| load_tr(WORD selector) | load_tr(UINT16 selector) |
| { | { |
| selector_t task_sel; | selector_t task_sel; |
| int rv; | int rv; |
| int i; | |
| UINT16 iobase; | |
| rv = parse_selector(&task_sel, selector); | rv = parse_selector(&task_sel, selector); |
| if (rv < 0 || task_sel.ldt || task_sel.desc.s) { | if (rv < 0 || task_sel.ldt || task_sel.desc.s) { |
| Line 49 load_tr(WORD selector) | Line 51 load_tr(WORD selector) |
| if (task_sel.desc.u.seg.limit < 0x2b) { | if (task_sel.desc.u.seg.limit < 0x2b) { |
| EXCEPTION(TS_EXCEPTION, task_sel.idx); | EXCEPTION(TS_EXCEPTION, task_sel.idx); |
| } | } |
| iobase = 0; | |
| break; | break; |
| case CPU_SYSDESC_TYPE_TSS_32: | case CPU_SYSDESC_TYPE_TSS_32: |
| if (task_sel.desc.u.seg.limit < 0x67) { | if (task_sel.desc.u.seg.limit < 0x67) { |
| EXCEPTION(TS_EXCEPTION, task_sel.idx); | EXCEPTION(TS_EXCEPTION, task_sel.idx); |
| } | } |
| iobase = cpu_kmemoryread_w(task_sel.desc.u.seg.segbase + 102); | |
| break; | break; |
| default: | default: |
| EXCEPTION(GP_EXCEPTION, task_sel.idx); | EXCEPTION(GP_EXCEPTION, task_sel.idx); |
| iobase = 0; /* compiler happy */ | |
| break; | break; |
| } | } |
| Line 75 load_tr(WORD selector) | Line 80 load_tr(WORD selector) |
| CPU_SET_TASK_BUSY(task_sel.selector, &task_sel.desc); | CPU_SET_TASK_BUSY(task_sel.selector, &task_sel.desc); |
| CPU_TR = task_sel.selector; | CPU_TR = task_sel.selector; |
| CPU_TR_DESC = task_sel.desc; | CPU_TR_DESC = task_sel.desc; |
| /* I/O deny bitmap */ | |
| if (task_sel.desc.type == CPU_SYSDESC_TYPE_TSS_BUSY_32) { | |
| if (iobase != 0 && iobase < task_sel.desc.u.seg.limit) { | |
| CPU_STAT_IOLIMIT = (UINT16)(task_sel.desc.u.seg.limit - iobase); | |
| CPU_STAT_IOADDR = task_sel.desc.u.seg.segbase + iobase; | |
| } else { | |
| CPU_STAT_IOLIMIT = 0; | |
| } | |
| } else { | |
| CPU_STAT_IOLIMIT = 0; | |
| } | |
| /* clear local break point flags */ | |
| CPU_DR7 &= ~(CPU_DR7_L(0)|CPU_DR7_L(1)|CPU_DR7_L(2)|CPU_DR7_L(3)); | |
| CPU_STAT_BP = 0; | |
| for (i = 0; i < CPU_DEBUG_REG_INDEX_NUM; i++) { | |
| if (CPU_DR7 & CPU_DR7_G(i)) { | |
| CPU_STAT_BP |= (1 << i); | |
| } | |
| } | |
| } | } |
| void | void |
| get_stack_pointer_from_tss(DWORD pl, WORD *new_ss, DWORD *new_esp) | get_stack_pointer_from_tss(UINT pl, UINT16 *new_ss, UINT32 *new_esp) |
| { | { |
| DWORD tss_stack_addr; | UINT32 tss_stack_addr; |
| __ASSERT(pl < 3); | __ASSERT(pl < 3); |
| Line 107 get_stack_pointer_from_tss(DWORD pl, WOR | Line 133 get_stack_pointer_from_tss(DWORD pl, WOR |
| VERBOSE(("get_stack_pointer_from_tss: pl = %d, new_esp = 0x%08x, new_ss = 0x%04x", pl, *new_esp, *new_ss)); | VERBOSE(("get_stack_pointer_from_tss: pl = %d, new_esp = 0x%08x, new_ss = 0x%04x", pl, *new_esp, *new_ss)); |
| } | } |
| WORD | UINT16 |
| get_backlink_selector_from_tss(void) | get_backlink_selector_from_tss(void) |
| { | { |
| WORD backlink; | UINT16 backlink; |
| if (CPU_TR_DESC.type == CPU_SYSDESC_TYPE_TSS_BUSY_32) { | if (CPU_TR_DESC.type == CPU_SYSDESC_TYPE_TSS_BUSY_32) { |
| if (4 > CPU_TR_DESC.u.seg.limit) { | if (4 > CPU_TR_DESC.u.seg.limit) { |
| Line 132 get_backlink_selector_from_tss(void) | Line 158 get_backlink_selector_from_tss(void) |
| void | void |
| task_switch(selector_t *task_sel, task_switch_type_t type) | task_switch(selector_t *task_sel, task_switch_type_t type) |
| { | { |
| DWORD regs[CPU_REG_NUM]; | UINT32 regs[CPU_REG_NUM]; |
| DWORD eip; | UINT32 eip; |
| DWORD new_flags; | UINT32 new_flags; |
| DWORD mask; | UINT32 mask; |
| DWORD cr3 = 0; | UINT32 cr3 = 0; |
| WORD sreg[CPU_SEGREG_NUM]; | UINT16 sreg[CPU_SEGREG_NUM]; |
| WORD ldtr; | UINT16 ldtr; |
| WORD t, iobase; | UINT16 iobase; |
| #if defined(IA32_SUPPORT_DEBUG_REGISTER) | |
| UINT16 t; | |
| #endif | |
| selector_t cs_sel; | selector_t cs_sel; |
| int rv; | int rv; |
| DWORD cur_base; /* current task state */ | UINT32 cur_base; /* current task state */ |
| DWORD task_base; /* new task state */ | UINT32 task_base; /* new task state */ |
| DWORD old_flags = REAL_EFLAGREG; | UINT32 old_flags = REAL_EFLAGREG; |
| BOOL task16; | BOOL task16; |
| DWORD nsreg; | UINT nsreg; |
| DWORD i; | UINT i; |
| VERBOSE(("task_switch: start")); | VERBOSE(("task_switch: start")); |
| Line 188 task_switch(selector_t *task_sel, task_s | Line 217 task_switch(selector_t *task_sel, task_s |
| #if defined(MORE_DEBUG) | #if defined(MORE_DEBUG) |
| { | { |
| DWORD v; | UINT32 v; |
| VERBOSE(("task_switch: new task")); | VERBOSE(("task_switch: new task")); |
| for (i = 0; i < task_sel->desc.u.seg.limit; i += 4) { | for (i = 0; i < task_sel->desc.u.seg.limit; i += 4) { |
| Line 219 task_switch(selector_t *task_sel, task_s | Line 248 task_switch(selector_t *task_sel, task_s |
| sreg[i] = cpu_kmemoryread_w(task_base + 72 + i * 4); | sreg[i] = cpu_kmemoryread_w(task_base + 72 + i * 4); |
| } | } |
| ldtr = cpu_kmemoryread_w(task_base + 96); | ldtr = cpu_kmemoryread_w(task_base + 96); |
| #if defined(IA32_SUPPORT_DEBUG_REGISTER) | |
| t = cpu_kmemoryread_w(task_base + 100); | t = cpu_kmemoryread_w(task_base + 100); |
| t &= 1; | if (t & 1) { |
| CPU_STAT_BP_EVENT |= CPU_STAT_BP_EVENT_TASK; | |
| } | |
| #endif | |
| iobase = cpu_kmemoryread_w(task_base + 102); | iobase = cpu_kmemoryread_w(task_base + 102); |
| } else { | } else { |
| eip = cpu_kmemoryread_w(task_base + 14); | eip = cpu_kmemoryread_w(task_base + 14); |
| Line 232 task_switch(selector_t *task_sel, task_s | Line 265 task_switch(selector_t *task_sel, task_s |
| sreg[i] = cpu_kmemoryread_w(task_base + 34 + i * 2); | sreg[i] = cpu_kmemoryread_w(task_base + 34 + i * 2); |
| } | } |
| ldtr = cpu_kmemoryread_w(task_base + 42); | ldtr = cpu_kmemoryread_w(task_base + 42); |
| t = 0; | |
| iobase = 0; | iobase = 0; |
| } | } |
| Line 300 task_switch(selector_t *task_sel, task_s | Line 332 task_switch(selector_t *task_sel, task_s |
| } | } |
| } else { | } else { |
| cpu_kmemorywrite_w(cur_base + 14, CPU_IP); | cpu_kmemorywrite_w(cur_base + 14, CPU_IP); |
| cpu_kmemorywrite_w(cur_base + 16, (WORD)old_flags); | cpu_kmemorywrite_w(cur_base + 16, (UINT16)old_flags); |
| for (i = 0; i < CPU_REG_NUM; i++) { | for (i = 0; i < CPU_REG_NUM; i++) { |
| cpu_kmemorywrite_w(cur_base + 18 + i * 2, CPU_REGS_WORD(i)); | cpu_kmemorywrite_w(cur_base + 18 + i * 2, CPU_REGS_WORD(i)); |
| } | } |
| Line 311 task_switch(selector_t *task_sel, task_s | Line 343 task_switch(selector_t *task_sel, task_s |
| #if defined(MORE_DEBUG) | #if defined(MORE_DEBUG) |
| { | { |
| DWORD v; | UINT32 v; |
| VERBOSE(("task_switch: current task")); | VERBOSE(("task_switch: current task")); |
| for (i = 0; i < CPU_TR_DESC.u.seg.limit; i += 4) { | for (i = 0; i < CPU_TR_DESC.u.seg.limit; i += 4) { |
| Line 320 task_switch(selector_t *task_sel, task_s | Line 352 task_switch(selector_t *task_sel, task_s |
| } | } |
| } | } |
| #endif | #endif |
| /* set back link selector */ | /* set back link selector */ |
| switch (type) { | switch (type) { |
| case TASK_SWITCH_CALL: | case TASK_SWITCH_CALL: |
| Line 355 task_switch(selector_t *task_sel, task_s | Line 388 task_switch(selector_t *task_sel, task_s |
| case TASK_SWITCH_IRET: | case TASK_SWITCH_IRET: |
| /* check busy flag is active */ | /* check busy flag is active */ |
| if (task_sel->desc.valid) { | if (task_sel->desc.valid) { |
| DWORD h; | UINT32 h; |
| h = cpu_kmemoryread_d(task_sel->addr + 4); | h = cpu_kmemoryread_d(task_sel->addr + 4); |
| if ((h & CPU_TSS_H_BUSY) == 0) { | if ((h & CPU_TSS_H_BUSY) == 0) { |
| ia32_panic("task_switch: new task is not busy"); | ia32_panic("task_switch: new task is not busy"); |
| Line 384 task_switch(selector_t *task_sel, task_s | Line 417 task_switch(selector_t *task_sel, task_s |
| /* set new EIP, GPR */ | /* set new EIP, GPR */ |
| CPU_PREV_EIP = CPU_EIP = eip; | CPU_PREV_EIP = CPU_EIP = eip; |
| CPU_PREFETCH_CLEAR(); | |
| for (i = 0; i < CPU_REG_NUM; i++) { | for (i = 0; i < CPU_REG_NUM; i++) { |
| CPU_REGS_DWORD(i) = regs[i]; | CPU_REGS_DWORD(i) = regs[i]; |
| } | } |
| Line 396 task_switch(selector_t *task_sel, task_s | Line 430 task_switch(selector_t *task_sel, task_s |
| mask = I_FLAG|IOPL_FLAG|RF_FLAG|VM_FLAG|VIF_FLAG|VIP_FLAG; | mask = I_FLAG|IOPL_FLAG|RF_FLAG|VM_FLAG|VIF_FLAG|VIP_FLAG; |
| set_eflags(new_flags, mask); | set_eflags(new_flags, mask); |
| /* I/O deny bitmap */ | |
| if (!task16) { | |
| if (iobase != 0 && iobase < task_sel->desc.u.seg.limit) { | |
| CPU_STAT_IOLIMIT = (UINT16)(task_sel->desc.u.seg.limit - iobase); | |
| CPU_STAT_IOADDR = task_sel->desc.u.seg.segbase + iobase; | |
| } else { | |
| CPU_STAT_IOLIMIT = 0; | |
| } | |
| } else { | |
| CPU_STAT_IOLIMIT = 0; | |
| } | |
| VERBOSE(("task_switch: ioaddr = %08x, limit = %08x", CPU_STAT_IOADDR, CPU_STAT_IOLIMIT)); | |
| #if defined(IA32_SUPPORT_DEBUG_REGISTER) | |
| /* check resume flag */ | |
| if (CPU_EFLAG & RF_FLAG) { | |
| CPU_STAT_BP_EVENT |= CPU_STAT_BP_EVENT_RF; | |
| } | |
| /* clear local break point flags */ | |
| CPU_DR7 &= ~(CPU_DR7_L(0)|CPU_DR7_L(1)|CPU_DR7_L(2)|CPU_DR7_L(3)); | |
| CPU_STAT_BP = 0; | |
| for (i = 0; i < CPU_DEBUG_REG_INDEX_NUM; i++) { | |
| if (CPU_DR7 & CPU_DR7_G(i)) { | |
| CPU_STAT_BP |= (1 << i); | |
| } | |
| } | |
| #endif | |
| /* load new LDTR */ | /* load new LDTR */ |
| load_ldtr(ldtr, TS_EXCEPTION); | load_ldtr(ldtr, TS_EXCEPTION); |
| Line 448 task_switch(selector_t *task_sel, task_s | Line 511 task_switch(selector_t *task_sel, task_s |
| } | } |
| } | } |
| /* I/O deny bitmap */ | |
| if (!task16) { | |
| if (task_sel->desc.u.seg.limit > iobase) { | |
| CPU_STAT_IOLIMIT = task_sel->desc.u.seg.limit - iobase; | |
| CPU_STAT_IOADDR = task_sel->desc.u.seg.segbase + iobase; | |
| } else { | |
| CPU_STAT_IOLIMIT = 0; | |
| } | |
| } else { | |
| CPU_STAT_IOLIMIT = 0; | |
| } | |
| VERBOSE(("task_switch: ioaddr = %08x, limit = %08x", CPU_STAT_IOADDR, CPU_STAT_IOLIMIT)); | |
| /* out of range */ | /* out of range */ |
| if (CPU_EIP > CPU_STAT_CS_LIMIT) { | if (CPU_EIP > CPU_STAT_CS_LIMIT) { |
| VERBOSE(("task_switch: new_ip is out of range. new_ip = %08x, limit = %08x", CPU_EIP, CPU_STAT_CS_LIMIT)); | VERBOSE(("task_switch: new_ip is out of range. new_ip = %08x, limit = %08x", CPU_EIP, CPU_STAT_CS_LIMIT)); |