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| version 1.17, 2004/03/12 13:34:08 | version 1.21, 2008/01/25 17:49:46 |
|---|---|
| Line 12 | Line 12 |
| * 2. Redistributions in binary form must reproduce the above copyright | * 2. Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the | * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. | * documentation and/or other materials provided with the distribution. |
| * 3. The name of the author may not be used to endorse or promote products | |
| * derived from this software without specific prior written permission. | |
| * | * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| Line 37 load_tr(UINT16 selector) | Line 35 load_tr(UINT16 selector) |
| { | { |
| selector_t task_sel; | selector_t task_sel; |
| int rv; | int rv; |
| #if defined(IA32_SUPPORT_DEBUG_REGISTER) | |
| int i; | int i; |
| #endif | |
| UINT16 iobase; | UINT16 iobase; |
| rv = parse_selector(&task_sel, selector); | rv = parse_selector(&task_sel, selector); |
| Line 63 load_tr(UINT16 selector) | Line 63 load_tr(UINT16 selector) |
| default: | default: |
| EXCEPTION(GP_EXCEPTION, task_sel.idx); | EXCEPTION(GP_EXCEPTION, task_sel.idx); |
| iobase = 0; /* compiler happy */ | return; |
| break; | |
| } | } |
| /* not present */ | /* not present */ |
| Line 93 load_tr(UINT16 selector) | Line 92 load_tr(UINT16 selector) |
| CPU_STAT_IOLIMIT = 0; | CPU_STAT_IOLIMIT = 0; |
| } | } |
| #if defined(IA32_SUPPORT_DEBUG_REGISTER) | |
| /* clear local break point flags */ | /* clear local break point flags */ |
| CPU_DR7 &= ~(CPU_DR7_L(0)|CPU_DR7_L(1)|CPU_DR7_L(2)|CPU_DR7_L(3)); | CPU_DR7 &= ~(CPU_DR7_L(0)|CPU_DR7_L(1)|CPU_DR7_L(2)|CPU_DR7_L(3)|CPU_DR7_LE); |
| CPU_STAT_BP = 0; | CPU_STAT_BP = 0; |
| for (i = 0; i < CPU_DEBUG_REG_INDEX_NUM; i++) { | for (i = 0; i < CPU_DEBUG_REG_INDEX_NUM; i++) { |
| if (CPU_DR7 & CPU_DR7_G(i)) { | if (CPU_DR7 & CPU_DR7_G(i)) { |
| CPU_STAT_BP |= (1 << i); | CPU_STAT_BP |= (1 << i); |
| } | } |
| } | } |
| #endif | |
| } | } |
| void | void |
| Line 222 task_switch(selector_t *task_sel, task_s | Line 223 task_switch(selector_t *task_sel, task_s |
| if (CPU_STAT_PAGING) { | if (CPU_STAT_PAGING) { |
| /* task state paging check */ | /* task state paging check */ |
| paging_check(cur_base, CPU_TR_DESC.u.seg.limit, CPU_PAGE_WRITE_DATA, CPU_MODE_SUPERVISER); | paging_check(cur_base, CPU_TR_DESC.u.seg.limit, CPU_PAGE_WRITE_DATA|CPU_MODE_SUPERVISER); |
| paging_check(task_base, task_sel->desc.u.seg.limit, CPU_PAGE_WRITE_DATA, CPU_MODE_SUPERVISER); | paging_check(task_base, task_sel->desc.u.seg.limit, CPU_PAGE_WRITE_DATA|CPU_MODE_SUPERVISER); |
| } | } |
| /* load task state */ | /* load task state */ |
| Line 423 task_switch(selector_t *task_sel, task_s | Line 424 task_switch(selector_t *task_sel, task_s |
| } | } |
| /* set new EFLAGS */ | /* set new EFLAGS */ |
| #if defined(IA32_DONT_USE_SET_EFLAGS_FUNCTION) | |
| CPU_EFLAG = new_flags; | |
| CPU_OV = CPU_FLAG & O_FLAG; | |
| CPU_TRAP = (CPU_FLAG & (I_FLAG|T_FLAG)) == (I_FLAG|T_FLAG); | |
| if ((old_flags ^ CPU_EFLAG) & VM_FLAG) { | |
| if (CPU_EFLAG & VM_FLAG) { | |
| change_vm(1); | |
| } else { | |
| change_vm(0); | |
| } | |
| } | |
| #else | |
| set_eflags(new_flags, I_FLAG|IOPL_FLAG|RF_FLAG|VM_FLAG|VIF_FLAG|VIP_FLAG); | set_eflags(new_flags, I_FLAG|IOPL_FLAG|RF_FLAG|VM_FLAG|VIF_FLAG|VIP_FLAG); |
| #endif | |
| /* I/O deny bitmap */ | /* I/O deny bitmap */ |
| if (!task16) { | if (!task16) { |
| Line 458 task_switch(selector_t *task_sel, task_s | Line 446 task_switch(selector_t *task_sel, task_s |
| } | } |
| /* clear local break point flags */ | /* clear local break point flags */ |
| CPU_DR7 &= ~(CPU_DR7_L(0)|CPU_DR7_L(1)|CPU_DR7_L(2)|CPU_DR7_L(3)); | CPU_DR7 &= ~(CPU_DR7_L(0)|CPU_DR7_L(1)|CPU_DR7_L(2)|CPU_DR7_L(3)|CPU_DR7_LE); |
| CPU_STAT_BP = 0; | CPU_STAT_BP = 0; |
| for (i = 0; i < CPU_DEBUG_REG_INDEX_NUM; i++) { | for (i = 0; i < CPU_DEBUG_REG_INDEX_NUM; i++) { |
| if (CPU_DR7 & CPU_DR7_G(i)) { | if (CPU_DR7 & CPU_DR7_G(i)) { |