|
|
| version 1.24, 2011/01/15 17:17:23 | version 1.28, 2011/12/20 09:55:07 |
|---|---|
| Line 27 | Line 27 |
| #include "cpu.h" | #include "cpu.h" |
| #include "ia32.mcr" | #include "ia32.mcr" |
| #define TSS_SIZE_16 44 | #define TSS_16_SIZE 44 |
| #define TSS_SIZE_32 108 | #define TSS_16_LIMIT (TSS_16_SIZE - 1) |
| #define TSS_32_SIZE 104 | |
| #define TSS_32_LIMIT (TSS_32_SIZE - 1) | |
| static void | static void |
| set_task_busy(UINT16 selector, descriptor_t *sdp) | set_task_busy(UINT16 selector) |
| { | { |
| UINT32 addr; | UINT32 addr; |
| UINT32 h; | UINT32 h; |
| Line 39 set_task_busy(UINT16 selector, descripto | Line 41 set_task_busy(UINT16 selector, descripto |
| addr = CPU_GDTR_BASE + (selector & CPU_SEGMENT_SELECTOR_INDEX_MASK); | addr = CPU_GDTR_BASE + (selector & CPU_SEGMENT_SELECTOR_INDEX_MASK); |
| h = cpu_kmemoryread_d(addr + 4); | h = cpu_kmemoryread_d(addr + 4); |
| if (!(h & CPU_TSS_H_BUSY)) { | if (!(h & CPU_TSS_H_BUSY)) { |
| sdp->type |= CPU_SYSDESC_TYPE_TSS_BUSY_IND; | |
| h |= CPU_TSS_H_BUSY; | h |= CPU_TSS_H_BUSY; |
| cpu_kmemorywrite_d(addr + 4, h); | cpu_kmemorywrite_d(addr + 4, h); |
| } else { | } else { |
| Line 48 set_task_busy(UINT16 selector, descripto | Line 49 set_task_busy(UINT16 selector, descripto |
| } | } |
| static void | static void |
| set_task_free(UINT16 selector, descriptor_t *sdp) | set_task_free(UINT16 selector) |
| { | { |
| UINT32 addr; | UINT32 addr; |
| UINT32 h; | UINT32 h; |
| Line 56 set_task_free(UINT16 selector, descripto | Line 57 set_task_free(UINT16 selector, descripto |
| addr = CPU_GDTR_BASE + (selector & CPU_SEGMENT_SELECTOR_INDEX_MASK); | addr = CPU_GDTR_BASE + (selector & CPU_SEGMENT_SELECTOR_INDEX_MASK); |
| h = cpu_kmemoryread_d(addr + 4); | h = cpu_kmemoryread_d(addr + 4); |
| if (h & CPU_TSS_H_BUSY) { | if (h & CPU_TSS_H_BUSY) { |
| sdp->type &= ~CPU_SYSDESC_TYPE_TSS_BUSY_IND; | |
| h &= ~CPU_TSS_H_BUSY; | h &= ~CPU_TSS_H_BUSY; |
| cpu_kmemorywrite_d(addr + 4, h); | cpu_kmemorywrite_d(addr + 4, h); |
| } else { | } else { |
| Line 82 load_tr(UINT16 selector) | Line 82 load_tr(UINT16 selector) |
| /* check descriptor type & stack room size */ | /* check descriptor type & stack room size */ |
| switch (task_sel.desc.type) { | switch (task_sel.desc.type) { |
| case CPU_SYSDESC_TYPE_TSS_16: | case CPU_SYSDESC_TYPE_TSS_16: |
| if (task_sel.desc.u.seg.limit < TSS_SIZE_16) { | if (task_sel.desc.u.seg.limit < TSS_16_LIMIT) { |
| EXCEPTION(TS_EXCEPTION, task_sel.idx); | EXCEPTION(TS_EXCEPTION, task_sel.idx); |
| } | } |
| iobase = 0; | iobase = 0; |
| break; | break; |
| case CPU_SYSDESC_TYPE_TSS_32: | case CPU_SYSDESC_TYPE_TSS_32: |
| if (task_sel.desc.u.seg.limit < TSS_SIZE_32) { | if (task_sel.desc.u.seg.limit < TSS_32_LIMIT) { |
| EXCEPTION(TS_EXCEPTION, task_sel.idx); | EXCEPTION(TS_EXCEPTION, task_sel.idx); |
| } | } |
| iobase = cpu_kmemoryread_w(task_sel.desc.u.seg.segbase + 102); | iobase = cpu_kmemoryread_w(task_sel.desc.u.seg.segbase + 102); |
| Line 110 load_tr(UINT16 selector) | Line 110 load_tr(UINT16 selector) |
| tr_dump(task_sel.selector, task_sel.desc.u.seg.segbase, task_sel.desc.u.seg.limit); | tr_dump(task_sel.selector, task_sel.desc.u.seg.segbase, task_sel.desc.u.seg.limit); |
| #endif | #endif |
| set_task_busy(task_sel.selector, &task_sel.desc); | set_task_busy(task_sel.selector); |
| CPU_TR = task_sel.selector; | CPU_TR = task_sel.selector; |
| CPU_TR_DESC = task_sel.desc; | CPU_TR_DESC = task_sel.desc; |
| CPU_TR_DESC.type |= CPU_SYSDESC_TYPE_TSS_BUSY_IND; | |
| /* I/O deny bitmap */ | /* I/O deny bitmap */ |
| CPU_STAT_IOLIMIT = 0; | CPU_STAT_IOLIMIT = 0; |
| if (task_sel.desc.type == CPU_SYSDESC_TYPE_TSS_BUSY_32) { | if (CPU_TR_DESC.type == CPU_SYSDESC_TYPE_TSS_BUSY_32) { |
| if (iobase != 0 && iobase < task_sel.desc.u.seg.limit) { | if (iobase != 0 && iobase < CPU_TR_DESC.u.seg.limit) { |
| CPU_STAT_IOLIMIT = (UINT16)(task_sel.desc.u.seg.limit - iobase); | CPU_STAT_IOLIMIT = (UINT16)(CPU_TR_DESC.u.seg.limit - iobase); |
| CPU_STAT_IOADDR = task_sel.desc.u.seg.segbase + iobase; | CPU_STAT_IOADDR = CPU_TR_DESC.u.seg.segbase + iobase; |
| } | } |
| } | } |
| Line 200 task_switch(selector_t *task_sel, task_s | Line 201 task_switch(selector_t *task_sel, task_s |
| UINT16 ldtr; | UINT16 ldtr; |
| UINT16 iobase; | UINT16 iobase; |
| UINT16 t; | UINT16 t; |
| int new_cpl; | |
| selector_t cs_sel, ss_sel; | selector_t sreg_sel[CPU_SEGREG_NUM]; |
| selector_t ldtr_sel; | |
| int rv; | int rv; |
| UINT32 cur_base, cur_paddr; /* current task state */ | UINT32 cur_base, cur_paddr; /* current task state */ |
| Line 215 task_switch(selector_t *task_sel, task_s | Line 218 task_switch(selector_t *task_sel, task_s |
| switch (task_sel->desc.type) { | switch (task_sel->desc.type) { |
| case CPU_SYSDESC_TYPE_TSS_32: | case CPU_SYSDESC_TYPE_TSS_32: |
| case CPU_SYSDESC_TYPE_TSS_BUSY_32: | case CPU_SYSDESC_TYPE_TSS_BUSY_32: |
| if (task_sel->desc.u.seg.limit < TSS_SIZE_32) { | if (task_sel->desc.u.seg.limit < TSS_32_LIMIT) { |
| EXCEPTION(TS_EXCEPTION, task_sel->idx); | EXCEPTION(TS_EXCEPTION, task_sel->idx); |
| } | } |
| task16 = 0; | task16 = 0; |
| Line 223 task_switch(selector_t *task_sel, task_s | Line 226 task_switch(selector_t *task_sel, task_s |
| case CPU_SYSDESC_TYPE_TSS_16: | case CPU_SYSDESC_TYPE_TSS_16: |
| case CPU_SYSDESC_TYPE_TSS_BUSY_16: | case CPU_SYSDESC_TYPE_TSS_BUSY_16: |
| if (task_sel->desc.u.seg.limit < TSS_SIZE_16) { | if (task_sel->desc.u.seg.limit < TSS_16_LIMIT) { |
| EXCEPTION(TS_EXCEPTION, task_sel->idx); | EXCEPTION(TS_EXCEPTION, task_sel->idx); |
| } | } |
| task16 = 1; | task16 = 1; |
| Line 332 task_switch(selector_t *task_sel, task_s | Line 335 task_switch(selector_t *task_sel, task_s |
| /*FALLTHROUGH*/ | /*FALLTHROUGH*/ |
| case TASK_SWITCH_JMP: | case TASK_SWITCH_JMP: |
| /* clear busy flags in current task */ | /* clear busy flags in current task */ |
| set_task_free(CPU_TR, &CPU_TR_DESC); | set_task_free(CPU_TR); |
| break; | break; |
| case TASK_SWITCH_CALL: | case TASK_SWITCH_CALL: |
| Line 407 task_switch(selector_t *task_sel, task_s | Line 410 task_switch(selector_t *task_sel, task_s |
| new_flags |= NT_FLAG; | new_flags |= NT_FLAG; |
| /*FALLTHROUGH*/ | /*FALLTHROUGH*/ |
| case TASK_SWITCH_JMP: | case TASK_SWITCH_JMP: |
| set_task_busy(task_sel->selector, &task_sel->desc); | set_task_busy(task_sel->selector); |
| break; | break; |
| case TASK_SWITCH_IRET: | case TASK_SWITCH_IRET: |
| /* check busy flag is active */ | /* check busy flag is active */ |
| if (SEG_IS_VALID(&task_sel->desc)) { | if (SEG_IS_VALID(&task_sel->desc)) { |
| Line 429 task_switch(selector_t *task_sel, task_s | Line 432 task_switch(selector_t *task_sel, task_s |
| /* load task selector to CPU_TR */ | /* load task selector to CPU_TR */ |
| CPU_TR = task_sel->selector; | CPU_TR = task_sel->selector; |
| CPU_TR_DESC = task_sel->desc; | CPU_TR_DESC = task_sel->desc; |
| CPU_TR_DESC.type |= CPU_SYSDESC_TYPE_TSS_BUSY_IND; | |
| /* clear BUSY flag in descriptor cache */ | |
| CPU_TR_DESC.type &= ~CPU_SYSDESC_TYPE_TSS_BUSY_IND; | |
| /* set CR0 image CPU_CR0_TS */ | /* set CR0 image CPU_CR0_TS */ |
| CPU_CR0 |= CPU_CR0_TS; | CPU_CR0 |= CPU_CR0_TS; |
| /* | /* |
| * load task state (CR3, EFLAG, EIP, GPR, segreg, LDTR) | * load task state (EIP, GPR, EFLAG, segreg, CR3, LDTR) |
| */ | */ |
| /* set new CR3 */ | |
| if (!task16 && CPU_STAT_PAGING) { | |
| set_cr3(cr3); | |
| } | |
| /* set new EIP, GPR */ | /* set new EIP, GPR */ |
| CPU_EIP = eip; | CPU_EIP = eip; |
| for (i = 0; i < CPU_REG_NUM; i++) { | for (i = 0; i < CPU_REG_NUM; i++) { |
| CPU_REGS_DWORD(i) = regs[i]; | CPU_REGS_DWORD(i) = regs[i]; |
| } | } |
| CPU_CLEAR_PREV_ESP(); | |
| /* set new EFLAGS */ | |
| set_eflags(new_flags, I_FLAG|IOPL_FLAG|RF_FLAG|VM_FLAG|VIF_FLAG|VIP_FLAG); | |
| /* check new segregs, ldtr */ | |
| for (i = 0; i < CPU_SEGREG_NUM; i++) { | for (i = 0; i < CPU_SEGREG_NUM; i++) { |
| segdesc_init(i, sreg[i], &CPU_STAT_SREG(i)); | rv = parse_selector(&sreg_sel[i], sreg[i]); |
| if (rv < 0) { | |
| VERBOSE(("task_switch: selector parse failure: index=%d (sel = 0x%04x, rv = %d)", i, sreg[i], rv)); | |
| EXCEPTION(TS_EXCEPTION, sreg_sel[i].idx); | |
| } | |
| } | |
| rv = parse_selector(&ldtr_sel, ldtr); | |
| if (rv < 0) { | |
| VERBOSE(("task_switch: LDTR selector parse failure (sel = 0x%04x, rv = %d)", ldtr, rv)); | |
| EXCEPTION(TS_EXCEPTION, ldtr_sel.idx); | |
| } | |
| /* invalidate segreg, ldtr descriptor */ | |
| for (i = 0; i < CPU_SEGREG_NUM; i++) { | |
| CPU_STAT_SREG(i).valid = 0; | |
| } | |
| CPU_LDTR_DESC.valid = 0; | |
| /* set new CR3 */ | |
| if (!task16 && CPU_STAT_PAGING) { | |
| set_cr3(cr3); | |
| } | } |
| /* load new LDTR */ | /* load new LDTR */ |
| Line 459 task_switch(selector_t *task_sel, task_s | Line 482 task_switch(selector_t *task_sel, task_s |
| /* I/O deny bitmap */ | /* I/O deny bitmap */ |
| CPU_STAT_IOLIMIT = 0; | CPU_STAT_IOLIMIT = 0; |
| if (!task16 && iobase != 0 && iobase < task_sel->desc.u.seg.limit) { | if (!task16 && iobase != 0 && iobase < CPU_TR_DESC.u.seg.limit) { |
| CPU_STAT_IOLIMIT = (UINT16)(task_sel->desc.u.seg.limit - iobase); | CPU_STAT_IOLIMIT = (UINT16)(CPU_TR_DESC.u.seg.limit - iobase); |
| CPU_STAT_IOADDR = task_base + iobase; | CPU_STAT_IOADDR = task_base + iobase; |
| } | } |
| VERBOSE(("task_switch: ioaddr = %08x, limit = %08x", CPU_STAT_IOADDR, CPU_STAT_IOLIMIT)); | VERBOSE(("task_switch: ioaddr = %08x, limit = %08x", CPU_STAT_IOADDR, CPU_STAT_IOLIMIT)); |
| Line 481 task_switch(selector_t *task_sel, task_s | Line 504 task_switch(selector_t *task_sel, task_s |
| } | } |
| #endif | #endif |
| /* set new EFLAGS */ | |
| set_eflags(new_flags, I_FLAG|IOPL_FLAG|RF_FLAG|VM_FLAG|VIF_FLAG|VIP_FLAG); | |
| /* set new segment register */ | /* set new segment register */ |
| if (!CPU_STAT_VM86) { | new_cpl = sreg_sel[CPU_CS_INDEX].rpl; |
| /* clear segment descriptor cache */ | if (CPU_STAT_VM86) { |
| for (i = 0; i < CPU_SEGREG_NUM; i++) { | load_ss(sreg_sel[CPU_SS_INDEX].selector, |
| segdesc_clear(&CPU_STAT_SREG(i)); | &sreg_sel[CPU_SS_INDEX].desc, new_cpl); |
| LOAD_SEGREG1(CPU_ES_INDEX, sreg_sel[CPU_ES_INDEX].selector, | |
| TS_EXCEPTION); | |
| LOAD_SEGREG1(CPU_DS_INDEX, sreg_sel[CPU_DS_INDEX].selector, | |
| TS_EXCEPTION); | |
| LOAD_SEGREG1(CPU_FS_INDEX, sreg_sel[CPU_FS_INDEX].selector, | |
| TS_EXCEPTION); | |
| LOAD_SEGREG1(CPU_GS_INDEX, sreg_sel[CPU_GS_INDEX].selector, | |
| TS_EXCEPTION); | |
| load_cs(sreg_sel[CPU_CS_INDEX].selector, | |
| &sreg_sel[CPU_CS_INDEX].desc, new_cpl); | |
| } else { | |
| /* load SS */ | |
| /* SS must be writable data segment */ | |
| if (SEG_IS_SYSTEM(&sreg_sel[CPU_SS_INDEX].desc) | |
| || SEG_IS_CODE(&sreg_sel[CPU_SS_INDEX].desc) | |
| || !SEG_IS_WRITABLE_DATA(&sreg_sel[CPU_SS_INDEX].desc)) { | |
| EXCEPTION(TS_EXCEPTION, sreg_sel[CPU_SS_INDEX].idx); | |
| } | } |
| /* load CS */ | /* check privilege level */ |
| rv = parse_selector(&cs_sel, sreg[CPU_CS_INDEX]); | if ((sreg_sel[CPU_SS_INDEX].desc.dpl != new_cpl) |
| || (sreg_sel[CPU_SS_INDEX].desc.dpl != new_cpl)) { | |
| EXCEPTION(TS_EXCEPTION, sreg_sel[CPU_SS_INDEX].idx); | |
| } | |
| /* stack segment is not present */ | |
| rv = selector_is_not_present(&sreg_sel[CPU_SS_INDEX]); | |
| if (rv < 0) { | if (rv < 0) { |
| VERBOSE(("task_switch: load CS failure (sel = 0x%04x, rv = %d)", sreg[CPU_CS_INDEX], rv)); | EXCEPTION(SS_EXCEPTION, sreg_sel[CPU_SS_INDEX].idx); |
| EXCEPTION(TS_EXCEPTION, cs_sel.idx); | |
| } | } |
| /* Now loading SS register */ | |
| load_ss(sreg_sel[CPU_SS_INDEX].selector, | |
| &sreg_sel[CPU_SS_INDEX].desc, new_cpl); | |
| /* load ES, DS, FS, GS segment register */ | |
| LOAD_SEGREG1(CPU_ES_INDEX, sreg_sel[CPU_ES_INDEX].selector, | |
| TS_EXCEPTION); | |
| LOAD_SEGREG1(CPU_DS_INDEX, sreg_sel[CPU_DS_INDEX].selector, | |
| TS_EXCEPTION); | |
| LOAD_SEGREG1(CPU_FS_INDEX, sreg_sel[CPU_FS_INDEX].selector, | |
| TS_EXCEPTION); | |
| LOAD_SEGREG1(CPU_GS_INDEX, sreg_sel[CPU_GS_INDEX].selector, | |
| TS_EXCEPTION); | |
| /* load CS */ | |
| /* CS must be code segment */ | /* CS must be code segment */ |
| if (SEG_IS_SYSTEM(&cs_sel.desc) || SEG_IS_DATA(&cs_sel.desc)) { | if (SEG_IS_SYSTEM(&sreg_sel[CPU_CS_INDEX].desc) |
| EXCEPTION(TS_EXCEPTION, cs_sel.idx); | || SEG_IS_DATA(&sreg_sel[CPU_CS_INDEX].desc)) { |
| EXCEPTION(TS_EXCEPTION, sreg_sel[CPU_CS_INDEX].idx); | |
| } | } |
| /* check privilege level */ | /* check privilege level */ |
| if (!SEG_IS_CONFORMING_CODE(&cs_sel.desc)) { | if (!SEG_IS_CONFORMING_CODE(&sreg_sel[CPU_CS_INDEX].desc)) { |
| /* non-confirming code segment */ | /* non-confirming code segment */ |
| if (cs_sel.desc.dpl != cs_sel.rpl) { | if (sreg_sel[CPU_CS_INDEX].desc.dpl != new_cpl) { |
| EXCEPTION(TS_EXCEPTION, cs_sel.idx); | EXCEPTION(TS_EXCEPTION, sreg_sel[CPU_CS_INDEX].idx); |
| } | } |
| } else { | } else { |
| /* conforming code segment */ | /* conforming code segment */ |
| if (cs_sel.desc.dpl > cs_sel.rpl) { | if (sreg_sel[CPU_CS_INDEX].desc.dpl > new_cpl) { |
| EXCEPTION(TS_EXCEPTION, cs_sel.idx); | EXCEPTION(TS_EXCEPTION, sreg_sel[CPU_CS_INDEX].idx); |
| } | } |
| } | } |
| /* code segment is not present */ | /* code segment is not present */ |
| rv = selector_is_not_present(&cs_sel); | rv = selector_is_not_present(&sreg_sel[CPU_CS_INDEX]); |
| if (rv < 0) { | |
| EXCEPTION(NP_EXCEPTION, cs_sel.idx); | |
| } | |
| /* load SS */ | |
| rv = parse_selector(&ss_sel, sreg[CPU_SS_INDEX]); | |
| if (rv < 0) { | |
| VERBOSE(("task_switch: load SS failure (sel = 0x%04x, rv = %d)", sreg[CPU_SS_INDEX], rv)); | |
| EXCEPTION(TS_EXCEPTION, ss_sel.idx); | |
| } | |
| /* SS must be writable data segment */ | |
| if (SEG_IS_SYSTEM(&ss_sel.desc) | |
| || SEG_IS_CODE(&ss_sel.desc) | |
| || !SEG_IS_WRITABLE_DATA(&ss_sel.desc)) { | |
| EXCEPTION(TS_EXCEPTION, ss_sel.idx); | |
| } | |
| /* check privilege level */ | |
| if ((ss_sel.desc.dpl != cs_sel.rpl) | |
| || (ss_sel.desc.dpl != ss_sel.rpl)) { | |
| EXCEPTION(TS_EXCEPTION, ss_sel.idx); | |
| } | |
| /* stack segment is not present */ | |
| rv = selector_is_not_present(&ss_sel); | |
| if (rv < 0) { | if (rv < 0) { |
| EXCEPTION(SS_EXCEPTION, ss_sel.idx); | EXCEPTION(NP_EXCEPTION, sreg_sel[CPU_CS_INDEX].idx); |
| } | |
| /* Now loading CS/SS register */ | |
| load_cs(cs_sel.selector, &cs_sel.desc, cs_sel.rpl); | |
| load_ss(ss_sel.selector, &ss_sel.desc, cs_sel.rpl); | |
| /* load ES, DS, FS, GS segment register */ | |
| for (i = 0; i < CPU_SEGREG_NUM; i++) { | |
| if (i != CPU_CS_INDEX || i != CPU_SS_INDEX) { | |
| LOAD_SEGREG1(i, sreg[i], TS_EXCEPTION); | |
| } | |
| } | } |
| } | |
| /* out of range */ | /* Now loading CS register */ |
| if (CPU_EIP > CPU_STAT_CS_LIMIT) { | load_cs(sreg_sel[CPU_CS_INDEX].selector, |
| VERBOSE(("task_switch: new_ip is out of range. new_ip = %08x, limit = %08x", CPU_EIP, CPU_STAT_CS_LIMIT)); | &sreg_sel[CPU_CS_INDEX].desc, new_cpl); |
| EXCEPTION(GP_EXCEPTION, 0); | |
| } | } |
| VERBOSE(("task_switch: done.")); | VERBOSE(("task_switch: done.")); |