| version 1.23, 2008/03/22 04:03:08 | version 1.30, 2011/12/29 13:32:12 | 
| Line 1 | Line 1 | 
 | /*      $Id$    */ |  | 
 |  |  | 
 | /* | /* | 
 | * Copyright (c) 2003 NONAKA Kimihiro | * Copyright (c) 2003 NONAKA Kimihiro | 
 | * All rights reserved. | * All rights reserved. | 
| Line 29 | Line 27 | 
 | #include "cpu.h" | #include "cpu.h" | 
 | #include "ia32.mcr" | #include "ia32.mcr" | 
 |  |  | 
| #define TSS_SIZE_16     44 | #define TSS_16_SIZE     44 | 
| #define TSS_SIZE_32     108 | #define TSS_16_LIMIT    (TSS_16_SIZE - 1) | 
|  | #define TSS_32_SIZE     104 | 
|  | #define TSS_32_LIMIT    (TSS_32_SIZE - 1) | 
 |  |  | 
| static void | static void CPUCALL | 
| set_task_busy(UINT16 selector, descriptor_t *sdp) | set_task_busy(UINT16 selector) | 
 | { | { | 
 | UINT32 addr; | UINT32 addr; | 
 | UINT32 h; | UINT32 h; | 
| Line 41  set_task_busy(UINT16 selector, descripto | Line 41  set_task_busy(UINT16 selector, descripto | 
 | addr = CPU_GDTR_BASE + (selector & CPU_SEGMENT_SELECTOR_INDEX_MASK); | addr = CPU_GDTR_BASE + (selector & CPU_SEGMENT_SELECTOR_INDEX_MASK); | 
 | h = cpu_kmemoryread_d(addr + 4); | h = cpu_kmemoryread_d(addr + 4); | 
 | if (!(h & CPU_TSS_H_BUSY)) { | if (!(h & CPU_TSS_H_BUSY)) { | 
 | sdp->type |= CPU_SYSDESC_TYPE_TSS_BUSY_IND; |  | 
 | h |= CPU_TSS_H_BUSY; | h |= CPU_TSS_H_BUSY; | 
 | cpu_kmemorywrite_d(addr + 4, h); | cpu_kmemorywrite_d(addr + 4, h); | 
 | } else { | } else { | 
| Line 49  set_task_busy(UINT16 selector, descripto | Line 48  set_task_busy(UINT16 selector, descripto | 
 | } | } | 
 | } | } | 
 |  |  | 
| static void | static void CPUCALL | 
| set_task_free(UINT16 selector, descriptor_t *sdp) | set_task_free(UINT16 selector) | 
 | { | { | 
 | UINT32 addr; | UINT32 addr; | 
 | UINT32 h; | UINT32 h; | 
| Line 58  set_task_free(UINT16 selector, descripto | Line 57  set_task_free(UINT16 selector, descripto | 
 | addr = CPU_GDTR_BASE + (selector & CPU_SEGMENT_SELECTOR_INDEX_MASK); | addr = CPU_GDTR_BASE + (selector & CPU_SEGMENT_SELECTOR_INDEX_MASK); | 
 | h = cpu_kmemoryread_d(addr + 4); | h = cpu_kmemoryread_d(addr + 4); | 
 | if (h & CPU_TSS_H_BUSY) { | if (h & CPU_TSS_H_BUSY) { | 
 | sdp->type &= ~CPU_SYSDESC_TYPE_TSS_BUSY_IND; |  | 
 | h &= ~CPU_TSS_H_BUSY; | h &= ~CPU_TSS_H_BUSY; | 
 | cpu_kmemorywrite_d(addr + 4, h); | cpu_kmemorywrite_d(addr + 4, h); | 
 | } else { | } else { | 
| Line 66  set_task_free(UINT16 selector, descripto | Line 64  set_task_free(UINT16 selector, descripto | 
 | } | } | 
 | } | } | 
 |  |  | 
| void | void CPUCALL | 
 | load_tr(UINT16 selector) | load_tr(UINT16 selector) | 
 | { | { | 
 | selector_t task_sel; | selector_t task_sel; | 
| Line 84  load_tr(UINT16 selector) | Line 82  load_tr(UINT16 selector) | 
 | /* check descriptor type & stack room size */ | /* check descriptor type & stack room size */ | 
 | switch (task_sel.desc.type) { | switch (task_sel.desc.type) { | 
 | case CPU_SYSDESC_TYPE_TSS_16: | case CPU_SYSDESC_TYPE_TSS_16: | 
| if (task_sel.desc.u.seg.limit < TSS_SIZE_16) { | if (task_sel.desc.u.seg.limit < TSS_16_LIMIT) { | 
 | EXCEPTION(TS_EXCEPTION, task_sel.idx); | EXCEPTION(TS_EXCEPTION, task_sel.idx); | 
 | } | } | 
 | iobase = 0; | iobase = 0; | 
 | break; | break; | 
 |  |  | 
 | case CPU_SYSDESC_TYPE_TSS_32: | case CPU_SYSDESC_TYPE_TSS_32: | 
| if (task_sel.desc.u.seg.limit < TSS_SIZE_32) { | if (task_sel.desc.u.seg.limit < TSS_32_LIMIT) { | 
 | EXCEPTION(TS_EXCEPTION, task_sel.idx); | EXCEPTION(TS_EXCEPTION, task_sel.idx); | 
 | } | } | 
 | iobase = cpu_kmemoryread_w(task_sel.desc.u.seg.segbase + 102); | iobase = cpu_kmemoryread_w(task_sel.desc.u.seg.segbase + 102); | 
| Line 112  load_tr(UINT16 selector) | Line 110  load_tr(UINT16 selector) | 
 | tr_dump(task_sel.selector, task_sel.desc.u.seg.segbase, task_sel.desc.u.seg.limit); | tr_dump(task_sel.selector, task_sel.desc.u.seg.segbase, task_sel.desc.u.seg.limit); | 
 | #endif | #endif | 
 |  |  | 
| set_task_busy(task_sel.selector, &task_sel.desc); | set_task_busy(task_sel.selector); | 
 | CPU_TR = task_sel.selector; | CPU_TR = task_sel.selector; | 
 | CPU_TR_DESC = task_sel.desc; | CPU_TR_DESC = task_sel.desc; | 
 |  | CPU_TR_DESC.type |= CPU_SYSDESC_TYPE_TSS_BUSY_IND; | 
 |  |  | 
 | /* I/O deny bitmap */ | /* I/O deny bitmap */ | 
 | CPU_STAT_IOLIMIT = 0; | CPU_STAT_IOLIMIT = 0; | 
| if (task_sel.desc.type == CPU_SYSDESC_TYPE_TSS_BUSY_32) { | if (CPU_TR_DESC.type == CPU_SYSDESC_TYPE_TSS_BUSY_32) { | 
| if (iobase != 0 && iobase < task_sel.desc.u.seg.limit) { | if (iobase != 0 && iobase < CPU_TR_DESC.u.seg.limit) { | 
| CPU_STAT_IOLIMIT = (UINT16)(task_sel.desc.u.seg.limit - iobase); | CPU_STAT_IOLIMIT = (UINT16)(CPU_TR_DESC.u.seg.limit - iobase); | 
| CPU_STAT_IOADDR = task_sel.desc.u.seg.segbase + iobase; | CPU_STAT_IOADDR = CPU_TR_DESC.u.seg.segbase + iobase; | 
 | } | } | 
 | } | } | 
 |  |  | 
| Line 137  load_tr(UINT16 selector) | Line 136  load_tr(UINT16 selector) | 
 | #endif | #endif | 
 | } | } | 
 |  |  | 
| void | void CPUCALL | 
 | get_stack_pointer_from_tss(UINT pl, UINT16 *new_ss, UINT32 *new_esp) | get_stack_pointer_from_tss(UINT pl, UINT16 *new_ss, UINT32 *new_esp) | 
 | { | { | 
 | UINT32 tss_stack_addr; | UINT32 tss_stack_addr; | 
| Line 191  get_backlink_selector_from_tss(void) | Line 190  get_backlink_selector_from_tss(void) | 
 | return backlink; | return backlink; | 
 | } | } | 
 |  |  | 
| void | void CPUCALL | 
 | task_switch(selector_t *task_sel, task_switch_type_t type) | task_switch(selector_t *task_sel, task_switch_type_t type) | 
 | { | { | 
 | UINT32 regs[CPU_REG_NUM]; | UINT32 regs[CPU_REG_NUM]; | 
| Line 217  task_switch(selector_t *task_sel, task_s | Line 216  task_switch(selector_t *task_sel, task_s | 
 | switch (task_sel->desc.type) { | switch (task_sel->desc.type) { | 
 | case CPU_SYSDESC_TYPE_TSS_32: | case CPU_SYSDESC_TYPE_TSS_32: | 
 | case CPU_SYSDESC_TYPE_TSS_BUSY_32: | case CPU_SYSDESC_TYPE_TSS_BUSY_32: | 
| if (task_sel->desc.u.seg.limit < TSS_SIZE_32) { | if (task_sel->desc.u.seg.limit < TSS_32_LIMIT) { | 
 | EXCEPTION(TS_EXCEPTION, task_sel->idx); | EXCEPTION(TS_EXCEPTION, task_sel->idx); | 
 | } | } | 
 | task16 = 0; | task16 = 0; | 
| Line 225  task_switch(selector_t *task_sel, task_s | Line 224  task_switch(selector_t *task_sel, task_s | 
 |  |  | 
 | case CPU_SYSDESC_TYPE_TSS_16: | case CPU_SYSDESC_TYPE_TSS_16: | 
 | case CPU_SYSDESC_TYPE_TSS_BUSY_16: | case CPU_SYSDESC_TYPE_TSS_BUSY_16: | 
| if (task_sel->desc.u.seg.limit < TSS_SIZE_16) { | if (task_sel->desc.u.seg.limit < TSS_16_LIMIT) { | 
 | EXCEPTION(TS_EXCEPTION, task_sel->idx); | EXCEPTION(TS_EXCEPTION, task_sel->idx); | 
 | } | } | 
 | task16 = 1; | task16 = 1; | 
| Line 334  task_switch(selector_t *task_sel, task_s | Line 333  task_switch(selector_t *task_sel, task_s | 
 | /*FALLTHROUGH*/ | /*FALLTHROUGH*/ | 
 | case TASK_SWITCH_JMP: | case TASK_SWITCH_JMP: | 
 | /* clear busy flags in current task */ | /* clear busy flags in current task */ | 
| set_task_free(CPU_TR, &CPU_TR_DESC); | set_task_free(CPU_TR); | 
 | break; | break; | 
 |  |  | 
 | case TASK_SWITCH_CALL: | case TASK_SWITCH_CALL: | 
| Line 409  task_switch(selector_t *task_sel, task_s | Line 408  task_switch(selector_t *task_sel, task_s | 
 | new_flags |= NT_FLAG; | new_flags |= NT_FLAG; | 
 | /*FALLTHROUGH*/ | /*FALLTHROUGH*/ | 
 | case TASK_SWITCH_JMP: | case TASK_SWITCH_JMP: | 
| set_task_busy(task_sel->selector, &task_sel->desc); | set_task_busy(task_sel->selector); | 
 | break; | break; | 
|  |  | 
 | case TASK_SWITCH_IRET: | case TASK_SWITCH_IRET: | 
 | /* check busy flag is active */ | /* check busy flag is active */ | 
 | if (SEG_IS_VALID(&task_sel->desc)) { | if (SEG_IS_VALID(&task_sel->desc)) { | 
| Line 431  task_switch(selector_t *task_sel, task_s | Line 430  task_switch(selector_t *task_sel, task_s | 
 | /* load task selector to CPU_TR */ | /* load task selector to CPU_TR */ | 
 | CPU_TR = task_sel->selector; | CPU_TR = task_sel->selector; | 
 | CPU_TR_DESC = task_sel->desc; | CPU_TR_DESC = task_sel->desc; | 
|  | CPU_TR_DESC.type |= CPU_SYSDESC_TYPE_TSS_BUSY_IND; | 
| /* clear BUSY flag in descriptor cache */ |  | 
| CPU_TR_DESC.type &= ~CPU_SYSDESC_TYPE_TSS_BUSY_IND; |  | 
 |  |  | 
 | /* set CR0 image CPU_CR0_TS */ | /* set CR0 image CPU_CR0_TS */ | 
 | CPU_CR0 |= CPU_CR0_TS; | CPU_CR0 |= CPU_CR0_TS; | 
 |  |  | 
 | /* | /* | 
| * load task state (CR3, EFLAG, EIP, GPR, segreg, LDTR) | * load task state (CR3, EIP, GPR, segregs, LDTR, EFLAGS) | 
 | */ | */ | 
 |  |  | 
 | /* set new CR3 */ | /* set new CR3 */ | 
| Line 447  task_switch(selector_t *task_sel, task_s | Line 444  task_switch(selector_t *task_sel, task_s | 
 | set_cr3(cr3); | set_cr3(cr3); | 
 | } | } | 
 |  |  | 
| /* set new EIP, GPR */ | /* set new EIP, GPR, segregs */ | 
 | CPU_EIP = eip; | CPU_EIP = eip; | 
 | for (i = 0; i < CPU_REG_NUM; i++) { | for (i = 0; i < CPU_REG_NUM; i++) { | 
 | CPU_REGS_DWORD(i) = regs[i]; | CPU_REGS_DWORD(i) = regs[i]; | 
 | } | } | 
 | for (i = 0; i < CPU_SEGREG_NUM; i++) { | for (i = 0; i < CPU_SEGREG_NUM; i++) { | 
 | segdesc_init(i, sreg[i], &CPU_STAT_SREG(i)); | segdesc_init(i, sreg[i], &CPU_STAT_SREG(i)); | 
 |  | /* invalidate segreg descriptor */ | 
 |  | CPU_STAT_SREG(i).valid = 0; | 
 | } | } | 
 |  |  | 
 |  | CPU_CLEAR_PREV_ESP(); | 
 |  |  | 
 | /* load new LDTR */ | /* load new LDTR */ | 
 |  | CPU_LDTR_DESC.valid = 0; | 
 | load_ldtr(ldtr, TS_EXCEPTION); | load_ldtr(ldtr, TS_EXCEPTION); | 
 |  |  | 
 | /* I/O deny bitmap */ | /* I/O deny bitmap */ | 
 | CPU_STAT_IOLIMIT = 0; | CPU_STAT_IOLIMIT = 0; | 
| if (!task16 && iobase != 0 && iobase < task_sel->desc.u.seg.limit) { | if (!task16 && iobase != 0 && iobase < CPU_TR_DESC.u.seg.limit) { | 
| CPU_STAT_IOLIMIT = (UINT16)(task_sel->desc.u.seg.limit - iobase); | CPU_STAT_IOLIMIT = (UINT16)(CPU_TR_DESC.u.seg.limit - iobase); | 
 | CPU_STAT_IOADDR = task_base + iobase; | CPU_STAT_IOADDR = task_base + iobase; | 
 | } | } | 
 | VERBOSE(("task_switch: ioaddr = %08x, limit = %08x", CPU_STAT_IOADDR, CPU_STAT_IOLIMIT)); | VERBOSE(("task_switch: ioaddr = %08x, limit = %08x", CPU_STAT_IOADDR, CPU_STAT_IOLIMIT)); | 
| Line 488  task_switch(selector_t *task_sel, task_s | Line 490  task_switch(selector_t *task_sel, task_s | 
 |  |  | 
 | /* set new segment register */ | /* set new segment register */ | 
 | if (!CPU_STAT_VM86) { | if (!CPU_STAT_VM86) { | 
| /* clear segment descriptor cache */ | /* load SS */ | 
| for (i = 0; i < CPU_SEGREG_NUM; i++) { | rv = parse_selector(&ss_sel, sreg[CPU_SS_INDEX]); | 
| segdesc_clear(&CPU_STAT_SREG(i)); | if (rv < 0) { | 
|  | VERBOSE(("task_switch: load SS failure (sel = 0x%04x, rv = %d)", sreg[CPU_SS_INDEX], rv)); | 
|  | EXCEPTION(TS_EXCEPTION, ss_sel.idx); | 
 | } | } | 
 |  |  | 
 |  | /* SS must be writable data segment */ | 
 |  | if (SEG_IS_SYSTEM(&ss_sel.desc) | 
 |  | || SEG_IS_CODE(&ss_sel.desc) | 
 |  | || !SEG_IS_WRITABLE_DATA(&ss_sel.desc)) { | 
 |  | EXCEPTION(TS_EXCEPTION, ss_sel.idx); | 
 |  | } | 
 |  |  | 
 |  | /* check privilege level */ | 
 |  | if ((ss_sel.desc.dpl != cs_sel.rpl) | 
 |  | || (ss_sel.desc.dpl != ss_sel.rpl)) { | 
 |  | EXCEPTION(TS_EXCEPTION, ss_sel.idx); | 
 |  | } | 
 |  |  | 
 |  | /* stack segment is not present */ | 
 |  | rv = selector_is_not_present(&ss_sel); | 
 |  | if (rv < 0) { | 
 |  | EXCEPTION(SS_EXCEPTION, ss_sel.idx); | 
 |  | } | 
 |  |  | 
 |  | /* Now loading SS register */ | 
 |  | load_ss(ss_sel.selector, &ss_sel.desc, cs_sel.rpl); | 
 |  |  | 
 |  | /* load ES, DS, FS, GS segment register */ | 
 |  | LOAD_SEGREG1(CPU_ES_INDEX, sreg[CPU_ES_INDEX], TS_EXCEPTION); | 
 |  | LOAD_SEGREG1(CPU_DS_INDEX, sreg[CPU_DS_INDEX], TS_EXCEPTION); | 
 |  | LOAD_SEGREG1(CPU_FS_INDEX, sreg[CPU_FS_INDEX], TS_EXCEPTION); | 
 |  | LOAD_SEGREG1(CPU_GS_INDEX, sreg[CPU_GS_INDEX], TS_EXCEPTION); | 
 |  |  | 
 | /* load CS */ | /* load CS */ | 
 | rv = parse_selector(&cs_sel, sreg[CPU_CS_INDEX]); | rv = parse_selector(&cs_sel, sreg[CPU_CS_INDEX]); | 
 | if (rv < 0) { | if (rv < 0) { | 
| Line 524  task_switch(selector_t *task_sel, task_s | Line 556  task_switch(selector_t *task_sel, task_s | 
 | EXCEPTION(NP_EXCEPTION, cs_sel.idx); | EXCEPTION(NP_EXCEPTION, cs_sel.idx); | 
 | } | } | 
 |  |  | 
| /* load SS */ | /* Now loading CS register */ | 
| rv = parse_selector(&ss_sel, sreg[CPU_SS_INDEX]); |  | 
| if (rv < 0) { |  | 
| VERBOSE(("task_switch: load SS failure (sel = 0x%04x, rv = %d)", sreg[CPU_SS_INDEX], rv)); |  | 
| EXCEPTION(TS_EXCEPTION, ss_sel.idx); |  | 
| } |  | 
|  |  | 
| /* SS must be writable data segment */ |  | 
| if (SEG_IS_SYSTEM(&ss_sel.desc) |  | 
| || SEG_IS_CODE(&ss_sel.desc) |  | 
| || !SEG_IS_WRITABLE_DATA(&ss_sel.desc)) { |  | 
| EXCEPTION(TS_EXCEPTION, ss_sel.idx); |  | 
| } |  | 
|  |  | 
| /* check privilege level */ |  | 
| if ((ss_sel.desc.dpl != cs_sel.rpl) |  | 
| || (ss_sel.desc.dpl != ss_sel.rpl)) { |  | 
| EXCEPTION(TS_EXCEPTION, ss_sel.idx); |  | 
| } |  | 
|  |  | 
| /* stack segment is not present */ |  | 
| rv = selector_is_not_present(&ss_sel); |  | 
| if (rv < 0) { |  | 
| EXCEPTION(SS_EXCEPTION, ss_sel.idx); |  | 
| } |  | 
|  |  | 
| /* Now loading CS/SS register */ |  | 
 | load_cs(cs_sel.selector, &cs_sel.desc, cs_sel.rpl); | load_cs(cs_sel.selector, &cs_sel.desc, cs_sel.rpl); | 
 | load_ss(ss_sel.selector, &ss_sel.desc, cs_sel.rpl); |  | 
 |  |  | 
 | /* load ES, DS, FS, GS segment register */ |  | 
 | for (i = 0; i < CPU_SEGREG_NUM; i++) { |  | 
 | if (i != CPU_CS_INDEX || i != CPU_SS_INDEX) { |  | 
 | LOAD_SEGREG1(i, sreg[i], TS_EXCEPTION); |  | 
 | } |  | 
 | } |  | 
 | } |  | 
 |  |  | 
 | /* out of range */ |  | 
 | if (CPU_EIP > CPU_STAT_CS_LIMIT) { |  | 
 | VERBOSE(("task_switch: new_ip is out of range. new_ip = %08x, limit = %08x", CPU_EIP, CPU_STAT_CS_LIMIT)); |  | 
 | EXCEPTION(GP_EXCEPTION, 0); |  | 
 | } | } | 
 |  |  | 
 | VERBOSE(("task_switch: done.")); | VERBOSE(("task_switch: done.")); |