| version 1.31, 2011/12/29 14:30:31 | version 1.33, 2012/01/08 11:36:06 | 
| Line 69  load_tr(UINT16 selector) | Line 69  load_tr(UINT16 selector) | 
 | { | { | 
 | selector_t task_sel; | selector_t task_sel; | 
 | int rv; | int rv; | 
 | #if defined(IA32_SUPPORT_DEBUG_REGISTER) |  | 
 | int i; |  | 
 | #endif |  | 
 | UINT16 iobase; | UINT16 iobase; | 
 |  |  | 
 | rv = parse_selector(&task_sel, selector); | rv = parse_selector(&task_sel, selector); | 
| Line 123  load_tr(UINT16 selector) | Line 120  load_tr(UINT16 selector) | 
 | CPU_STAT_IOADDR = CPU_TR_DESC.u.seg.segbase + iobase; | CPU_STAT_IOADDR = CPU_TR_DESC.u.seg.segbase + iobase; | 
 | } | } | 
 | } | } | 
 |  |  | 
 | #if defined(IA32_SUPPORT_DEBUG_REGISTER) |  | 
 | /* clear local break point flags */ |  | 
 | CPU_DR7 &= ~(CPU_DR7_L(0)|CPU_DR7_L(1)|CPU_DR7_L(2)|CPU_DR7_L(3)|CPU_DR7_LE); |  | 
 | CPU_STAT_BP = 0; |  | 
 | for (i = 0; i < CPU_DEBUG_REG_INDEX_NUM; i++) { |  | 
 | if (CPU_DR7 & CPU_DR7_G(i)) { |  | 
 | CPU_STAT_BP |= (1 << i); |  | 
 | } |  | 
 | } |  | 
 | #endif |  | 
 | } | } | 
 |  |  | 
 | void CPUCALL | void CPUCALL | 
| Line 142  get_stack_pointer_from_tss(UINT pl, UINT | Line 128  get_stack_pointer_from_tss(UINT pl, UINT | 
 | UINT32 tss_stack_addr; | UINT32 tss_stack_addr; | 
 |  |  | 
 | VERBOSE(("get_stack_pointer_from_tss: pl = %d", pl)); | VERBOSE(("get_stack_pointer_from_tss: pl = %d", pl)); | 
| VERBOSE(("CPU_TR type = %d, base = 0x%08x, limit = 0x%08x", CPU_TR_DESC.type, CPU_TR_BASE, CPU_TR_LIMIT)); | VERBOSE(("get_stack_pointer_from_tss: CPU_TR type = %d, base = 0x%08x, limit = 0x%08x", CPU_TR_DESC.type, CPU_TR_BASE, CPU_TR_LIMIT)); | 
 |  |  | 
 | __ASSERT(pl < 3); | __ASSERT(pl < 3); | 
 |  |  | 
| Line 165  get_stack_pointer_from_tss(UINT pl, UINT | Line 151  get_stack_pointer_from_tss(UINT pl, UINT | 
 | } else { | } else { | 
 | ia32_panic("get_stack_pointer_from_tss: task register is invalid (%d)\n", CPU_TR_DESC.type); | ia32_panic("get_stack_pointer_from_tss: task register is invalid (%d)\n", CPU_TR_DESC.type); | 
 | } | } | 
| VERBOSE(("new stack pointer = %04x:%08x", *new_ss, *new_esp)); | VERBOSE(("get_stack_pointer_from_tss: new stack pointer = %04x:%08x", *new_ss, *new_esp)); | 
 | } | } | 
 |  |  | 
 | UINT16 | UINT16 | 
| Line 469  task_switch(selector_t *task_sel, task_s | Line 455  task_switch(selector_t *task_sel, task_s | 
 | } | } | 
 | VERBOSE(("task_switch: ioaddr = %08x, limit = %08x", CPU_STAT_IOADDR, CPU_STAT_IOLIMIT)); | VERBOSE(("task_switch: ioaddr = %08x, limit = %08x", CPU_STAT_IOADDR, CPU_STAT_IOLIMIT)); | 
 |  |  | 
 | #if defined(IA32_SUPPORT_DEBUG_REGISTER) |  | 
 | /* check resume flag */ |  | 
 | if (CPU_EFLAG & RF_FLAG) { |  | 
 | CPU_STAT_BP_EVENT |= CPU_STAT_BP_EVENT_RF; |  | 
 | } |  | 
 |  |  | 
 | /* clear local break point flags */ |  | 
 | CPU_DR7 &= ~(CPU_DR7_L(0)|CPU_DR7_L(1)|CPU_DR7_L(2)|CPU_DR7_L(3)|CPU_DR7_LE); |  | 
 | CPU_STAT_BP = 0; |  | 
 | for (i = 0; i < CPU_DEBUG_REG_INDEX_NUM; i++) { |  | 
 | if (CPU_DR7 & CPU_DR7_G(i)) { |  | 
 | CPU_STAT_BP |= (1 << i); |  | 
 | } |  | 
 | } |  | 
 | #endif |  | 
 |  |  | 
 | /* set new EFLAGS */ | /* set new EFLAGS */ | 
 | set_eflags(new_flags, I_FLAG|IOPL_FLAG|RF_FLAG|VM_FLAG|VIF_FLAG|VIP_FLAG); | set_eflags(new_flags, I_FLAG|IOPL_FLAG|RF_FLAG|VM_FLAG|VIF_FLAG|VIP_FLAG); | 
 |  |  |