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| version 1.36, 2012/02/07 08:01:55 | version 1.37, 2012/02/07 08:14:07 |
|---|---|
| Line 44 set_task_busy(UINT16 selector) | Line 44 set_task_busy(UINT16 selector) |
| h |= CPU_TSS_H_BUSY; | h |= CPU_TSS_H_BUSY; |
| cpu_kmemorywrite_d(addr + 4, h); | cpu_kmemorywrite_d(addr + 4, h); |
| } else { | } else { |
| ia32_panic("set_task_busy: already busy(%04x:%08x)",selector,h); | ia32_panic("set_task_busy: already busy(%04x:%08x)", |
| selector, h); | |
| } | } |
| } | } |
| Line 60 set_task_free(UINT16 selector) | Line 61 set_task_free(UINT16 selector) |
| h &= ~CPU_TSS_H_BUSY; | h &= ~CPU_TSS_H_BUSY; |
| cpu_kmemorywrite_d(addr + 4, h); | cpu_kmemorywrite_d(addr + 4, h); |
| } else { | } else { |
| ia32_panic("set_task_free: already free(%04x:%08x)",selector,h); | ia32_panic("set_task_free: already free(%04x:%08x)", |
| selector, h); | |
| } | } |
| } | } |
| Line 155 get_stack_pointer_from_tss(UINT pl, UINT | Line 157 get_stack_pointer_from_tss(UINT pl, UINT |
| } else { | } else { |
| ia32_panic("get_stack_pointer_from_tss: task register is invalid (%d)\n", CPU_TR_DESC.type); | ia32_panic("get_stack_pointer_from_tss: task register is invalid (%d)\n", CPU_TR_DESC.type); |
| } | } |
| VERBOSE(("get_stack_pointer_from_tss: new stack pointer = %04x:%08x", *new_ss, *new_esp)); | VERBOSE(("get_stack_pointer_from_tss: new stack pointer = %04x:%08x", |
| *new_ss, *new_esp)); | |
| } | } |
| UINT16 | UINT16 |
| Line 176 get_backlink_selector_from_tss(void) | Line 179 get_backlink_selector_from_tss(void) |
| } | } |
| backlink = cpu_kmemoryread_w(CPU_TR_BASE); | backlink = cpu_kmemoryread_w(CPU_TR_BASE); |
| VERBOSE(("get_backlink_selector_from_tss: backlink selector = 0x%04x", backlink)); | VERBOSE(("get_backlink_selector_from_tss: backlink selector = 0x%04x", |
| backlink)); | |
| return backlink; | return backlink; |
| } | } |
| Line 230 task_switch(selector_t *task_sel, task_s | Line 234 task_switch(selector_t *task_sel, task_s |
| cur_paddr = laddr_to_paddr(cur_base, CPU_PAGE_WRITE_DATA|CPU_MODE_SUPERVISER); | cur_paddr = laddr_to_paddr(cur_base, CPU_PAGE_WRITE_DATA|CPU_MODE_SUPERVISER); |
| task_base = task_sel->desc.u.seg.segbase; | task_base = task_sel->desc.u.seg.segbase; |
| task_paddr = laddr_to_paddr(task_base, CPU_PAGE_WRITE_DATA|CPU_MODE_SUPERVISER); | task_paddr = laddr_to_paddr(task_base, CPU_PAGE_WRITE_DATA|CPU_MODE_SUPERVISER); |
| VERBOSE(("task_switch: current task (%04x) = 0x%08x:%08x", CPU_TR, cur_base, CPU_TR_LIMIT)); | VERBOSE(("task_switch: current task (%04x) = 0x%08x:%08x (p0x%08x)", |
| VERBOSE(("task_switch: new task (%04x) = 0x%08x:%08x", task_sel->selector, task_base, task_sel->desc.u.seg.limit)); | CPU_TR, cur_base, CPU_TR_LIMIT, cur_paddr)); |
| VERBOSE(("task_switch: new task (%04x) = 0x%08x:%08x (p0x%08x)", | |
| task_sel->selector, task_base, task_sel->desc.u.seg.limit, | |
| task_paddr)); | |
| VERBOSE(("task_switch: %dbit task switch", task16 ? 16 : 32)); | VERBOSE(("task_switch: %dbit task switch", task16 ? 16 : 32)); |
| #if defined(MORE_DEBUG) | #if defined(MORE_DEBUG) |