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| version 1.5, 2004/01/23 14:33:26 | version 1.9, 2004/02/05 16:43:44 |
|---|---|
| Line 68 load_tr(WORD selector) | Line 68 load_tr(WORD selector) |
| EXCEPTION(NP_EXCEPTION, task_sel.idx); | EXCEPTION(NP_EXCEPTION, task_sel.idx); |
| } | } |
| #if defined(DEBUG) | #if defined(MORE_DEBUG) |
| tr_dump(task_sel.selector, task_sel.desc.u.seg.segbase, task_sel.desc.u.seg.limit); | tr_dump(task_sel.selector, task_sel.desc.u.seg.segbase, task_sel.desc.u.seg.limit); |
| #endif | #endif |
| CPU_SET_TASK_BUSY(&task_sel.desc); | CPU_SET_TASK_BUSY(task_sel.selector, &task_sel.desc); |
| CPU_TR = task_sel.selector; | CPU_TR = task_sel.selector; |
| CPU_TR_DESC = task_sel.desc; | CPU_TR_DESC = task_sel.desc; |
| } | } |
| Line 90 get_stack_from_tss(DWORD pl, WORD *new_s | Line 90 get_stack_from_tss(DWORD pl, WORD *new_s |
| EXCEPTION(TS_EXCEPTION, CPU_TR & ~3); | EXCEPTION(TS_EXCEPTION, CPU_TR & ~3); |
| } | } |
| tss_stack_addr += CPU_TR_DESC.u.seg.segbase; | tss_stack_addr += CPU_TR_DESC.u.seg.segbase; |
| *new_esp = cpu_lmemoryread_d(tss_stack_addr); | *new_esp = cpu_kmemoryread_d(tss_stack_addr); |
| *new_ss = cpu_lmemoryread_w(tss_stack_addr + 4); | *new_ss = cpu_kmemoryread_w(tss_stack_addr + 4); |
| } else if (CPU_TR_DESC.type == CPU_SYSDESC_TYPE_TSS_BUSY_16) { | } else if (CPU_TR_DESC.type == CPU_SYSDESC_TYPE_TSS_BUSY_16) { |
| tss_stack_addr = pl * 4 + 2; | tss_stack_addr = pl * 4 + 2; |
| if (tss_stack_addr + 3 > CPU_TR_DESC.u.seg.limit) { | if (tss_stack_addr + 3 > CPU_TR_DESC.u.seg.limit) { |
| EXCEPTION(TS_EXCEPTION, CPU_TR & ~3); | EXCEPTION(TS_EXCEPTION, CPU_TR & ~3); |
| } | } |
| tss_stack_addr += CPU_TR_DESC.u.seg.segbase; | tss_stack_addr += CPU_TR_DESC.u.seg.segbase; |
| *new_esp = cpu_lmemoryread_w(tss_stack_addr); | *new_esp = cpu_kmemoryread_w(tss_stack_addr); |
| *new_ss = cpu_lmemoryread_w(tss_stack_addr + 2); | *new_ss = cpu_kmemoryread_w(tss_stack_addr + 2); |
| } else { | } else { |
| ia32_panic("get_stack_from_tss: task register is invalid (%d)\n", CPU_TR_DESC.type); | ia32_panic("get_stack_from_tss: task register is invalid (%d)\n", CPU_TR_DESC.type); |
| } | } |
| VERBOSE(("get_stack_from_tss: new_esp = 0x%08x, new_ss = 0x%04x", *new_esp, *new_ss)); | VERBOSE(("get_stack_from_tss: pl = %d, new_esp = 0x%08x, new_ss = 0x%04x", pl, *new_esp, *new_ss)); |
| } | } |
| WORD | WORD |
| Line 124 get_link_selector_from_tss() | Line 124 get_link_selector_from_tss() |
| ia32_panic("get_link_selector_from_tss: task register is invalid (%d)\n", CPU_TR_DESC.type); | ia32_panic("get_link_selector_from_tss: task register is invalid (%d)\n", CPU_TR_DESC.type); |
| } | } |
| backlink = cpu_lmemoryread_w(CPU_TR_DESC.u.seg.segbase); | backlink = cpu_kmemoryread_w(CPU_TR_DESC.u.seg.segbase); |
| VERBOSE(("get_link_selector_from_tss: backlink selector = 0x%04x", backlink)); | VERBOSE(("get_link_selector_from_tss: backlink selector = 0x%04x", backlink)); |
| return backlink; | return backlink; |
| } | } |
| Line 135 task_switch(selector_t* task_sel, int ty | Line 135 task_switch(selector_t* task_sel, int ty |
| DWORD regs[CPU_REG_NUM]; | DWORD regs[CPU_REG_NUM]; |
| DWORD eip; | DWORD eip; |
| DWORD new_flags; | DWORD new_flags; |
| DWORD mask; | |
| DWORD cr3 = 0; | DWORD cr3 = 0; |
| WORD sreg[CPU_SEGREG_NUM]; | WORD sreg[CPU_SEGREG_NUM]; |
| WORD ldtr; | WORD ldtr; |
| Line 152 task_switch(selector_t* task_sel, int ty | Line 153 task_switch(selector_t* task_sel, int ty |
| VERBOSE(("task_switch: start")); | VERBOSE(("task_switch: start")); |
| cur_base = CPU_TR_DESC.u.seg.segbase; | |
| task_base = task_sel->desc.u.seg.segbase; | |
| VERBOSE(("task_switch: current task base address = 0x%08x", cur_base)); | |
| VERBOSE(("task_switch: new task base address = 0x%08x", task_base)); | |
| /* limit check */ | /* limit check */ |
| switch (task_sel->desc.type) { | switch (task_sel->desc.type) { |
| case CPU_SYSDESC_TYPE_TSS_32: | case CPU_SYSDESC_TYPE_TSS_32: |
| Line 184 task_switch(selector_t* task_sel, int ty | Line 180 task_switch(selector_t* task_sel, int ty |
| break; | break; |
| } | } |
| #if defined(DEBUG) | cur_base = CPU_TR_DESC.u.seg.segbase; |
| task_base = task_sel->desc.u.seg.segbase; | |
| VERBOSE(("task_switch: cur task (%04x) = 0x%08x:%08x", CPU_TR, cur_base, CPU_TR_DESC.u.seg.limit)); | |
| VERBOSE(("task_switch: new task (%04x) = 0x%08x:%08x", task_sel->selector, task_base, task_sel->desc.u.seg.limit)); | |
| VERBOSE(("task_switch: %dbit task switch", task16 ? 16 : 32)); | |
| #if defined(MORE_DEBUG) | |
| { | { |
| DWORD v; | DWORD v; |
| VERBOSE(("task_switch: new task")); | VERBOSE(("task_switch: new task")); |
| for (i = 0; i < task_sel->desc.u.seg.limit; i += 4) { | for (i = 0; i < task_sel->desc.u.seg.limit; i += 4) { |
| v = cpu_lmemoryread_d(task_base + i); | v = cpu_kmemoryread_d(task_base + i); |
| VERBOSE(("task_switch: 0x%08x: %08x", task_base + i,v)); | VERBOSE(("task_switch: 0x%08x: %08x", task_base + i,v)); |
| } | } |
| } | } |
| Line 198 task_switch(selector_t* task_sel, int ty | Line 200 task_switch(selector_t* task_sel, int ty |
| if (CPU_STAT_PAGING) { | if (CPU_STAT_PAGING) { |
| /* task state paging check */ | /* task state paging check */ |
| paging_check(cur_base, CPU_TR_DESC.u.seg.limit, CPU_PAGING_PAGE_WRITE); | paging_check(cur_base, CPU_TR_DESC.u.seg.limit, CPU_PAGE_WRITE_DATA, CPU_MODE_SUPERVISER); |
| paging_check(task_base, task_sel->desc.u.seg.limit, CPU_PAGING_PAGE_WRITE); | paging_check(task_base, task_sel->desc.u.seg.limit, CPU_PAGE_WRITE_DATA, CPU_MODE_SUPERVISER); |
| } | } |
| /* load task state */ | /* load task state */ |
| memset(sreg, 0, sizeof(sreg)); | memset(sreg, 0, sizeof(sreg)); |
| if (!task16) { | if (!task16) { |
| if (CPU_STAT_PAGING) { | if (CPU_STAT_PAGING) { |
| cr3 = cpu_lmemoryread_d(task_base + 28); | cr3 = cpu_kmemoryread_d(task_base + 28); |
| } | } |
| eip = cpu_lmemoryread_d(task_base + 32); | eip = cpu_kmemoryread_d(task_base + 32); |
| new_flags = cpu_lmemoryread_d(task_base + 36); | new_flags = cpu_kmemoryread_d(task_base + 36); |
| for (i = 0; i < CPU_REG_NUM; i++) { | for (i = 0; i < CPU_REG_NUM; i++) { |
| regs[i] = cpu_lmemoryread_d(task_base + 40 + i * 4); | regs[i] = cpu_kmemoryread_d(task_base + 40 + i * 4); |
| } | } |
| for (i = 0; i < nsreg; i++) { | for (i = 0; i < nsreg; i++) { |
| sreg[i] = cpu_lmemoryread_w(task_base + 72 + i * 4); | sreg[i] = cpu_kmemoryread_w(task_base + 72 + i * 4); |
| } | } |
| ldtr = cpu_lmemoryread_w(task_base + 96); | ldtr = cpu_kmemoryread_w(task_base + 96); |
| t = cpu_lmemoryread_w(task_base + 100); | t = cpu_kmemoryread_w(task_base + 100); |
| t &= 1; | t &= 1; |
| iobase = cpu_lmemoryread_w(task_base + 102); | iobase = cpu_kmemoryread_w(task_base + 102); |
| } else { | } else { |
| eip = cpu_lmemoryread_w(task_base + 14); | eip = cpu_kmemoryread_w(task_base + 14); |
| new_flags = cpu_lmemoryread_w(task_base + 16); | new_flags = cpu_kmemoryread_w(task_base + 16); |
| for (i = 0; i < CPU_REG_NUM; i++) { | for (i = 0; i < CPU_REG_NUM; i++) { |
| regs[i] = cpu_lmemoryread_w(task_base + 18 + i * 2); | regs[i] = cpu_kmemoryread_w(task_base + 18 + i * 2); |
| } | } |
| for (i = 0; i < nsreg; i++) { | for (i = 0; i < nsreg; i++) { |
| sreg[i] = cpu_lmemoryread_w(task_base + 34 + i * 2); | sreg[i] = cpu_kmemoryread_w(task_base + 34 + i * 2); |
| } | } |
| ldtr = cpu_lmemoryread_w(task_base + 42); | ldtr = cpu_kmemoryread_w(task_base + 42); |
| t = 0; | t = 0; |
| iobase = 0; | iobase = 0; |
| } | } |
| #if defined(DEBUG) | #if defined(DEBUG) |
| VERBOSE(("task_switch: %dbit task", task16 ? 16 : 32)); | VERBOSE(("task_switch: current task")); |
| VERBOSE(("task_switch: CR3 = 0x%08x", cr3)); | VERBOSE(("task_switch: eip = 0x%08x", CPU_EIP)); |
| VERBOSE(("task_switch: eflags = 0x%08x", old_flags)); | |
| for (i = 0; i < CPU_REG_NUM; i++) { | |
| VERBOSE(("task_switch: regs[%d] = 0x%08x", i, CPU_REGS_DWORD(i))); | |
| } | |
| for (i = 0; i < nsreg; i++) { | |
| VERBOSE(("task_switch: sreg[%d] = 0x%04x", i, CPU_REGS_SREG(i))); | |
| } | |
| VERBOSE(("task_switch: new task")); | |
| if (!task16) { | |
| VERBOSE(("task_switch: CR3 = 0x%08x", cr3)); | |
| } | |
| VERBOSE(("task_switch: eip = 0x%08x", eip)); | VERBOSE(("task_switch: eip = 0x%08x", eip)); |
| VERBOSE(("task_switch: eflags = 0x%08x", new_flags)); | VERBOSE(("task_switch: eflags = 0x%08x", new_flags)); |
| for (i = 0; i < CPU_REG_NUM; i++) { | for (i = 0; i < CPU_REG_NUM; i++) { |
| Line 246 task_switch(selector_t* task_sel, int ty | Line 260 task_switch(selector_t* task_sel, int ty |
| VERBOSE(("task_switch: sreg[%d] = 0x%04x", i, sreg[i])); | VERBOSE(("task_switch: sreg[%d] = 0x%04x", i, sreg[i])); |
| } | } |
| VERBOSE(("task_switch: ldtr = 0x%04x", ldtr)); | VERBOSE(("task_switch: ldtr = 0x%04x", ldtr)); |
| VERBOSE(("task_switch: t = 0x%04x", t)); | if (!task16) { |
| VERBOSE(("task_switch: iobase = 0x%04x", iobase)); | VERBOSE(("task_switch: t = 0x%04x", t)); |
| VERBOSE(("task_switch: iobase = 0x%04x", iobase)); | |
| } | |
| #endif | #endif |
| /* if IRET or JMP, clear busy flag in this task: need */ | /* if IRET or JMP, clear busy flag in this task: need */ |
| Line 259 task_switch(selector_t* task_sel, int ty | Line 275 task_switch(selector_t* task_sel, int ty |
| /*FALLTHROUGH*/ | /*FALLTHROUGH*/ |
| case TASK_SWITCH_JMP: | case TASK_SWITCH_JMP: |
| /* clear busy flags in current task */ | /* clear busy flags in current task */ |
| CPU_SET_TASK_FREE(&CPU_TR_DESC); | CPU_SET_TASK_FREE(CPU_TR, &CPU_TR_DESC); |
| break; | break; |
| case TASK_SWITCH_CALL: | case TASK_SWITCH_CALL: |
| Line 272 task_switch(selector_t* task_sel, int ty | Line 288 task_switch(selector_t* task_sel, int ty |
| break; | break; |
| } | } |
| /* save this task state in this task state segment ind */ | /* save this task state in this task state segment */ |
| if (!task16) { | if (!task16) { |
| cpu_lmemorywrite_d(cur_base + 28, CPU_CR3); | cpu_kmemorywrite_d(cur_base + 32, CPU_EIP); |
| cpu_lmemorywrite_d(cur_base + 32, CPU_EIP); | cpu_kmemorywrite_d(cur_base + 36, old_flags); |
| cpu_lmemorywrite_d(cur_base + 36, old_flags); | |
| for (i = 0; i < CPU_REG_NUM; i++) { | for (i = 0; i < CPU_REG_NUM; i++) { |
| cpu_lmemorywrite_d(cur_base + 40 + i * 4, CPU_REGS_DWORD(i)); | cpu_kmemorywrite_d(cur_base + 40 + i * 4, CPU_REGS_DWORD(i)); |
| } | } |
| for (i = 0; i < nsreg; i++) { | for (i = 0; i < nsreg; i++) { |
| cpu_lmemorywrite_d(cur_base + 72 + i * 4, CPU_REGS_SREG(i)); | cpu_kmemorywrite_w(cur_base + 72 + i * 4, CPU_REGS_SREG(i)); |
| } | } |
| cpu_lmemorywrite_w(cur_base + 96, CPU_LDTR); | |
| } else { | } else { |
| cpu_lmemorywrite_w(cur_base + 14, CPU_IP); | cpu_kmemorywrite_w(cur_base + 14, CPU_IP); |
| cpu_lmemorywrite_w(cur_base + 16, (WORD)old_flags); | cpu_kmemorywrite_w(cur_base + 16, (WORD)old_flags); |
| for (i = 0; i < CPU_REG_NUM; i++) { | for (i = 0; i < CPU_REG_NUM; i++) { |
| cpu_lmemorywrite_w(cur_base + 18 + i * 2, CPU_REGS_WORD(i)); | cpu_kmemorywrite_w(cur_base + 18 + i * 2, CPU_REGS_WORD(i)); |
| } | } |
| for (i = 0; i < nsreg; i++) { | for (i = 0; i < nsreg; i++) { |
| cpu_lmemorywrite_w(cur_base + 34 + i * 2, CPU_REGS_SREG(i)); | cpu_kmemorywrite_w(cur_base + 34 + i * 2, CPU_REGS_SREG(i)); |
| } | } |
| cpu_lmemorywrite_w(cur_base + 42, CPU_LDTR); | |
| } | } |
| #if defined(DEBUG) | #if defined(MORE_DEBUG) |
| { | { |
| DWORD v; | DWORD v; |
| VERBOSE(("task_switch: current task")); | VERBOSE(("task_switch: current task")); |
| for (i = 0; i < CPU_TR_DESC.u.seg.limit; i += 4) { | for (i = 0; i < CPU_TR_DESC.u.seg.limit; i += 4) { |
| v = cpu_lmemoryread_d(cur_base + i); | v = cpu_kmemoryread_d(cur_base + i); |
| VERBOSE(("task_switch: 0x%08x: %08x", cur_base + i, v)); | VERBOSE(("task_switch: 0x%08x: %08x", cur_base + i, v)); |
| } | } |
| } | } |
| Line 312 task_switch(selector_t* task_sel, int ty | Line 325 task_switch(selector_t* task_sel, int ty |
| case TASK_SWITCH_CALL: | case TASK_SWITCH_CALL: |
| case TASK_SWITCH_INTR: | case TASK_SWITCH_INTR: |
| /* set back link selector */ | /* set back link selector */ |
| cpu_lmemorywrite_w(task_base, CPU_TR); | cpu_kmemorywrite_w(task_base, CPU_TR); |
| break; | break; |
| case TASK_SWITCH_IRET: | case TASK_SWITCH_IRET: |
| Line 336 task_switch(selector_t* task_sel, int ty | Line 349 task_switch(selector_t* task_sel, int ty |
| new_flags |= NT_FLAG; | new_flags |= NT_FLAG; |
| /*FALLTHROUGH*/ | /*FALLTHROUGH*/ |
| case TASK_SWITCH_JMP: | case TASK_SWITCH_JMP: |
| CPU_SET_TASK_BUSY(&task_sel->desc); | CPU_SET_TASK_BUSY(task_sel->selector, &task_sel->desc); |
| break; | break; |
| case TASK_SWITCH_IRET: | case TASK_SWITCH_IRET: |
| /* Nothing to do */ | /* check busy flag is active */ |
| /* XXX: if IRET, check busy flag is active? */ | if (task_sel->desc.valid) { |
| DWORD h; | |
| h = cpu_kmemoryread_d(task_sel->addr + 4); | |
| if ((h & CPU_TSS_H_BUSY) == 0) { | |
| ia32_panic("task_switch: new task is not busy"); | |
| } | |
| } | |
| break; | break; |
| default: | default: |
| Line 357 task_switch(selector_t* task_sel, int ty | Line 376 task_switch(selector_t* task_sel, int ty |
| CPU_TR_DESC = task_sel->desc; | CPU_TR_DESC = task_sel->desc; |
| /* load task state (CR3, EFLAG, EIP, GPR, segreg, LDTR) */ | /* load task state (CR3, EFLAG, EIP, GPR, segreg, LDTR) */ |
| if (!task16) { | |
| /* set new CR3 */ | |
| if (!task16 && CPU_STAT_PAGING) { | |
| set_CR3(cr3); | set_CR3(cr3); |
| } | } |
| /* set new EFLAGS */ | |
| set_eflags(new_flags, I_FLAG|IOPL_FLAG|RF_FLAG|VM_FLAG|VIF_FLAG|VIP_FLAG); | |
| /* set new EIP, GPR */ | /* set new EIP, GPR */ |
| CPU_PREV_EIP = CPU_EIP = eip; | CPU_PREV_EIP = CPU_EIP = eip; |
| for (i = 0; i < CPU_REG_NUM; i++) { | for (i = 0; i < CPU_REG_NUM; i++) { |
| Line 371 task_switch(selector_t* task_sel, int ty | Line 389 task_switch(selector_t* task_sel, int ty |
| } | } |
| for (i = 0; i < CPU_SEGREG_NUM; i++) { | for (i = 0; i < CPU_SEGREG_NUM; i++) { |
| CPU_REGS_SREG(i) = sreg[i]; | CPU_REGS_SREG(i) = sreg[i]; |
| CPU_STAT_SREG_CLEAR(i); | CPU_STAT_SREG_INIT(i); |
| } | } |
| /* set new EFLAGS */ | |
| mask = I_FLAG|IOPL_FLAG|RF_FLAG|VM_FLAG|VIF_FLAG|VIP_FLAG; | |
| set_eflags(new_flags, mask); | |
| /* load new LDTR */ | /* load new LDTR */ |
| load_ldtr(ldtr, TS_EXCEPTION); | load_ldtr(ldtr, TS_EXCEPTION); |
| /* set new segment register */ | /* set new segment register */ |
| if (CPU_STAT_VM86) { | if (!CPU_STAT_VM86) { |
| /* VM86 */ | /* clear segment descriptor cache */ |
| /* clear 32bit */ | for (i = 0; i < CPU_SEGREG_NUM; i++) { |
| CPU_STATSAVE.cpu_inst_default.op_32 = | CPU_STAT_SREG_CLEAR(i); |
| CPU_STATSAVE.cpu_inst_default.as_32 = 0; | |
| CPU_STAT_SS32 = 0; | |
| CPU_STAT_CPL = task_sel->desc.dpl; | |
| for (i = 0; i < nsreg; i++) { | |
| CPU_STAT_SREG_INIT(i); | |
| load_segreg(i, sreg[i], TS_EXCEPTION); | |
| } | } |
| } else { | |
| /* load CS */ | /* load CS */ |
| rv = parse_selector(&cs_sel, sreg[CPU_CS_INDEX]); | rv = parse_selector(&cs_sel, sreg[CPU_CS_INDEX]); |
| if (rv < 0) { | if (rv < 0) { |
| Line 426 task_switch(selector_t* task_sel, int ty | Line 441 task_switch(selector_t* task_sel, int ty |
| load_cs(cs_sel.selector, &cs_sel.desc, cs_sel.desc.dpl); | load_cs(cs_sel.selector, &cs_sel.desc, cs_sel.desc.dpl); |
| /* load ES, SS, DS, FS, GS segment register */ | /* load ES, SS, DS, FS, GS segment register */ |
| for (i = 0; i < nsreg; i++) { | for (i = 0; i < CPU_SEGREG_NUM; i++) { |
| if (i != CPU_CS_INDEX) { | if (i != CPU_CS_INDEX) { |
| load_segreg(i, sreg[i], TS_EXCEPTION); | load_segreg(i, sreg[i], TS_EXCEPTION); |
| } | } |
| Line 437 task_switch(selector_t* task_sel, int ty | Line 452 task_switch(selector_t* task_sel, int ty |
| if (!task16) { | if (!task16) { |
| if (task_sel->desc.u.seg.limit > iobase) { | if (task_sel->desc.u.seg.limit > iobase) { |
| CPU_STAT_IOLIMIT = task_sel->desc.u.seg.limit - iobase; | CPU_STAT_IOLIMIT = task_sel->desc.u.seg.limit - iobase; |
| CPU_STAT_IOLIMIT *= 8; /* ビット単位で保持しておく */ | |
| CPU_STAT_IOADDR = task_sel->desc.u.seg.segbase + iobase; | CPU_STAT_IOADDR = task_sel->desc.u.seg.segbase + iobase; |
| } else { | } else { |
| CPU_STAT_IOLIMIT = 0; | CPU_STAT_IOLIMIT = 0; |
| Line 445 task_switch(selector_t* task_sel, int ty | Line 459 task_switch(selector_t* task_sel, int ty |
| } else { | } else { |
| CPU_STAT_IOLIMIT = 0; | CPU_STAT_IOLIMIT = 0; |
| } | } |
| VERBOSE(("task_switch: ioaddr = %08x, limit = %08x", CPU_STAT_IOADDR, CPU_STAT_IOLIMIT)); | |
| /* out of range */ | /* out of range */ |
| if (CPU_EIP > CPU_STAT_CS_LIMIT) { | if (CPU_EIP > CPU_STAT_CS_LIMIT) { |