--- np2/i386c/ia32/task.c 2004/03/02 16:30:43 1.15 +++ np2/i386c/ia32/task.c 2005/03/12 12:32:54 1.20 @@ -1,4 +1,4 @@ -/* $Id: task.c,v 1.15 2004/03/02 16:30:43 monaka Exp $ */ +/* $Id: task.c,v 1.20 2005/03/12 12:32:54 monaka Exp $ */ /* * Copyright (c) 2003 NONAKA Kimihiro @@ -12,8 +12,6 @@ * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES @@ -37,6 +35,9 @@ load_tr(UINT16 selector) { selector_t task_sel; int rv; +#if defined(IA32_SUPPORT_DEBUG_REGISTER) + int i; +#endif UINT16 iobase; rv = parse_selector(&task_sel, selector); @@ -62,8 +63,7 @@ load_tr(UINT16 selector) default: EXCEPTION(GP_EXCEPTION, task_sel.idx); - iobase = 0; /* compiler happy */ - break; + return; } /* not present */ @@ -91,6 +91,17 @@ load_tr(UINT16 selector) } else { CPU_STAT_IOLIMIT = 0; } + +#if defined(IA32_SUPPORT_DEBUG_REGISTER) + /* clear local break point flags */ + CPU_DR7 &= ~(CPU_DR7_L(0)|CPU_DR7_L(1)|CPU_DR7_L(2)|CPU_DR7_L(3)|CPU_DR7_LE); + CPU_STAT_BP = 0; + for (i = 0; i < CPU_DEBUG_REG_INDEX_NUM; i++) { + if (CPU_DR7 & CPU_DR7_G(i)) { + CPU_STAT_BP |= (1 << i); + } + } +#endif } void @@ -151,11 +162,11 @@ task_switch(selector_t *task_sel, task_s UINT32 regs[CPU_REG_NUM]; UINT32 eip; UINT32 new_flags; - UINT32 mask; UINT32 cr3 = 0; UINT16 sreg[CPU_SEGREG_NUM]; UINT16 ldtr; - UINT16 t, iobase; + UINT16 iobase; + UINT16 t; selector_t cs_sel; int rv; @@ -164,7 +175,6 @@ task_switch(selector_t *task_sel, task_s UINT32 task_base; /* new task state */ UINT32 old_flags = REAL_EFLAGREG; BOOL task16; - UINT nsreg; UINT i; VERBOSE(("task_switch: start")); @@ -177,7 +187,6 @@ task_switch(selector_t *task_sel, task_s EXCEPTION(TS_EXCEPTION, task_sel->idx); } task16 = FALSE; - nsreg = CPU_SEGREG_NUM; break; case CPU_SYSDESC_TYPE_TSS_16: @@ -186,13 +195,11 @@ task_switch(selector_t *task_sel, task_s EXCEPTION(TS_EXCEPTION, task_sel->idx); } task16 = TRUE; - nsreg = CPU_SEGREG286_NUM; break; default: ia32_panic("task_switch: descriptor type is invalid."); task16 = FALSE; /* compiler happy */ - nsreg = CPU_SEGREG_NUM; /* compiler happy */ break; } @@ -216,8 +223,8 @@ task_switch(selector_t *task_sel, task_s if (CPU_STAT_PAGING) { /* task state paging check */ - paging_check(cur_base, CPU_TR_DESC.u.seg.limit, CPU_PAGE_WRITE_DATA, CPU_MODE_SUPERVISER); - paging_check(task_base, task_sel->desc.u.seg.limit, CPU_PAGE_WRITE_DATA, CPU_MODE_SUPERVISER); + paging_check(cur_base, CPU_TR_DESC.u.seg.limit, CPU_PAGE_WRITE_DATA|CPU_MODE_SUPERVISER); + paging_check(task_base, task_sel->desc.u.seg.limit, CPU_PAGE_WRITE_DATA|CPU_MODE_SUPERVISER); } /* load task state */ @@ -231,12 +238,14 @@ task_switch(selector_t *task_sel, task_s for (i = 0; i < CPU_REG_NUM; i++) { regs[i] = cpu_kmemoryread_d(task_base + 40 + i * 4); } - for (i = 0; i < nsreg; i++) { + for (i = 0; i < CPU_SEGREG_NUM; i++) { sreg[i] = cpu_kmemoryread_w(task_base + 72 + i * 4); } ldtr = cpu_kmemoryread_w(task_base + 96); t = cpu_kmemoryread_w(task_base + 100); - t &= 1; + if (t & 1) { + CPU_STAT_BP_EVENT |= CPU_STAT_BP_EVENT_TASK; + } iobase = cpu_kmemoryread_w(task_base + 102); } else { eip = cpu_kmemoryread_w(task_base + 14); @@ -244,24 +253,28 @@ task_switch(selector_t *task_sel, task_s for (i = 0; i < CPU_REG_NUM; i++) { regs[i] = cpu_kmemoryread_w(task_base + 18 + i * 2); } - for (i = 0; i < nsreg; i++) { + for (i = 0; i < CPU_SEGREG286_NUM; i++) { sreg[i] = cpu_kmemoryread_w(task_base + 34 + i * 2); } ldtr = cpu_kmemoryread_w(task_base + 42); - t = 0; iobase = 0; + t = 0; } #if defined(DEBUG) VERBOSE(("task_switch: current task")); + if (!task16) { + VERBOSE(("task_switch: CR3 = 0x%08x", CPU_CR3)); + } VERBOSE(("task_switch: eip = 0x%08x", CPU_EIP)); VERBOSE(("task_switch: eflags = 0x%08x", old_flags)); for (i = 0; i < CPU_REG_NUM; i++) { VERBOSE(("task_switch: regs[%d] = 0x%08x", i, CPU_REGS_DWORD(i))); } - for (i = 0; i < nsreg; i++) { + for (i = 0; i < CPU_SEGREG_NUM; i++) { VERBOSE(("task_switch: sreg[%d] = 0x%04x", i, CPU_REGS_SREG(i))); } + VERBOSE(("task_switch: ldtr = 0x%04x", CPU_LDTR)); VERBOSE(("task_switch: new task")); if (!task16) { @@ -272,7 +285,7 @@ task_switch(selector_t *task_sel, task_s for (i = 0; i < CPU_REG_NUM; i++) { VERBOSE(("task_switch: regs[%d] = 0x%08x", i, regs[i])); } - for (i = 0; i < nsreg; i++) { + for (i = 0; i < CPU_SEGREG_NUM; i++) { VERBOSE(("task_switch: sreg[%d] = 0x%04x", i, sreg[i])); } VERBOSE(("task_switch: ldtr = 0x%04x", ldtr)); @@ -311,7 +324,7 @@ task_switch(selector_t *task_sel, task_s for (i = 0; i < CPU_REG_NUM; i++) { cpu_kmemorywrite_d(cur_base + 40 + i * 4, CPU_REGS_DWORD(i)); } - for (i = 0; i < nsreg; i++) { + for (i = 0; i < CPU_SEGREG_NUM; i++) { cpu_kmemorywrite_w(cur_base + 72 + i * 4, CPU_REGS_SREG(i)); } } else { @@ -320,7 +333,7 @@ task_switch(selector_t *task_sel, task_s for (i = 0; i < CPU_REG_NUM; i++) { cpu_kmemorywrite_w(cur_base + 18 + i * 2, CPU_REGS_WORD(i)); } - for (i = 0; i < nsreg; i++) { + for (i = 0; i < CPU_SEGREG286_NUM; i++) { cpu_kmemorywrite_w(cur_base + 34 + i * 2, CPU_REGS_SREG(i)); } } @@ -336,6 +349,7 @@ task_switch(selector_t *task_sel, task_s } } #endif + /* set back link selector */ switch (type) { case TASK_SWITCH_CALL: @@ -400,6 +414,7 @@ task_switch(selector_t *task_sel, task_s /* set new EIP, GPR */ CPU_PREV_EIP = CPU_EIP = eip; + CPU_PREFETCH_CLEAR(); for (i = 0; i < CPU_REG_NUM; i++) { CPU_REGS_DWORD(i) = regs[i]; } @@ -409,8 +424,49 @@ task_switch(selector_t *task_sel, task_s } /* set new EFLAGS */ - mask = I_FLAG|IOPL_FLAG|RF_FLAG|VM_FLAG|VIF_FLAG|VIP_FLAG; - set_eflags(new_flags, mask); +#if defined(IA32_DONT_USE_SET_EFLAGS_FUNCTION) + CPU_EFLAG = new_flags; + CPU_OV = CPU_FLAG & O_FLAG; + CPU_TRAP = (CPU_FLAG & (I_FLAG|T_FLAG)) == (I_FLAG|T_FLAG); + if ((old_flags ^ CPU_EFLAG) & VM_FLAG) { + if (CPU_EFLAG & VM_FLAG) { + change_vm(1); + } else { + change_vm(0); + } + } +#else + set_eflags(new_flags, I_FLAG|IOPL_FLAG|RF_FLAG|VM_FLAG|VIF_FLAG|VIP_FLAG); +#endif + + /* I/O deny bitmap */ + if (!task16) { + if (iobase != 0 && iobase < task_sel->desc.u.seg.limit) { + CPU_STAT_IOLIMIT = (UINT16)(task_sel->desc.u.seg.limit - iobase); + CPU_STAT_IOADDR = task_sel->desc.u.seg.segbase + iobase; + } else { + CPU_STAT_IOLIMIT = 0; + } + } else { + CPU_STAT_IOLIMIT = 0; + } + VERBOSE(("task_switch: ioaddr = %08x, limit = %08x", CPU_STAT_IOADDR, CPU_STAT_IOLIMIT)); + +#if defined(IA32_SUPPORT_DEBUG_REGISTER) + /* check resume flag */ + if (CPU_EFLAG & RF_FLAG) { + CPU_STAT_BP_EVENT |= CPU_STAT_BP_EVENT_RF; + } + + /* clear local break point flags */ + CPU_DR7 &= ~(CPU_DR7_L(0)|CPU_DR7_L(1)|CPU_DR7_L(2)|CPU_DR7_L(3)|CPU_DR7_LE); + CPU_STAT_BP = 0; + for (i = 0; i < CPU_DEBUG_REG_INDEX_NUM; i++) { + if (CPU_DR7 & CPU_DR7_G(i)) { + CPU_STAT_BP |= (1 << i); + } + } +#endif /* load new LDTR */ load_ldtr(ldtr, TS_EXCEPTION); @@ -464,19 +520,6 @@ task_switch(selector_t *task_sel, task_s } } - /* I/O deny bitmap */ - if (!task16) { - if (iobase != 0 && iobase < task_sel->desc.u.seg.limit) { - CPU_STAT_IOLIMIT = (UINT16)(task_sel->desc.u.seg.limit - iobase); - CPU_STAT_IOADDR = task_sel->desc.u.seg.segbase + iobase; - } else { - CPU_STAT_IOLIMIT = 0; - } - } else { - CPU_STAT_IOLIMIT = 0; - } - VERBOSE(("task_switch: ioaddr = %08x, limit = %08x", CPU_STAT_IOADDR, CPU_STAT_IOLIMIT)); - /* out of range */ if (CPU_EIP > CPU_STAT_CS_LIMIT) { VERBOSE(("task_switch: new_ip is out of range. new_ip = %08x, limit = %08x", CPU_EIP, CPU_STAT_CS_LIMIT));