--- np2/i386c/ia32/task.c	2011/12/17 02:08:04	1.26
+++ np2/i386c/ia32/task.c	2012/01/08 07:48:22	1.32
@@ -32,7 +32,7 @@
 #define	TSS_32_SIZE	104
 #define	TSS_32_LIMIT	(TSS_32_SIZE - 1)
 
-static void
+static void CPUCALL
 set_task_busy(UINT16 selector)
 {
 	UINT32 addr;
@@ -48,7 +48,7 @@ set_task_busy(UINT16 selector)
 	}
 }
 
-static void
+static void CPUCALL
 set_task_free(UINT16 selector)
 {
 	UINT32 addr;
@@ -64,7 +64,7 @@ set_task_free(UINT16 selector)
 	}
 }
 
-void
+void CPUCALL
 load_tr(UINT16 selector)
 {
 	selector_t task_sel;
@@ -136,13 +136,13 @@ load_tr(UINT16 selector)
 #endif
 }
 
-void
+void CPUCALL
 get_stack_pointer_from_tss(UINT pl, UINT16 *new_ss, UINT32 *new_esp)
 {
 	UINT32 tss_stack_addr;
 
 	VERBOSE(("get_stack_pointer_from_tss: pl = %d", pl));
-	VERBOSE(("CPU_TR type = %d, base = 0x%08x, limit = 0x%08x", CPU_TR_DESC.type, CPU_TR_BASE, CPU_TR_LIMIT));
+	VERBOSE(("get_stack_pointer_from_tss: CPU_TR type = %d, base = 0x%08x, limit = 0x%08x", CPU_TR_DESC.type, CPU_TR_BASE, CPU_TR_LIMIT));
 
 	__ASSERT(pl < 3);
 
@@ -165,7 +165,7 @@ get_stack_pointer_from_tss(UINT pl, UINT
 	} else {
 		ia32_panic("get_stack_pointer_from_tss: task register is invalid (%d)\n", CPU_TR_DESC.type);
 	}
-	VERBOSE(("new stack pointer = %04x:%08x", *new_ss, *new_esp));
+	VERBOSE(("get_stack_pointer_from_tss: new stack pointer = %04x:%08x", *new_ss, *new_esp));
 }
 
 UINT16
@@ -190,7 +190,7 @@ get_backlink_selector_from_tss(void)
 	return backlink;
 }
 
-void
+void CPUCALL
 task_switch(selector_t *task_sel, task_switch_type_t type)
 {
 	UINT32 regs[CPU_REG_NUM];
@@ -436,7 +436,7 @@ task_switch(selector_t *task_sel, task_s
 	CPU_CR0 |= CPU_CR0_TS;
 
 	/*
-	 * load task state (CR3, EFLAG, EIP, GPR, segreg, LDTR)
+	 * load task state (CR3, EIP, GPR, segregs, LDTR, EFLAGS)
 	 */
 
 	/* set new CR3 */
@@ -444,16 +444,21 @@ task_switch(selector_t *task_sel, task_s
 		set_cr3(cr3);
 	}
 
-	/* set new EIP, GPR */
+	/* set new EIP, GPR, segregs */
 	CPU_EIP = eip;
 	for (i = 0; i < CPU_REG_NUM; i++) {
 		CPU_REGS_DWORD(i) = regs[i];
 	}
 	for (i = 0; i < CPU_SEGREG_NUM; i++) {
 		segdesc_init(i, sreg[i], &CPU_STAT_SREG(i));
+		/* invalidate segreg descriptor */
+		CPU_STAT_SREG(i).valid = 0;
 	}
 
+	CPU_CLEAR_PREV_ESP();
+
 	/* load new LDTR */
+	CPU_LDTR_DESC.valid = 0;
 	load_ldtr(ldtr, TS_EXCEPTION);
 
 	/* I/O deny bitmap */
@@ -485,11 +490,6 @@ task_switch(selector_t *task_sel, task_s
 
 	/* set new segment register */
 	if (!CPU_STAT_VM86) {
-		/* clear segment descriptor cache */
-		for (i = 0; i < CPU_SEGREG_NUM; i++) {
-			segdesc_clear(&CPU_STAT_SREG(i));
-		}
-
 		/* load CS */
 		rv = parse_selector(&cs_sel, sreg[CPU_CS_INDEX]);
 		if (rv < 0) {
@@ -547,22 +547,17 @@ task_switch(selector_t *task_sel, task_s
 			EXCEPTION(SS_EXCEPTION, ss_sel.idx);
 		}
 
-		/* Now loading CS/SS register */
-		load_cs(cs_sel.selector, &cs_sel.desc, cs_sel.rpl);
+		/* Now loading SS register */
 		load_ss(ss_sel.selector, &ss_sel.desc, cs_sel.rpl);
 
 		/* load ES, DS, FS, GS segment register */
-		for (i = 0; i < CPU_SEGREG_NUM; i++) {
-			if (i != CPU_CS_INDEX || i != CPU_SS_INDEX) {
-				LOAD_SEGREG1(i, sreg[i], TS_EXCEPTION);
-			}
-		}
-	}
+		LOAD_SEGREG1(CPU_ES_INDEX, sreg[CPU_ES_INDEX], TS_EXCEPTION);
+		LOAD_SEGREG1(CPU_DS_INDEX, sreg[CPU_DS_INDEX], TS_EXCEPTION);
+		LOAD_SEGREG1(CPU_FS_INDEX, sreg[CPU_FS_INDEX], TS_EXCEPTION);
+		LOAD_SEGREG1(CPU_GS_INDEX, sreg[CPU_GS_INDEX], TS_EXCEPTION);
 
-	/* out of range */
-	if (CPU_EIP > CPU_STAT_CS_LIMIT) {
-		VERBOSE(("task_switch: new_ip is out of range. new_ip = %08x, limit = %08x", CPU_EIP, CPU_STAT_CS_LIMIT));
-		EXCEPTION(GP_EXCEPTION, 0);
+		/* Now loading CS register */
+		load_cs(cs_sel.selector, &cs_sel.desc, cs_sel.rpl);
 	}
 
 	VERBOSE(("task_switch: done."));