np2/i386c/memory.c - diff

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Diff for /np2/i386c/memory.c between versions 1.5 and 1.10

version 1.5, 2003/12/26 03:41:05	version 1.10, 2004/02/20 16:09:04
Line 14	Line 14
BYTE mem[0x200000];	BYTE mem[0x200000];


#define USE_HIMEM	#define USE_HIMEM 0x110000

// ---- write byte	// ---- write byte

Line 25 static void MEMCALL i286_wt(UINT32 addre	Line 25 static void MEMCALL i286_wt(UINT32 addre

static void MEMCALL tram_wt(UINT32 address, REG8 value) {	static void MEMCALL tram_wt(UINT32 address, REG8 value) {

CPU_REMCLOCK -= vramop.tramwait;	CPU_REMCLOCK -= MEMWAIT_TRAM;
if (address < 0xa2000) {	if (address < 0xa2000) {
mem[address] = (BYTE)value;	mem[address] = (BYTE)value;
tramupdate[LOW12(address >> 1)] = 1;	tramupdate[LOW12(address >> 1)] = 1;
Line 57 static void MEMCALL tram_wt(UINT32 addre	Line 57 static void MEMCALL tram_wt(UINT32 addre

static void MEMCALL vram_w0(UINT32 address, REG8 value) {	static void MEMCALL vram_w0(UINT32 address, REG8 value) {

CPU_REMCLOCK -= vramop.vramwait;	CPU_REMCLOCK -= MEMWAIT_VRAM;
mem[address] = (BYTE)value;	mem[address] = (BYTE)value;
vramupdate[LOW15(address)] \|= 1;	vramupdate[LOW15(address)] \|= 1;
gdcs.grphdisp \|= 1;	gdcs.grphdisp \|= 1;
Line 65 static void MEMCALL vram_w0(UINT32 addre	Line 65 static void MEMCALL vram_w0(UINT32 addre

static void MEMCALL vram_w1(UINT32 address, REG8 value) {	static void MEMCALL vram_w1(UINT32 address, REG8 value) {

CPU_REMCLOCK -= vramop.vramwait;	CPU_REMCLOCK -= MEMWAIT_VRAM;
mem[address + VRAM_STEP] = (BYTE)value;	mem[address + VRAM_STEP] = (BYTE)value;
vramupdate[LOW15(address)] \|= 2;	vramupdate[LOW15(address)] \|= 2;
gdcs.grphdisp \|= 2;	gdcs.grphdisp \|= 2;
Line 76 static void MEMCALL grcg_rmw0(UINT32 add	Line 76 static void MEMCALL grcg_rmw0(UINT32 add
REG8 mask;	REG8 mask;
BYTE *vram;	BYTE *vram;

CPU_REMCLOCK -= vramop.grcgwait;	CPU_REMCLOCK -= MEMWAIT_GRCG;
mask = ~value;	mask = ~value;
address = LOW15(address);	address = LOW15(address);
vramupdate[address] \|= 1;	vramupdate[address] \|= 1;
Line 105 static void MEMCALL grcg_rmw1(UINT32 add	Line 105 static void MEMCALL grcg_rmw1(UINT32 add
REG8 mask;	REG8 mask;
BYTE *vram;	BYTE *vram;

CPU_REMCLOCK -= vramop.grcgwait;	CPU_REMCLOCK -= MEMWAIT_GRCG;
mask = ~value;	mask = ~value;
address = LOW15(address);	address = LOW15(address);
vramupdate[address] \|= 2;	vramupdate[address] \|= 2;
Line 133 static void MEMCALL grcg_tdw0(UINT32 add	Line 133 static void MEMCALL grcg_tdw0(UINT32 add

BYTE *vram;	BYTE *vram;

CPU_REMCLOCK -= vramop.grcgwait;	CPU_REMCLOCK -= MEMWAIT_GRCG;
address = LOW15(address);	address = LOW15(address);
vramupdate[address] \|= 1;	vramupdate[address] \|= 1;
gdcs.grphdisp \|= 1;	gdcs.grphdisp \|= 1;
Line 157 static void MEMCALL grcg_tdw1(UINT32 add	Line 157 static void MEMCALL grcg_tdw1(UINT32 add

BYTE *vram;	BYTE *vram;

CPU_REMCLOCK -= vramop.grcgwait;	CPU_REMCLOCK -= MEMWAIT_GRCG;
address = LOW15(address);	address = LOW15(address);
vramupdate[address] \|= 2;	vramupdate[address] \|= 2;
gdcs.grphdisp \|= 2;	gdcs.grphdisp \|= 2;
Line 179 static void MEMCALL grcg_tdw1(UINT32 add	Line 179 static void MEMCALL grcg_tdw1(UINT32 add

static void MEMCALL egc_wt(UINT32 address, REG8 value) {	static void MEMCALL egc_wt(UINT32 address, REG8 value) {

	CPU_REMCLOCK -= MEMWAIT_GRCG;
egc_write(address, value);	egc_write(address, value);
}	}

static void MEMCALL emmc_wt(UINT32 address, REG8 value) {	static void MEMCALL i286_wb(UINT32 address, REG8 value) {

extmem.pageptr[(address >> 14) & 3][LOW14(address)] = (BYTE)value;	mem[address + 0x1c8000 - 0xe8000] = (BYTE)value;
}	}

static void MEMCALL i286_wn(UINT32 address, REG8 value) {	static void MEMCALL i286_wn(UINT32 address, REG8 value) {
Line 203 static REG8 MEMCALL i286_rd(UINT32 addre	Line 204 static REG8 MEMCALL i286_rd(UINT32 addre

static REG8 MEMCALL tram_rd(UINT32 address) {	static REG8 MEMCALL tram_rd(UINT32 address) {

CPU_REMCLOCK -= vramop.tramwait;	CPU_REMCLOCK -= MEMWAIT_TRAM;
if (address < 0xa4000) {	if (address < 0xa4000) {
return(mem[address]);	return(mem[address]);
}	}
Line 220 static REG8 MEMCALL tram_rd(UINT32 addre	Line 221 static REG8 MEMCALL tram_rd(UINT32 addre

static REG8 MEMCALL vram_r0(UINT32 address) {	static REG8 MEMCALL vram_r0(UINT32 address) {

CPU_REMCLOCK -= vramop.vramwait;	CPU_REMCLOCK -= MEMWAIT_VRAM;
return(mem[address]);	return(mem[address]);
}	}

static REG8 MEMCALL vram_r1(UINT32 address) {	static REG8 MEMCALL vram_r1(UINT32 address) {

CPU_REMCLOCK -= vramop.vramwait;	CPU_REMCLOCK -= MEMWAIT_VRAM;
return(mem[address + VRAM_STEP]);	return(mem[address + VRAM_STEP]);
}	}

Line 235 static REG8 MEMCALL grcg_tcr0(UINT32 add	Line 236 static REG8 MEMCALL grcg_tcr0(UINT32 add
const BYTE *vram;	const BYTE *vram;
REG8 ret;	REG8 ret;

CPU_REMCLOCK -= vramop.grcgwait;	CPU_REMCLOCK -= MEMWAIT_GRCG;
vram = mem + LOW15(address);	vram = mem + LOW15(address);
ret = 0;	ret = 0;
if (!(grcg.modereg & 1)) {	if (!(grcg.modereg & 1)) {
Line 258 static REG8 MEMCALL grcg_tcr1(UINT32 add	Line 259 static REG8 MEMCALL grcg_tcr1(UINT32 add
const BYTE *vram;	const BYTE *vram;
REG8 ret;	REG8 ret;

CPU_REMCLOCK -= vramop.grcgwait;	CPU_REMCLOCK -= MEMWAIT_GRCG;
ret = 0;	ret = 0;
vram = mem + LOW15(address);	vram = mem + LOW15(address);
if (!(grcg.modereg & 1)) {	if (!(grcg.modereg & 1)) {
Line 278 const BYTE *vram;	Line 279 const BYTE *vram;

static REG8 MEMCALL egc_rd(UINT32 address) {	static REG8 MEMCALL egc_rd(UINT32 address) {

	CPU_REMCLOCK -= MEMWAIT_GRCG;
return(egc_read(address));	return(egc_read(address));
}	}

static REG8 MEMCALL emmc_rd(UINT32 address) {	static REG8 MEMCALL i286_rb(UINT32 address) {

return(extmem.pageptr[(address >> 14) & 3][LOW14(address)]);
}

static REG8 MEMCALL i286_itf(UINT32 address) {

if (CPU_ITFBANK) {	if (CPU_ITFBANK) {
address = ITF_ADRS + LOW15(address);	address += VRAM_STEP;
}	}
return(mem[address]);	return(mem[address]);
}	}
Line 307 static void MEMCALL i286w_wt(UINT32 addr	Line 304 static void MEMCALL i286w_wt(UINT32 addr

static void MEMCALL tramw_wt(UINT32 address, REG16 value) {	static void MEMCALL tramw_wt(UINT32 address, REG16 value) {

	CPU_REMCLOCK -= MEMWAIT_TRAM;
if (address < 0xa1fff) {	if (address < 0xa1fff) {
STOREINTELWORD(mem + address, value);	STOREINTELWORD(mem + address, value);
tramupdate[LOW12(address >> 1)] = 1;	tramupdate[LOW12(address >> 1)] = 1;
Line 352 static void MEMCALL tramw_wt(UINT32 addr	Line 350 static void MEMCALL tramw_wt(UINT32 addr


#define GRCGW_NON(page) { \	#define GRCGW_NON(page) { \
CPU_REMCLOCK -= vramop.vramwait; \	CPU_REMCLOCK -= MEMWAIT_VRAM; \
STOREINTELWORD(mem + address + VRAM_STEP*(page), value); \	STOREINTELWORD(mem + address + VRAM_STEP*(page), value); \
vramupdate[LOW15(address)] \|= (1 << page); \	vramupdate[LOW15(address)] \|= (1 << page); \
vramupdate[LOW15(address + 1)] \|= (1 << page); \	vramupdate[LOW15(address + 1)] \|= (1 << page); \
Line 361 static void MEMCALL tramw_wt(UINT32 addr	Line 359 static void MEMCALL tramw_wt(UINT32 addr

#define GRCGW_RMW(page) { \	#define GRCGW_RMW(page) { \
BYTE *vram; \	BYTE *vram; \
CPU_REMCLOCK -= vramop.grcgwait; \	CPU_REMCLOCK -= MEMWAIT_GRCG; \
address = LOW15(address); \	address = LOW15(address); \
vramupdate[address] \|= (1 << page); \	vramupdate[address] \|= (1 << page); \
vramupdate[address + 1] \|= (1 << page); \	vramupdate[address + 1] \|= (1 << page); \
Line 407 static void MEMCALL tramw_wt(UINT32 addr	Line 405 static void MEMCALL tramw_wt(UINT32 addr

#define GRCGW_TDW(page) { \	#define GRCGW_TDW(page) { \
BYTE *vram; \	BYTE *vram; \
CPU_REMCLOCK -= vramop.grcgwait; \	CPU_REMCLOCK -= MEMWAIT_GRCG; \
address = LOW15(address); \	address = LOW15(address); \
vramupdate[address] \|= (1 << page); \	vramupdate[address] \|= (1 << page); \
vramupdate[address + 1] \|= (1 << page); \	vramupdate[address + 1] \|= (1 << page); \
Line 441 static void MEMCALL grcgw_tdw1(UINT32 ad	Line 439 static void MEMCALL grcgw_tdw1(UINT32 ad

static void MEMCALL egcw_wt(UINT32 address, REG16 value) {	static void MEMCALL egcw_wt(UINT32 address, REG16 value) {

	CPU_REMCLOCK -= MEMWAIT_GRCG;
if (!(address & 1)) {	if (!(address & 1)) {
egc_write_w(address, value);	egc_write_w(address, value);
}	}
Line 456 static void MEMCALL egcw_wt(UINT32 addre	Line 455 static void MEMCALL egcw_wt(UINT32 addre
}	}
}	}

static void MEMCALL emmcw_wt(UINT32 address, REG16 value) {	static void MEMCALL i286w_wb(UINT32 address, REG16 value) {

BYTE *ptr;

if ((address & 0x3fff) != 0x3fff) {	mem[address + 0x1c8000 - 0xe8000] = (BYTE)value;
ptr = extmem.pageptr[(address >> 14) & 3] + LOW14(address);	mem[address + 0x1c8001 - 0xe8000] = (BYTE)(value >> 8);
STOREINTELWORD(ptr, value);
}
else {
extmem.pageptr[(address >> 14) & 3][0x3fff] = (BYTE)value;
extmem.pageptr[((address + 1) >> 14) & 3][0] = (BYTE)(value >> 8);
}
}	}

static void MEMCALL i286w_wn(UINT32 address, REG16 value) {	static void MEMCALL i286w_wn(UINT32 address, REG16 value) {
Line 489 static REG16 MEMCALL i286w_rd(UINT32 add	Line 480 static REG16 MEMCALL i286w_rd(UINT32 add

static REG16 MEMCALL tramw_rd(UINT32 address) {	static REG16 MEMCALL tramw_rd(UINT32 address) {

CPU_REMCLOCK -= vramop.tramwait;	CPU_REMCLOCK -= MEMWAIT_TRAM;
if (address < (0xa4000 - 1)) {	if (address < (0xa4000 - 1)) {
return(LOADINTELWORD(mem + address));	return(LOADINTELWORD(mem + address));
}	}
Line 518 static REG16 MEMCALL tramw_rd(UINT32 add	Line 509 static REG16 MEMCALL tramw_rd(UINT32 add

static REG16 MEMCALL vramw_r0(UINT32 address) {	static REG16 MEMCALL vramw_r0(UINT32 address) {

CPU_REMCLOCK -= vramop.vramwait;	CPU_REMCLOCK -= MEMWAIT_VRAM;
return(LOADINTELWORD(mem + address));	return(LOADINTELWORD(mem + address));
}	}

static REG16 MEMCALL vramw_r1(UINT32 address) {	static REG16 MEMCALL vramw_r1(UINT32 address) {

CPU_REMCLOCK -= vramop.vramwait;	CPU_REMCLOCK -= MEMWAIT_VRAM;
return(LOADINTELWORD(mem + address + VRAM_STEP));	return(LOADINTELWORD(mem + address + VRAM_STEP));
}	}

Line 533 static REG16 MEMCALL grcgw_tcr0(UINT32 a	Line 524 static REG16 MEMCALL grcgw_tcr0(UINT32 a
BYTE *vram;	BYTE *vram;
REG16 ret;	REG16 ret;

CPU_REMCLOCK -= vramop.grcgwait;	CPU_REMCLOCK -= MEMWAIT_GRCG;
ret = 0;	ret = 0;
vram = mem + LOW15(address);	vram = mem + LOW15(address);
if (!(grcg.modereg & 1)) {	if (!(grcg.modereg & 1)) {
Line 556 static REG16 MEMCALL grcgw_tcr1(UINT32 a	Line 547 static REG16 MEMCALL grcgw_tcr1(UINT32 a
BYTE *vram;	BYTE *vram;
REG16 ret;	REG16 ret;

CPU_REMCLOCK -= vramop.grcgwait;	CPU_REMCLOCK -= MEMWAIT_GRCG;
ret = 0;	ret = 0;
vram = mem + LOW15(address);	vram = mem + LOW15(address);
if (!(grcg.modereg & 1)) {	if (!(grcg.modereg & 1)) {
Line 578 static REG16 MEMCALL egcw_rd(UINT32 addr	Line 569 static REG16 MEMCALL egcw_rd(UINT32 addr

REG16 ret;	REG16 ret;

	CPU_REMCLOCK -= MEMWAIT_GRCG;
if (!(address & 1)) {	if (!(address & 1)) {
return(egc_read_w(address));	return(egc_read_w(address));
}	}
Line 595 static REG16 MEMCALL egcw_rd(UINT32 addr	Line 587 static REG16 MEMCALL egcw_rd(UINT32 addr
}	}
}	}

static REG16 MEMCALL emmcw_rd(UINT32 address) {	static REG16 MEMCALL i286w_rb(UINT32 address) {

const BYTE *ptr;
REG16 ret;

if ((address & 0x3fff) != 0x3fff) {
ptr = extmem.pageptr[(address >> 14) & 3] + LOW14(address);
return(LOADINTELWORD(ptr));
}
else {
ret = extmem.pageptr[(address >> 14) & 3][0x3fff];
ret += extmem.pageptr[((address + 1) >> 14) & 3][0] << 8;
return(ret);
}
}

static REG16 MEMCALL i286w_itf(UINT32 address) {

if (CPU_ITFBANK) {	if (CPU_ITFBANK) {
address = ITF_ADRS + LOW15(address);	address += VRAM_STEP;
}	}
return(LOADINTELWORD(mem + address));	return(LOADINTELWORD(mem + address));
}	}
Line 627 typedef REG8 (MEMCALL * MEM8READ)(UINT32	Line 603 typedef REG8 (MEMCALL * MEM8READ)(UINT32
typedef void (MEMCALL * MEM16WRITE)(UINT32 address, REG16 value);	typedef void (MEMCALL * MEM16WRITE)(UINT32 address, REG16 value);
typedef REG16 (MEMCALL * MEM16READ)(UINT32 address);	typedef REG16 (MEMCALL * MEM16READ)(UINT32 address);

static MEM8WRITE memory_write[] = {	typedef struct {
i286_wt, i286_wt, i286_wt, i286_wt, // 00	MEM8READ rd8[0x20];
i286_wt, i286_wt, i286_wt, i286_wt, // 20	MEM8WRITE wr8[0x20];
i286_wt, i286_wt, i286_wt, i286_wt, // 40	MEM16READ rd16[0x20];
i286_wt, i286_wt, i286_wt, i286_wt, // 60	MEM16WRITE wr16[0x20];
i286_wt, i286_wt, i286_wt, i286_wt, // 80	} MEMFN;
tram_wt, vram_w0, vram_w0, vram_w0, // a0
emmc_wt, emmc_wt, i286_wn, i286_wn, // c0	typedef struct {
vram_w0, i286_wn, i286_wn, i286_wn}; // e0	MEM8READ brd8;
	MEM8READ ird8;
	MEM8WRITE ewr8;
	MEM8WRITE bwr8;
	MEM16READ brd16;
	MEM16READ ird16;
	MEM16WRITE ewr16;
	MEM16WRITE bwr16;
	} MMAPTBL;

	typedef struct {
	MEM8READ rd8;
	MEM8WRITE wr8;
	MEM16READ rd16;
	MEM16WRITE wr16;
	} VACCTBL;

static MEM8READ memory_read[] = {	static MEMFN memfn = {
i286_rd, i286_rd, i286_rd, i286_rd, // 00	{i286_rd, i286_rd, i286_rd, i286_rd, // 00
i286_rd, i286_rd, i286_rd, i286_rd, // 20	i286_rd, i286_rd, i286_rd, i286_rd, // 20
i286_rd, i286_rd, i286_rd, i286_rd, // 40	i286_rd, i286_rd, i286_rd, i286_rd, // 40
i286_rd, i286_rd, i286_rd, i286_rd, // 60	i286_rd, i286_rd, i286_rd, i286_rd, // 60
i286_rd, i286_rd, i286_rd, i286_rd, // 80	i286_rd, i286_rd, i286_rd, i286_rd, // 80
tram_rd, vram_r0, vram_r0, vram_r0, // a0	tram_rd, vram_r0, vram_r0, vram_r0, // a0
emmc_rd, emmc_rd, i286_rd, i286_rd, // c0	i286_rd, i286_rd, i286_rd, i286_rd, // c0
vram_r0, i286_rd, i286_rd, i286_itf}; // f0	vram_r0, i286_rd, i286_rd, i286_rb}, // e0

static MEM16WRITE memword_write[] = {	{i286_wt, i286_wt, i286_wt, i286_wt, // 00
i286w_wt, i286w_wt, i286w_wt, i286w_wt, // 00	i286_wt, i286_wt, i286_wt, i286_wt, // 20
i286w_wt, i286w_wt, i286w_wt, i286w_wt, // 20	i286_wt, i286_wt, i286_wt, i286_wt, // 40
i286w_wt, i286w_wt, i286w_wt, i286w_wt, // 40	i286_wt, i286_wt, i286_wt, i286_wt, // 60
i286w_wt, i286w_wt, i286w_wt, i286w_wt, // 60	i286_wt, i286_wt, i286_wt, i286_wt, // 80
i286w_wt, i286w_wt, i286w_wt, i286w_wt, // 80	tram_wt, vram_w0, vram_w0, vram_w0, // a0
tramw_wt, vramw_w0, vramw_w0, vramw_w0, // a0	i286_wn, i286_wn, i286_wn, i286_wn, // c0
emmcw_wt, emmcw_wt, i286w_wn, i286w_wn, // c0	vram_w0, i286_wn, i286_wn, i286_wn}, // e0
vramw_w0, i286w_wn, i286w_wn, i286w_wn}; // e0

static MEM16READ memword_read[] = {	{i286w_rd, i286w_rd, i286w_rd, i286w_rd, // 00
i286w_rd, i286w_rd, i286w_rd, i286w_rd, // 00
i286w_rd, i286w_rd, i286w_rd, i286w_rd, // 20	i286w_rd, i286w_rd, i286w_rd, i286w_rd, // 20
i286w_rd, i286w_rd, i286w_rd, i286w_rd, // 40	i286w_rd, i286w_rd, i286w_rd, i286w_rd, // 40
i286w_rd, i286w_rd, i286w_rd, i286w_rd, // 60	i286w_rd, i286w_rd, i286w_rd, i286w_rd, // 60
i286w_rd, i286w_rd, i286w_rd, i286w_rd, // 80	i286w_rd, i286w_rd, i286w_rd, i286w_rd, // 80
tramw_rd, vramw_r0, vramw_r0, vramw_r0, // a0	tramw_rd, vramw_r0, vramw_r0, vramw_r0, // a0
emmcw_rd, emmcw_rd, i286w_rd, i286w_rd, // c0	i286w_rd, i286w_rd, i286w_rd, i286w_rd, // c0
vramw_r0, i286w_rd, i286w_rd, i286w_itf}; // e0	vramw_r0, i286w_rd, i286w_rd, i286w_rb}, // e0

static const MEM8WRITE vram_write[] = {	{i286w_wt, i286w_wt, i286w_wt, i286w_wt, // 00
vram_w0, vram_w1, vram_w0, vram_w1, // 00	i286w_wt, i286w_wt, i286w_wt, i286w_wt, // 20
vram_w0, vram_w1, vram_w0, vram_w1, // 40	i286w_wt, i286w_wt, i286w_wt, i286w_wt, // 40
grcg_tdw0, grcg_tdw1, egc_wt, egc_wt, // 80 tdw/tcr	i286w_wt, i286w_wt, i286w_wt, i286w_wt, // 60
grcg_rmw0, grcg_rmw1, egc_wt, egc_wt}; // c0 rmw	i286w_wt, i286w_wt, i286w_wt, i286w_wt, // 80
	tramw_wt, vramw_w0, vramw_w0, vramw_w0, // a0
static const MEM8READ vram_read[] = {	i286w_wn, i286w_wn, i286w_wn, i286w_wn, // c0
vram_r0, vram_r1, vram_r0, vram_r1, // 00	vramw_w0, i286w_wn, i286w_wn, i286w_wn}}; // e0
vram_r0, vram_r1, vram_r0, vram_r1, // 40
grcg_tcr0, grcg_tcr1, egc_rd, egc_rd, // 80 tdw/tcr	static const MMAPTBL mmaptbl[2] = {
vram_r0, vram_r1, egc_rd, egc_rd}; // c0 rmw	{i286_rd, i286_rb, i286_wn, i286_wn,
	i286w_rd, i286w_rb, i286w_wn, i286w_wn},
static const MEM16WRITE vramw_write[] = {	{i286_rb, i286_rb, i286_wt, i286_wb,
vramw_w0, vramw_w1, vramw_w0, vramw_w1, // 00	i286w_rb, i286w_rb, i286w_wt, i286w_wb}};
vramw_w0, vramw_w1, vramw_w0, vramw_w1, // 40
grcgw_tdw0, grcgw_tdw1, egcw_wt, egcw_wt, // 80 tdw/tcr	static const VACCTBL vacctbl[0x10] = {
grcgw_rmw0, grcgw_rmw1, egcw_wt, egcw_wt}; // c0 rmw	{vram_r0, vram_w0, vramw_r0, vramw_w0}, // 00
	{vram_r1, vram_w1, vramw_r1, vramw_w1},
static const MEM16READ vramw_read[] = {	{vram_r0, vram_w0, vramw_r0, vramw_w0},
vramw_r0, vramw_r1, vramw_r0, vramw_r1, // 00	{vram_r1, vram_w1, vramw_r1, vramw_w1},
vramw_r0, vramw_r1, vramw_r0, vramw_r1, // 40	{vram_r0, vram_w0, vramw_r0, vramw_w0}, // 40
grcgw_tcr0, grcgw_tcr1, egcw_rd, egcw_rd, // 80 tdw/tcr	{vram_r1, vram_w1, vramw_r1, vramw_w1},
vramw_r0, vramw_r1, egcw_rd, egcw_rd}; // c0 rmw	{vram_r0, vram_w0, vramw_r0, vramw_w0},
	{vram_r1, vram_w1, vramw_r1, vramw_w1},
	{grcg_tcr0, grcg_tdw0, grcgw_tcr0, grcgw_tdw0}, // 80 tdw/tcr
	{grcg_tcr1, grcg_tdw1, grcgw_tcr1, grcgw_tdw1},
	{egc_rd, egc_wt, egcw_rd, egcw_wt},
	{egc_rd, egc_wt, egcw_rd, egcw_wt},
	{vram_r0, grcg_rmw0, vramw_r0, grcgw_rmw0}, // c0 rmw
	{vram_r1, grcg_rmw1, vramw_r1, grcgw_rmw1},
	{egc_rd, egc_wt, egcw_rd, egcw_wt},
	{egc_rd, egc_wt, egcw_rd, egcw_wt}};


static REG8 MEMCALL i286_nonram_r(UINT32 address) {	static REG8 MEMCALL i286_nonram_r(UINT32 address) {
Line 704 static REG16 MEMCALL i286_nonram_rw(UINT	Line 702 static REG16 MEMCALL i286_nonram_rw(UINT
return(0xffff);	return(0xffff);
}	}


	void MEMCALL i286_memorymap(UINT type) {

	const MMAPTBL *mm;

	mm = mmaptbl + (type & 1);

	memfn.rd8[0xe8000 >> 15] = mm->brd8;
	memfn.rd8[0xf0000 >> 15] = mm->brd8;
	memfn.rd8[0xf8000 >> 15] = mm->ird8;

	memfn.wr8[0xd0000 >> 15] = mm->ewr8;
	memfn.wr8[0xd8000 >> 15] = mm->ewr8;
	memfn.wr8[0xe8000 >> 15] = mm->bwr8;
	memfn.wr8[0xf0000 >> 15] = mm->bwr8;
	memfn.wr8[0xf8000 >> 15] = mm->bwr8;

	memfn.rd16[0xe8000 >> 15] = mm->brd16;
	memfn.rd16[0xf0000 >> 15] = mm->brd16;
	memfn.rd16[0xf8000 >> 15] = mm->ird16;

	memfn.wr16[0xd0000 >> 15] = mm->ewr16;
	memfn.wr16[0xd8000 >> 15] = mm->ewr16;
	memfn.wr16[0xe8000 >> 15] = mm->bwr16;
	memfn.wr16[0xf0000 >> 15] = mm->bwr16;
	memfn.wr16[0xf8000 >> 15] = mm->bwr16;
	}

void MEMCALL i286_vram_dispatch(UINT func) {	void MEMCALL i286_vram_dispatch(UINT func) {

UINT proc;	const VACCTBL *vacc;

	vacc = vacctbl + (func & 0x0f);

proc = func & 0x0f;	memfn.rd8[0xa8000 >> 15] = vacc->rd8;
memory_write[0xa8000 >> 15] = vram_write[proc];	memfn.rd8[0xb0000 >> 15] = vacc->rd8;
memory_write[0xb0000 >> 15] = vram_write[proc];	memfn.rd8[0xb8000 >> 15] = vacc->rd8;
memory_write[0xb8000 >> 15] = vram_write[proc];	memfn.rd8[0xe0000 >> 15] = vacc->rd8;
memory_write[0xe0000 >> 15] = vram_write[proc];
	memfn.wr8[0xa8000 >> 15] = vacc->wr8;
memory_read[0xa8000 >> 15] = vram_read[proc];	memfn.wr8[0xb0000 >> 15] = vacc->wr8;
memory_read[0xb0000 >> 15] = vram_read[proc];	memfn.wr8[0xb8000 >> 15] = vacc->wr8;
memory_read[0xb8000 >> 15] = vram_read[proc];	memfn.wr8[0xe0000 >> 15] = vacc->wr8;
memory_read[0xe0000 >> 15] = vram_read[proc];
	memfn.rd16[0xa8000 >> 15] = vacc->rd16;
memword_write[0xa8000 >> 15] = vramw_write[proc];	memfn.rd16[0xb0000 >> 15] = vacc->rd16;
memword_write[0xb0000 >> 15] = vramw_write[proc];	memfn.rd16[0xb8000 >> 15] = vacc->rd16;
memword_write[0xb8000 >> 15] = vramw_write[proc];	memfn.rd16[0xe0000 >> 15] = vacc->rd16;
memword_write[0xe0000 >> 15] = vramw_write[proc];
	memfn.wr16[0xa8000 >> 15] = vacc->wr16;
memword_read[0xa8000 >> 15] = vramw_read[proc];	memfn.wr16[0xb0000 >> 15] = vacc->wr16;
memword_read[0xb0000 >> 15] = vramw_read[proc];	memfn.wr16[0xb8000 >> 15] = vacc->wr16;
memword_read[0xb8000 >> 15] = vramw_read[proc];	memfn.wr16[0xe0000 >> 15] = vacc->wr16;
memword_read[0xe0000 >> 15] = vramw_read[proc];
	if (!(func & 0x10)) { // digital
if (!(func & 0x10)) { // degital	memfn.wr8[0xe0000 >> 15] = i286_wn;
memory_write[0xe0000 >> 15] = i286_wn;	memfn.wr16[0xe0000 >> 15] = i286w_wn;
memword_write[0xe0000 >> 15] = i286w_wn;	memfn.rd8[0xe0000 >> 15] = i286_nonram_r;
memory_read[0xe0000 >> 15] = i286_nonram_r;	memfn.rd16[0xe0000 >> 15] = i286_nonram_rw;
memword_read[0xe0000 >> 15] = i286_nonram_rw;
}	}
#if defined(USE_ASM)
i286a_vram_dispatch(func);
#endif
}	}

REG8 MEMCALL __i286_memoryread(UINT32 address) {
	REG8 MEMCALL i286_memoryread(UINT32 paddr) {

	UINT32 address = paddr & CPU_ADRSMASK;

if (address < I286_MEMREADMAX) {	if (address < I286_MEMREADMAX) {
return(mem[address]);	return(mem[address]);
}	}
#if defined(USE_HIMEM)	else if (address >= USE_HIMEM) {
else if (address >= 0x10fff0) {
address -= 0x100000;	address -= 0x100000;
if (address < CPU_EXTMEMSIZE) {	if (address < CPU_EXTMEMSIZE) {
return(CPU_EXTMEM[address]);	return(CPU_EXTMEM[address]);
Line 755 REG8 MEMCALL __i286_memoryread(UINT32 ad	Line 781 REG8 MEMCALL __i286_memoryread(UINT32 ad
return(0xff);	return(0xff);
}	}
}	}
#endif
else {	else {
return(memory_read[(address >> 15) & 0x1f](address));	return(memfn.rd8[(address >> 15) & 0x1f](address));
}	}
}	}

REG16 MEMCALL __i286_memoryread_w(UINT32 address) {	REG16 MEMCALL i286_memoryread_w(UINT32 paddr) {

	UINT32 address = paddr & CPU_ADRSMASK;
REG16 ret;	REG16 ret;

if (address < (I286_MEMREADMAX - 1)) {	if (address < (I286_MEMREADMAX - 1)) {
return(LOADINTELWORD(mem + address));	return(LOADINTELWORD(mem + address));
}	}
#if defined(USE_HIMEM)	else if (address >= (USE_HIMEM - 1)) {
else if (address >= (0x10fff0 - 1)) {
address -= 0x100000;	address -= 0x100000;
if (address == (0x00fff0 - 1)) {	if (address == (USE_HIMEM - 0x100000 - 1)) {
ret = mem[0x100000 + address];	ret = mem[0x100000 + address];
}	}
else if (address < CPU_EXTMEMSIZE) {	else if (address < CPU_EXTMEMSIZE) {
Line 789 REG16 MEMCALL __i286_memoryread_w(UINT32	Line 814 REG16 MEMCALL __i286_memoryread_w(UINT32
}	}
return(ret);	return(ret);
}	}
#endif
else if ((address & 0x7fff) != 0x7fff) {	else if ((address & 0x7fff) != 0x7fff) {
return(memword_read[(address >> 15) & 0x1f](address));	return(memfn.rd16[(address >> 15) & 0x1f](address));
}	}
else {	else {
ret = memory_read[(address >> 15) & 0x1f](address);	ret = memfn.rd8[(address >> 15) & 0x1f](address);
address++;	address++;
ret += memory_read[(address >> 15) & 0x1f](address) << 8;	ret += (REG16)(memfn.rd8[(address >> 15) & 0x1f](address)) << 8;
return(ret);	return(ret);
}	}
}	}

UINT32 MEMCALL __i286_memoryread_d(UINT32 address) {	UINT32 MEMCALL i286_memoryread_d(UINT32 paddr) {

UINT32 ret;	UINT32 address = paddr & CPU_ADRSMASK;
	UINT32 adrs;
ret = __i286_memoryread_w(address);	UINT32 ret;
ret \|= (UINT32)__i286_memoryread_w(address + 2) << 16;

	if (address < (I286_MEMREADMAX - 3)) {
	return(LOADINTELDWORD(mem + address));
	}
	else if (address >= USE_HIMEM) {
	adrs = address - 0x100000;
	if (adrs + 3 < CPU_EXTMEMSIZE) {
	return(LOADINTELDWORD(CPU_EXTMEM + adrs));
	}
	}
	ret = i286_memoryread_w(address);
	ret += (UINT32)i286_memoryread_w(address + 2) << 16;
return ret;	return ret;
}	}

void MEMCALL __i286_memorywrite(UINT32 address, REG8 value) {	void MEMCALL i286_memorywrite(UINT32 paddr, REG8 value) {

	UINT32 address = paddr & CPU_ADRSMASK;

if (address < I286_MEMWRITEMAX) {	if (address < I286_MEMWRITEMAX) {
mem[address] = (BYTE)value;	mem[address] = (BYTE)value;
}	}
#if defined(USE_HIMEM)	else if (address >= USE_HIMEM) {
else if (address >= 0x10fff0) {
address -= 0x100000;	address -= 0x100000;
if (address < CPU_EXTMEMSIZE) {	if (address < CPU_EXTMEMSIZE) {
CPU_EXTMEM[address] = (BYTE)value;	CPU_EXTMEM[address] = (BYTE)value;
}	}
}	}
#endif
else {	else {
memory_write[(address >> 15) & 0x1f](address, value);	memfn.wr8[(address >> 15) & 0x1f](address, value);
}	}
}	}

void MEMCALL __i286_memorywrite_w(UINT32 address, REG16 value) {	void MEMCALL i286_memorywrite_w(UINT32 paddr, REG16 value) {

	UINT32 address = paddr & CPU_ADRSMASK;

if (address < (I286_MEMWRITEMAX - 1)) {	if (address < (I286_MEMWRITEMAX - 1)) {
STOREINTELWORD(mem + address, value);	STOREINTELWORD(mem + address, value);
}	}
#if defined(USE_HIMEM)	else if (address >= (USE_HIMEM - 1)) {
else if (address >= (0x10fff0 - 1)) {
address -= 0x100000;	address -= 0x100000;
if (address == (0x00fff0 - 1)) {	if (address == (USE_HIMEM - 0x100000 - 1)) {
mem[address] = (BYTE)value;	mem[address] = (BYTE)value;
}	}
else if (address < CPU_EXTMEMSIZE) {	else if (address < CPU_EXTMEMSIZE) {
Line 848 void MEMCALL __i286_memorywrite_w(UINT32	Line 883 void MEMCALL __i286_memorywrite_w(UINT32
CPU_EXTMEM[address] = (BYTE)(value >> 8);	CPU_EXTMEM[address] = (BYTE)(value >> 8);
}	}
}	}
#endif
else if ((address & 0x7fff) != 0x7fff) {	else if ((address & 0x7fff) != 0x7fff) {
memword_write[(address >> 15) & 0x1f](address, value);	memfn.wr16[(address >> 15) & 0x1f](address, value);
}	}
else {	else {
memory_write[(address >> 15) & 0x1f](address, (BYTE)value);	memfn.wr8[(address >> 15) & 0x1f](address, (BYTE)value);
address++;	address++;
memory_write[(address >> 15) & 0x1f](address, (BYTE)(value >> 8));	memfn.wr8[(address >> 15) & 0x1f](address, (BYTE)(value >> 8));
}	}
}	}

void MEMCALL __i286_memorywrite_d(UINT32 address, UINT32 value) {	void MEMCALL i286_memorywrite_d(UINT32 paddr, UINT32 value) {

__i286_memorywrite_w(address, value & 0xffff);	UINT32 address = paddr & CPU_ADRSMASK;
__i286_memorywrite_w(address + 2, (WORD)(value >> 16));	UINT32 adrs;

	if (address < (I286_MEMWRITEMAX - 3)) {
	STOREINTELDWORD(mem + address, value);
	return;
	}
	else if (address >= USE_HIMEM) {
	adrs = address - 0x100000;
	if (adrs + 3 < CPU_EXTMEMSIZE) {
	STOREINTELDWORD(CPU_EXTMEM + adrs, value);
	return;
	}
	}
	i286_memorywrite_w(address, value & 0xffff);
	i286_memorywrite_w(address + 2, (WORD)(value >> 16));
}	}

#if 0	#ifdef NP2_MEMORY_ASM
REG8 MEMCALL i286_membyte_read(UINT seg, UINT off) {	REG8 MEMCALL i286_membyte_read(UINT seg, UINT off) {

UINT32 address;	UINT32 address;
Line 917 void MEMCALL i286_memword_write(UINT seg	Line 965 void MEMCALL i286_memword_write(UINT seg
i286_memorywrite_w(address, value);	i286_memorywrite_w(address, value);
}	}
}	}
#endif	#endif /* NP2_MEMORY_ASM */

void MEMCALL i286_memstr_read(UINT seg, UINT off, void *dat, UINT leng) {	void MEMCALL i286_memstr_read(UINT seg, UINT off, void *dat, UINT leng) {

Line 957 void MEMCALL i286_memstr_read(UINT seg,	Line 1005 void MEMCALL i286_memstr_read(UINT seg,
}	}
}	}

void MEMCALL i286_memstr_write(UINT seg, UINT off,	void MEMCALL i286_memstr_write(UINT seg, UINT off, const void *dat, UINT leng) {
const void *dat, UINT leng) {

BYTE *out;	BYTE *out;
UINT32 adrs;	UINT32 adrs;
Line 1035 const BYTE *out;	Line 1082 const BYTE *out;
}	}
}	}
}	}

#endif	#endif

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