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| version 1.8, 2004/01/29 09:41:50 | version 1.10, 2004/01/30 01:29:13 |
|---|---|
| Line 20 static const UINT8 FDCCMD_TABLE[32] = { | Line 20 static const UINT8 FDCCMD_TABLE[32] = { |
| #define FDC_FORCEREADY (1) | #define FDC_FORCEREADY (1) |
| #define FDC_MAXDRIVE 2 | |
| #define FDC_DELAYERROR7 | #define FDC_DELAYERROR7 |
| Line 54 static BOOL fdc_isfdcinterrupt(void) { | Line 53 static BOOL fdc_isfdcinterrupt(void) { |
| REG8 DMACCALL fdc_dmafunc(REG8 func) { | REG8 DMACCALL fdc_dmafunc(REG8 func) { |
| TRACEOUT(("fdc_dmafunc = %d", func)); | // TRACEOUT(("fdc_dmafunc = %d", func)); |
| switch(func) { | switch(func) { |
| case DMAEXT_START: | case DMAEXT_START: |
| return(1); | return(1); |
| Line 239 static void FDC_SenseDeviceStatus(void) | Line 238 static void FDC_SenseDeviceStatus(void) |
| get_hdus(); | get_hdus(); |
| fdc.buf[0] = (fdc.hd << 2) | fdc.us; | fdc.buf[0] = (fdc.hd << 2) | fdc.us; |
| fdc.stat[fdc.us] = (fdc.hd << 2) | fdc.us; | fdc.stat[fdc.us] = (fdc.hd << 2) | fdc.us; |
| if (fdc.us < FDC_MAXDRIVE) { | if (fdc.equip & (1 << fdc.us)) { |
| fdc.buf[0] |= 0x08; | fdc.buf[0] |= 0x08; |
| if (!fdc.treg[fdc.us]) { | if (!fdc.treg[fdc.us]) { |
| fdc.buf[0] |= 0x10; | fdc.buf[0] |= 0x10; |
| Line 254 static void FDC_SenseDeviceStatus(void) | Line 253 static void FDC_SenseDeviceStatus(void) |
| else { | else { |
| fdc.buf[0] |= 0x80; | fdc.buf[0] |= 0x80; |
| } | } |
| TRACEOUT(("FDC_SenseDeviceStatus %.2x", fdc.buf[0])); | // TRACEOUT(("FDC_SenseDeviceStatus %.2x", fdc.buf[0])); |
| fdc.event = FDCEVENT_BUFSEND; | fdc.event = FDCEVENT_BUFSEND; |
| fdc.bufcnt = 1; | fdc.bufcnt = 1; |
| fdc.bufp = 0; | fdc.bufp = 0; |
| Line 403 static void FDC_Recalibrate(void) { | Line 402 static void FDC_Recalibrate(void) { |
| fdc.ncn = 0; | fdc.ncn = 0; |
| fdc.stat[fdc.us] = (fdc.hd << 2) | fdc.us; | fdc.stat[fdc.us] = (fdc.hd << 2) | fdc.us; |
| fdc.stat[fdc.us] |= FDCRLT_SE; | fdc.stat[fdc.us] |= FDCRLT_SE; |
| if (fdc.us >= FDC_MAXDRIVE) { | if (!(fdc.equip & (1 << fdc.us))) { |
| fdc.stat[fdc.us] |= FDCRLT_NR | FDCRLT_IC0; | fdc.stat[fdc.us] |= FDCRLT_NR | FDCRLT_IC0; |
| } | } |
| else if (!fddfile[fdc.us].fname[0]) { | else if (!fddfile[fdc.us].fname[0]) { |
| Line 435 static void FDC_SenceintStatus(void) { | Line 434 static void FDC_SenceintStatus(void) { |
| fdc.buf[1] = fdc.treg[fdc.us]; | fdc.buf[1] = fdc.treg[fdc.us]; |
| fdc.bufcnt = 2; | fdc.bufcnt = 2; |
| fdc.stat[fdc.us] = 0; | fdc.stat[fdc.us] = 0; |
| TRACEOUT(("fdc stat - %d [%.2x]", fdc.us, fdc.buf[0])); | // TRACEOUT(("fdc stat - %d [%.2x]", fdc.us, fdc.buf[0])); |
| } | } |
| else { | else { |
| for (; i<4; i++) { | for (; i<4; i++) { |
| Line 444 static void FDC_SenceintStatus(void) { | Line 443 static void FDC_SenceintStatus(void) { |
| fdc.buf[1] = fdc.treg[i]; | fdc.buf[1] = fdc.treg[i]; |
| fdc.bufcnt = 2; | fdc.bufcnt = 2; |
| fdc.stat[i] = 0; | fdc.stat[i] = 0; |
| TRACEOUT(("fdc stat - %d [%.2x]", i, fdc.buf[0])); | // TRACEOUT(("fdc stat - %d [%.2x]", i, fdc.buf[0])); |
| break; | break; |
| } | } |
| } | } |
| Line 553 static void FDC_Seek(void) { // cm | Line 552 static void FDC_Seek(void) { // cm |
| fdc.ncn = fdc.cmds[1]; | fdc.ncn = fdc.cmds[1]; |
| fdc.stat[fdc.us] = (fdc.hd << 2) | fdc.us; | fdc.stat[fdc.us] = (fdc.hd << 2) | fdc.us; |
| fdc.stat[fdc.us] |= FDCRLT_SE; | fdc.stat[fdc.us] |= FDCRLT_SE; |
| if ((fdc.us >= FDC_MAXDRIVE) || (!fddfile[fdc.us].fname[0])) { | if ((!(fdc.equip & (1 << fdc.us))) || |
| (!fddfile[fdc.us].fname[0])) { | |
| fdc.stat[fdc.us] |= FDCRLT_NR | FDCRLT_IC0; | fdc.stat[fdc.us] |= FDCRLT_NR | FDCRLT_IC0; |
| } | } |
| else { | else { |
| Line 712 REG8 DMACCALL fdc_dataread(void) { | Line 712 REG8 DMACCALL fdc_dataread(void) { |
| static void IOOUTCALL fdc_o92(UINT port, REG8 dat) { | static void IOOUTCALL fdc_o92(UINT port, REG8 dat) { |
| TRACEOUT(("fdc out %.2x %.2x [%.4x:%.4x]", port, dat, CPU_CS, CPU_IP)); | // TRACEOUT(("fdc out %.2x %.2x [%.4x:%.4x]", port, dat, CPU_CS, CPU_IP)); |
| if (((port >> 4) ^ fdc.chgreg) & 1) { | if (((port >> 4) ^ fdc.chgreg) & 1) { |
| return; | return; |
| Line 724 static void IOOUTCALL fdc_o92(UINT port, | Line 724 static void IOOUTCALL fdc_o92(UINT port, |
| static void IOOUTCALL fdc_o94(UINT port, REG8 dat) { | static void IOOUTCALL fdc_o94(UINT port, REG8 dat) { |
| TRACEOUT(("fdc out %.2x %.2x [%.4x:%.4x]", port, dat, CPU_CS, CPU_IP)); | // TRACEOUT(("fdc out %.2x %.2x [%.4x:%.4x]", port, dat, CPU_CS, CPU_IP)); |
| if (((port >> 4) ^ fdc.chgreg) & 1) { | if (((port >> 4) ^ fdc.chgreg) & 1) { |
| return; | return; |
| Line 739 static void IOOUTCALL fdc_o94(UINT port, | Line 739 static void IOOUTCALL fdc_o94(UINT port, |
| static REG8 IOINPCALL fdc_i90(UINT port) { | static REG8 IOINPCALL fdc_i90(UINT port) { |
| TRACEOUT(("fdc in %.2x %.2x [%.4x:%.4x]", port, fdc.status, | // TRACEOUT(("fdc in %.2x %.2x [%.4x:%.4x]", port, fdc.status, |
| CPU_CS, CPU_IP)); | // CPU_CS, CPU_IP)); |
| if (((port >> 4) ^ fdc.chgreg) & 1) { | if (((port >> 4) ^ fdc.chgreg) & 1) { |
| return(0xff); | return(0xff); |
| Line 762 static REG8 IOINPCALL fdc_i92(UINT port) | Line 762 static REG8 IOINPCALL fdc_i92(UINT port) |
| else { | else { |
| ret = fdc.lastdata; | ret = fdc.lastdata; |
| } | } |
| TRACEOUT(("fdc in %.2x %.2x [%.4x:%.4x]", port, ret, CPU_CS, CPU_IP)); | // TRACEOUT(("fdc in %.2x %.2x [%.4x:%.4x]", port, ret, CPU_CS, CPU_IP)); |
| return(ret); | return(ret); |
| } | } |
| Line 793 static REG8 IOINPCALL fdc_ibe(UINT port) | Line 793 static REG8 IOINPCALL fdc_ibe(UINT port) |
| return((fdc.chgreg & 3) | 8); | return((fdc.chgreg & 3) | 8); |
| } | } |
| static void IOOUTCALL fdc_o4be(UINT port, REG8 dat) { | |
| fdc.reg144 = dat; | |
| if (dat & 0x10) { | |
| fdc.rpm[(dat >> 5) & 3] = dat & 1; | |
| } | |
| (void)port; | |
| } | |
| static REG8 IOINPCALL fdc_i4be(UINT port) { | |
| (void)port; | |
| return(fdc.rpm[(fdc.reg144 >> 5) & 3] | 0xf0); | |
| } | |
| // ---- I/F | // ---- I/F |
| Line 806 static const IOINP fdcibe[1] = {fdc_ibe} | Line 821 static const IOINP fdcibe[1] = {fdc_ibe} |
| void fdc_reset(void) { | void fdc_reset(void) { |
| ZeroMemory(&fdc, sizeof(fdc)); | ZeroMemory(&fdc, sizeof(fdc)); |
| fdc.equip = np2cfg.fddequip; | |
| fdc.support144 = np2cfg.usefd144; | |
| fdcstatusreset(); | fdcstatusreset(); |
| dmac_attach(DMADEV_2HD, FDC_DMACH2HD); | dmac_attach(DMADEV_2HD, FDC_DMACH2HD); |
| dmac_attach(DMADEV_2DD, FDC_DMACH2DD); | dmac_attach(DMADEV_2DD, FDC_DMACH2DD); |
| Line 817 void fdc_bind(void) { | Line 834 void fdc_bind(void) { |
| iocore_attachcmnoutex(0x0090, 0x00f9, fdco90, 4); | iocore_attachcmnoutex(0x0090, 0x00f9, fdco90, 4); |
| iocore_attachcmninpex(0x0090, 0x00f9, fdci90, 4); | iocore_attachcmninpex(0x0090, 0x00f9, fdci90, 4); |
| // iocore_attachcmnoutex(0x00c8, 0x00f9, fdco90, 4); | iocore_attachcmnoutex(0x00c8, 0x00f9, fdco90, 4); |
| // iocore_attachcmninpex(0x00c8, 0x00f9, fdci90, 4); | iocore_attachcmninpex(0x00c8, 0x00f9, fdci90, 4); |
| if (fdc.support144) { | |
| iocore_attachout(0x04be, fdc_o4be); | |
| iocore_attachinp(0x04be, fdc_i4be); | |
| } | |
| iocore_attachsysoutex(0x00be, 0x0cff, fdcobe, 1); | iocore_attachsysoutex(0x00be, 0x0cff, fdcobe, 1); |
| iocore_attachsysinpex(0x00be, 0x0cff, fdcibe, 1); | iocore_attachsysinpex(0x00be, 0x0cff, fdcibe, 1); |
| } | } |