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| version 1.20, 2004/02/19 03:04:02 | version 1.23, 2004/02/26 08:44:32 |
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| Line 3 | Line 3 |
| #include "cpucore.h" | #include "cpucore.h" |
| #include "pccore.h" | #include "pccore.h" |
| #include "iocore.h" | #include "iocore.h" |
| #include "gdc_cmd.tbl" | |
| #include "gdc_sub.h" | |
| #include "vram.h" | #include "vram.h" |
| #include "palettes.h" | #include "palettes.h" |
| #include "gdc_cmd.tbl" | |
| #include "timing.h" | #include "timing.h" |
| Line 20 typedef struct { | Line 21 typedef struct { |
| UINT maxy; | UINT maxy; |
| } GDCCLK; | } GDCCLK; |
| // 31kHzの時の動作クロックが不明… | |
| static const GDCCLK gdcclk[] = { | static const GDCCLK gdcclk[] = { |
| {14318180 / 8, 112 - 8, 112 + 8, 200, 300}, | {14318180 / 8, 112 - 8, 112 + 8, 200, 300}, |
| {21052600 / 8, 106 - 6, 106 + 6, 400, 575}, | {21052600 / 8, 106 - 6, 106 + 6, 400, 575}, |
| {25056815 / 8, 106 - 6, 106 + 6, 400, 575}, | {25260000 / 8, 100 - 8, 100 + 8, 400, 575}}; |
| {25175000 / 8, 100 - 4, 100 + 4, 400, 575}}; | |
| static const UINT8 defdegpal[4] = {0x04,0x15,0x26,0x37}; | typedef struct { |
| UINT8 master[8]; | |
| UINT8 slave[8]; | |
| } GDCSYNC; | |
| static const UINT8 defsyncm15[8] = {0x10,0x4e,0x07,0x25,0x0d,0x0f,0xc8,0x94}; | static const UINT8 defsyncm15[8] = {0x10,0x4e,0x07,0x25,0x0d,0x0f,0xc8,0x94}; |
| static const UINT8 defsyncs15[8] = {0x06,0x26,0x03,0x11,0x86,0x0f,0xc8,0x94}; | static const UINT8 defsyncs15[8] = {0x06,0x26,0x03,0x11,0x86,0x0f,0xc8,0x94}; |
| Line 35 static const UINT8 defsyncs15[8] = {0x06 | Line 39 static const UINT8 defsyncs15[8] = {0x06 |
| static const UINT8 defsyncm24[8] = {0x10,0x4e,0x07,0x25,0x07,0x07,0x90,0x65}; | static const UINT8 defsyncm24[8] = {0x10,0x4e,0x07,0x25,0x07,0x07,0x90,0x65}; |
| static const UINT8 defsyncs24[8] = {0x06,0x26,0x03,0x11,0x83,0x07,0x90,0x65}; | static const UINT8 defsyncs24[8] = {0x06,0x26,0x03,0x11,0x83,0x07,0x90,0x65}; |
| static const UINT8 defsyncm31[8] = {0x10,0x4e,0x47,0x0c,0x07,0x0d,0x90,0x89}; | |
| static const UINT8 defsyncs31[8] = {0x06,0x26,0x41,0x0c,0x83,0x0d,0x90,0x89}; | |
| static const UINT8 defdegpal[4] = {0x04,0x15,0x26,0x37}; | |
| void gdc_setdegitalpal(int color, REG8 value) { | void gdc_setdegitalpal(int color, REG8 value) { |
| Line 113 void gdc_paletteinit(void) { | Line 125 void gdc_paletteinit(void) { |
| // -------------------------------------------------------------------------- | // -------------------------------------------------------------------------- |
| void gdc_vectreset(GDCDATA item) { | |
| item->para[GDC_VECTW+1] = 0x00; | |
| item->para[GDC_VECTW+2] = 0x00; | |
| item->para[GDC_VECTW+3] = 0x08; | |
| item->para[GDC_VECTW+4] = 0x00; | |
| item->para[GDC_VECTW+5] = 0x08; | |
| item->para[GDC_VECTW+6] = 0x00; | |
| item->para[GDC_VECTW+7] = 0xff; | |
| item->para[GDC_VECTW+8] = 0xff; | |
| item->para[GDC_VECTW+9] = 0xff; | |
| item->para[GDC_VECTW+10] = 0xff; | |
| } | |
| static void vectdraw(void) { | static void vectdraw(void) { |
| UINT32 csrw; | UINT32 csrw; |
| Line 137 const GDCVECT *vect; | Line 163 const GDCVECT *vect; |
| if (vect->ope & 0x40) { | if (vect->ope & 0x40) { |
| gdcsub_vectr(csrw, vect, textw, ope); | gdcsub_vectr(csrw, vect, textw, ope); |
| } | } |
| gdc_vectreset(&gdc.s); | |
| } | } |
| static void textdraw(void) { | static void textdraw(void) { |
| Line 164 const GDCVECT *vect; | Line 191 const GDCVECT *vect; |
| if (vect->ope & 0x40) { // undocumented | if (vect->ope & 0x40) { // undocumented |
| gdcsub_vectr(csrw, vect, textw, ope); | gdcsub_vectr(csrw, vect, textw, ope); |
| } | } |
| gdc_vectreset(&gdc.s); | |
| } | } |
| void gdc_work(int id) { | void gdc_work(int id) { |
| Line 264 void gdc_work(int id) { | Line 292 void gdc_work(int id) { |
| } | } |
| // BIOSとかで弄った時にリセット | // BIOSとかで弄った時にリセット |
| void gdc_forceready(GDCDATA item) { | void gdc_forceready(int id) { |
| GDCDATA item; | |
| item = (id == GDCWORK_MASTER)?&gdc.m:&gdc.s; | |
| if (item->cnt) { | |
| gdc_work(id); | |
| } | |
| item->rcv = 0; | item->rcv = 0; |
| item->snd = 0; | item->snd = 0; |
| } | } |
| Line 579 static void IOOUTCALL gdc_oa0(UINT port, | Line 612 static void IOOUTCALL gdc_oa0(UINT port, |
| if (gdc.s.cnt < GDCCMD_MAX) { | if (gdc.s.cnt < GDCCMD_MAX) { |
| gdc.s.fifo[gdc.s.cnt++] = dat; | gdc.s.fifo[gdc.s.cnt++] = dat; |
| } | } |
| // TRACEOUT(("GDC-B %.2x", dat)); | // TRACEOUT(("GDC-B %.2x [%.4x:%.4x]", dat, CPU_CS, CPU_IP)); |
| if (gdc.s.paracb) { | if (gdc.s.paracb) { |
| gdc_work(GDCWORK_SLAVE); | gdc_work(GDCWORK_SLAVE); |
| } | } |
| Line 683 static REG8 IOINPCALL gdc_ia0(UINT port) | Line 716 static REG8 IOINPCALL gdc_ia0(UINT port) |
| } | } |
| else { | else { |
| gdc_work(GDCWORK_SLAVE); | gdc_work(GDCWORK_SLAVE); |
| TRACEOUT(("gdc.s.cnt=%d", gdc.s.cnt)); | |
| } | } |
| #ifdef SEARCH_SYNC | #ifdef SEARCH_SYNC |
| if ((CPU_INPADRS) && (CPU_REMCLOCK >= 5)) { | if ((CPU_INPADRS) && (CPU_REMCLOCK >= 5)) { |
| Line 783 void gdc_reset(void) { | Line 815 void gdc_reset(void) { |
| CopyMemory(gdc.m.para + GDC_SYNC, defsyncm15, 8); | CopyMemory(gdc.m.para + GDC_SYNC, defsyncm15, 8); |
| CopyMemory(gdc.s.para + GDC_SYNC, defsyncs15, 8); | CopyMemory(gdc.s.para + GDC_SYNC, defsyncs15, 8); |
| } | } |
| gdc_vectreset(&gdc.m); | |
| gdc_vectreset(&gdc.s); | |
| gdc.clock = 0; | gdc.clock = 0; |
| gdc.m.para[GDC_PITCH] = 80; | gdc.m.para[GDC_PITCH] = 80; |