| version 1.24, 2004/02/29 00:57:06 | version 1.37, 2005/02/27 15:07:36 | 
| Line 9 | Line 9 | 
 | #include        "palettes.h" | #include        "palettes.h" | 
 | #include        "timing.h" | #include        "timing.h" | 
 |  |  | 
|  | #if !defined(CPUCORE_IA32) | 
 | #define SEARCH_SYNC | #define SEARCH_SYNC | 
 |  | #endif | 
 | #define TURE_SYNC | #define TURE_SYNC | 
 |  |  | 
 | typedef struct { | typedef struct { | 
| Line 44  static const UINT8 defsyncs31[8] = {0x06 | Line 45  static const UINT8 defsyncs31[8] = {0x06 | 
 |  |  | 
 |  |  | 
 | static const UINT8 defdegpal[4] = {0x04,0x15,0x26,0x37}; | static const UINT8 defdegpal[4] = {0x04,0x15,0x26,0x37}; | 
|  | static const UINT16 defanapal[16] = { | 
|  | 0x000,0x007,0x070,0x077,0x700,0x707,0x770,0x777, | 
|  | 0x444,0x00f,0x0f0,0x0ff,0xf00,0xf0f,0xff0,0xfff}; | 
 |  |  | 
 |  |  | 
 | void gdc_setdegitalpal(int color, REG8 value) { | void gdc_setdegitalpal(int color, REG8 value) { | 
| Line 70  void gdc_setdegitalpal(int color, REG8 v | Line 72  void gdc_setdegitalpal(int color, REG8 v | 
 | } | } | 
 | } | } | 
 |  |  | 
 |  | void gdc_setdegpalpack(int color, REG8 value) { | 
 |  |  | 
 |  | if ((gdc.degpal[color] ^ value) & 0x77) { | 
 |  | gdcs.palchange = GDCSCRN_REDRAW; | 
 |  | } | 
 |  | gdc.degpal[color] = (UINT8)value; | 
 |  | } | 
 |  |  | 
 | void gdc_setanalogpal(int color, int rgb, REG8 value) { | void gdc_setanalogpal(int color, int rgb, REG8 value) { | 
 |  |  | 
 | UINT8           *ptr; | UINT8           *ptr; | 
| Line 95  void gdc_setanalogpal(int color, int rgb | Line 105  void gdc_setanalogpal(int color, int rgb | 
 | *ptr = value; | *ptr = value; | 
 | } | } | 
 |  |  | 
| void gdc_setdegpalpack(int color, REG8 value) { | void gdc_setanalogpalall(const UINT16 *paltbl) { | 
 |  |  | 
| if ((gdc.degpal[color] ^ value) & 0x77) { | UINT    c; | 
| gdcs.palchange = GDCSCRN_REDRAW; | UINT    pal; | 
|  |  | 
|  | for (c=0; c<16; c++) { | 
|  | pal = *paltbl++; | 
|  | #if defined(SUPPORT_PC9821) | 
|  | gdc.anareg[(c * 3) + 0] = (pal >> 8) & 15; | 
|  | gdc.anareg[(c * 3) + 1] = (pal >> 4) & 15; | 
|  | gdc.anareg[(c * 3) + 2] = (pal >> 0) & 15; | 
|  | #endif | 
|  | gdc_setanalogpal(c, offsetof(RGB32, p.g), (REG8)((pal >> 8) & 15)); | 
|  | gdc_setanalogpal(c, offsetof(RGB32, p.r), (REG8)((pal >> 4) & 15)); | 
|  | gdc_setanalogpal(c, offsetof(RGB32, p.b), (REG8)((pal >> 0) & 15)); | 
 | } | } | 
 | gdc.degpal[color] = (UINT8)value; |  | 
 | } | } | 
 |  |  | 
 |  |  | 
 | void gdc_paletteinit(void) { | void gdc_paletteinit(void) { | 
 |  |  | 
 | int             c; | int             c; | 
| Line 122  void gdc_paletteinit(void) { | Line 143  void gdc_paletteinit(void) { | 
 | gdcs.palchange = GDCSCRN_REDRAW; | gdcs.palchange = GDCSCRN_REDRAW; | 
 | } | } | 
 |  |  | 
 |  | #if defined(SUPPORT_PC9821) | 
 |  | void gdc_analogext(BOOL extend) { | 
 |  |  | 
 |  | if (extend) { | 
 |  | gdc.analog |= (1 << GDCANALOG_256); | 
 |  | vramop.operate |= (1 << VOPBIT_VGA); | 
 |  | } | 
 |  | else { | 
 |  | gdc.analog &= ~(1 << (GDCANALOG_256)); | 
 |  | vramop.operate &= ~(1 << VOPBIT_VGA); | 
 |  | } | 
 |  | gdcs.palchange = GDCSCRN_REDRAW; | 
 |  | gdcs.grphdisp |= GDCSCRN_EXT | GDCSCRN_ALLDRAW2; | 
 |  | i286_vram_dispatch(vramop.operate); | 
 |  | } | 
 |  | #endif | 
 |  |  | 
 |  |  | 
 | // -------------------------------------------------------------------------- | // -------------------------------------------------------------------------- | 
 |  |  | 
| Line 366  const GDCCLK *clk; | Line 404  const GDCCLK *clk; | 
 | y = clk->maxy; | y = clk->maxy; | 
 | } | } | 
 | hclock = clk->clock / x; | hclock = clk->clock / x; | 
 |  | gdc.hclock = hclock; | 
 |  | gdc.vclock = hclock * 10 / y; | 
 | cnt = (pccore.baseclock * y) / hclock; | cnt = (pccore.baseclock * y) / hclock; | 
 | cnt *= pccore.multiple; | cnt *= pccore.multiple; | 
 | gdc.rasterclock = cnt / y; | gdc.rasterclock = cnt / y; | 
| Line 377  const GDCCLK *clk; | Line 417  const GDCCLK *clk; | 
 |  |  | 
 | void gdc_restorekacmode(void) { | void gdc_restorekacmode(void) { | 
 |  |  | 
| BYTE    bit; | UINT8   bit; | 
 |  |  | 
 | bit = (((!np2cfg.uPD72020) && (gdc.mode1 & 0x20))?0x00:0xff); | bit = (((!np2cfg.uPD72020) && (gdc.mode1 & 0x20))?0x00:0xff); | 
 | if (gdc.bitac != bit) { | if (gdc.bitac != bit) { | 
| Line 460  static void IOOUTCALL gdc_o6a(UINT port, | Line 500  static void IOOUTCALL gdc_o6a(UINT port, | 
 | switch(bit) { | switch(bit) { | 
 | case 0: | case 0: | 
 | if (gdc.display & (1 << GDCDISP_ANALOG)) { | if (gdc.display & (1 << GDCDISP_ANALOG)) { | 
| gdc.analog &= ~1; | gdc.analog &= ~(1 << GDCANALOG_16); | 
| gdc.analog |= dat; | gdc.analog |= (dat << GDCANALOG_16); | 
 | gdcs.palchange = GDCSCRN_REDRAW; | gdcs.palchange = GDCSCRN_REDRAW; | 
| vramop.operate &= VOP_ANALOGMASK; | vramop.operate &= ~(1 << VOPBIT_ANALOG); | 
| vramop.operate |= dat << 4; | vramop.operate |= dat << VOPBIT_ANALOG; | 
 | i286_vram_dispatch(vramop.operate); | i286_vram_dispatch(vramop.operate); | 
 | } | } | 
 | break; | break; | 
 |  |  | 
 | case 2: | case 2: | 
 | if ((gdc.mode2 & 0x08) && (grcg.chip == 3)) { | if ((gdc.mode2 & 0x08) && (grcg.chip == 3)) { | 
| vramop.operate &= VOP_EGCMASK; | vramop.operate &= ~(1 << VOPBIT_EGC); | 
| vramop.operate |= dat << 1; | vramop.operate |= dat << VOPBIT_EGC; | 
 | i286_vram_dispatch(vramop.operate); | i286_vram_dispatch(vramop.operate); | 
 | } | } | 
 | break; | break; | 
| Line 481  static void IOOUTCALL gdc_o6a(UINT port, | Line 521  static void IOOUTCALL gdc_o6a(UINT port, | 
 | } | } | 
 | else { | else { | 
 | switch(dat) { | switch(dat) { | 
 |  | #if defined(SUPPORT_PC9821) | 
 |  | case 0x20: | 
 |  | if (gdc.mode2 & 0x08) { | 
 |  | gdc_analogext(FALSE); | 
 |  | } | 
 |  | break; | 
 |  |  | 
 |  | case 0x21: | 
 |  | if (gdc.mode2 & 0x08) { | 
 |  | gdc_analogext(TRUE); | 
 |  | } | 
 |  | break; | 
 |  |  | 
 |  | case 0x68: | 
 |  | gdc.analog &= ~(1 << GDCANALOG_256E); | 
 |  | break; | 
 |  |  | 
 |  | case 0x69: | 
 |  | gdc.analog |= (1 << GDCANALOG_256E); | 
 |  | break; | 
 |  | #endif | 
 | case 0x40: | case 0x40: | 
 | case 0x80:                                      // EPSON? | case 0x80:                                      // EPSON? | 
 | gdc.display &= ~(1 << GDCDISP_PLAZMA); | gdc.display &= ~(1 << GDCDISP_PLAZMA); | 
| Line 557  static REG8 IOINPCALL gdc_i60(UINT port) | Line 618  static REG8 IOINPCALL gdc_i60(UINT port) | 
 | else { | else { | 
 | gdc_work(GDCWORK_MASTER); | gdc_work(GDCWORK_MASTER); | 
 | } | } | 
| #ifdef SEARCH_SYNC | #ifdef SEARCH_SYNC              // ToDo: フェッチキューを参照するように… | 
 | if ((CPU_INPADRS) && (CPU_REMCLOCK >= 5)) { | if ((CPU_INPADRS) && (CPU_REMCLOCK >= 5)) { | 
| UINT16 jadr = 0xfa74; | UINT32 addr; | 
|  | UINT16 jadr; | 
 | UINT16 memv; | UINT16 memv; | 
| memv = i286_memoryread_w(CPU_INPADRS); | addr = CPU_INPADRS; | 
|  | jadr = 0xfa74; | 
|  | memv = i286_memoryread_w(addr); | 
 | while((memv == 0x00eb) || (memv == 0x5fe6)) { | while((memv == 0x00eb) || (memv == 0x5fe6)) { | 
 | jadr -= 0x200; | jadr -= 0x200; | 
| CPU_INPADRS += 2; | addr += 2; | 
| memv = i286_memoryread_w(CPU_INPADRS); | memv = i286_memoryread_w(addr); | 
 | } | } | 
 | if ((memv == 0x20a8) || (memv == 0x2024)) { | if ((memv == 0x20a8) || (memv == 0x2024)) { | 
| memv = i286_memoryread_w(CPU_INPADRS + 2); | memv = i286_memoryread_w(addr + 2); | 
 | if (memv == jadr) {                                     // je | if (memv == jadr) {                                     // je | 
 | if (!gdc.vsync) { | if (!gdc.vsync) { | 
 | CPU_REMCLOCK = -1; | CPU_REMCLOCK = -1; | 
| Line 649  static void IOOUTCALL gdc_oa4(UINT port, | Line 713  static void IOOUTCALL gdc_oa4(UINT port, | 
 |  |  | 
 | static void IOOUTCALL gdc_oa6(UINT port, REG8 dat) { | static void IOOUTCALL gdc_oa6(UINT port, REG8 dat) { | 
 |  |  | 
| if ((gdcs.access ^ dat) & 1) { | dat = dat & 1; | 
| gdcs.access = dat & 1; | if (gdcs.access != dat) { | 
| vramop.operate &= VOP_ACCESSMASK; | gdcs.access = (UINT8)dat; | 
| vramop.operate |= gdcs.access; | vramop.operate &= ~(1 << VOPBIT_ACCESS); | 
|  | vramop.operate |= dat << VOPBIT_ACCESS; | 
 | i286_vram_dispatch(vramop.operate); | i286_vram_dispatch(vramop.operate); | 
 | } | } | 
 | (void)port; | (void)port; | 
| Line 684  static REG8 IOINPCALL gdc_ia0(UINT port) | Line 749  static REG8 IOINPCALL gdc_ia0(UINT port) | 
 | } | } | 
 | #ifdef SEARCH_SYNC | #ifdef SEARCH_SYNC | 
 | if ((CPU_INPADRS) && (CPU_REMCLOCK >= 5)) { | if ((CPU_INPADRS) && (CPU_REMCLOCK >= 5)) { | 
| UINT16 jadr = 0xfa74; | UINT32 addr; | 
|  | UINT16 jadr; | 
 | UINT16 memv; | UINT16 memv; | 
| memv = i286_memoryread_w(CPU_INPADRS); | addr = CPU_INPADRS; | 
|  | jadr = 0xfa74; | 
|  | memv = i286_memoryread_w(addr); | 
 | while((memv == 0x00eb) || (memv == 0x5fe6)) { | while((memv == 0x00eb) || (memv == 0x5fe6)) { | 
 | jadr -= 0x200; | jadr -= 0x200; | 
| CPU_INPADRS += 2; | addr += 2; | 
| memv = i286_memoryread_w(CPU_INPADRS); | memv = i286_memoryread_w(addr); | 
 | } | } | 
 | if ((memv == 0x20a8) || (memv == 0x2024)) { | if ((memv == 0x20a8) || (memv == 0x2024)) { | 
| memv = i286_memoryread_w(CPU_INPADRS + 2); | memv = i286_memoryread_w(addr + 2); | 
 | if (memv == jadr) {                                     // je | if (memv == jadr) {                                     // je | 
 | if (!gdc.vsync) { | if (!gdc.vsync) { | 
 | CPU_REMCLOCK = -1; | CPU_REMCLOCK = -1; | 
| Line 743  static REG8 IOINPCALL gdc_ia6(UINT port) | Line 811  static REG8 IOINPCALL gdc_ia6(UINT port) | 
 |  |  | 
 | static void IOOUTCALL gdc_oa8(UINT port, REG8 dat) { | static void IOOUTCALL gdc_oa8(UINT port, REG8 dat) { | 
 |  |  | 
| if (gdc.analog) { | if (gdc.analog & ((1 << GDCANALOG_256) + (1 << GDCANALOG_16))) { | 
 | gdc.palnum = dat; | gdc.palnum = dat; | 
 | } | } | 
 | else { | else { | 
| Line 754  static void IOOUTCALL gdc_oa8(UINT port, | Line 822  static void IOOUTCALL gdc_oa8(UINT port, | 
 |  |  | 
 | static void IOOUTCALL gdc_oaa(UINT port, REG8 dat) { | static void IOOUTCALL gdc_oaa(UINT port, REG8 dat) { | 
 |  |  | 
| if (gdc.analog) { | #if defined(SUPPORT_PC9821) | 
|  | if (gdc.analog & (1 << GDCANALOG_256)) { | 
|  | gdcs.palchange = GDCSCRN_REDRAW; | 
|  | gdc.anareg[(16 * 3) + (gdc.palnum * 4) + 0] = dat; | 
|  | } | 
|  | else | 
|  | #endif | 
|  | if (gdc.analog & (1 << GDCANALOG_16)) { | 
|  | #if defined(SUPPORT_PC9821) | 
|  | gdc.anareg[(gdc.palnum * 3) + 0] = dat; | 
|  | #endif | 
 | gdc_setanalogpal(gdc.palnum & 15, offsetof(RGB32, p.g), dat); | gdc_setanalogpal(gdc.palnum & 15, offsetof(RGB32, p.g), dat); | 
 | } | } | 
 | else { | else { | 
| Line 765  static void IOOUTCALL gdc_oaa(UINT port, | Line 843  static void IOOUTCALL gdc_oaa(UINT port, | 
 |  |  | 
 | static void IOOUTCALL gdc_oac(UINT port, REG8 dat) { | static void IOOUTCALL gdc_oac(UINT port, REG8 dat) { | 
 |  |  | 
| if (gdc.analog) { | #if defined(SUPPORT_PC9821) | 
|  | if (gdc.analog & (1 << GDCANALOG_256)) { | 
|  | gdcs.palchange = GDCSCRN_REDRAW; | 
|  | gdc.anareg[(16 * 3) + (gdc.palnum * 4) + 1] = dat; | 
|  | } | 
|  | else | 
|  | #endif | 
|  | if (gdc.analog & (1 << GDCANALOG_16)) { | 
|  | #if defined(SUPPORT_PC9821) | 
|  | gdc.anareg[(gdc.palnum * 3) + 1] = dat; | 
|  | #endif | 
 | gdc_setanalogpal(gdc.palnum & 15, offsetof(RGB32, p.r), dat); | gdc_setanalogpal(gdc.palnum & 15, offsetof(RGB32, p.r), dat); | 
 | } | } | 
 | else { | else { | 
| Line 776  static void IOOUTCALL gdc_oac(UINT port, | Line 864  static void IOOUTCALL gdc_oac(UINT port, | 
 |  |  | 
 | static void IOOUTCALL gdc_oae(UINT port, REG8 dat) { | static void IOOUTCALL gdc_oae(UINT port, REG8 dat) { | 
 |  |  | 
| if (gdc.analog) { | #if defined(SUPPORT_PC9821) | 
|  | if (gdc.analog & (1 << GDCANALOG_256)) { | 
|  | gdcs.palchange = GDCSCRN_REDRAW; | 
|  | gdc.anareg[(16 * 3) + (gdc.palnum * 4) + 2] = dat; | 
|  | } | 
|  | else | 
|  | #endif | 
|  | if (gdc.analog & (1 << GDCANALOG_16)) { | 
|  | #if defined(SUPPORT_PC9821) | 
|  | gdc.anareg[(gdc.palnum * 3) + 2] = dat; | 
|  | #endif | 
 | gdc_setanalogpal(gdc.palnum & 15, offsetof(RGB32, p.b), dat); | gdc_setanalogpal(gdc.palnum & 15, offsetof(RGB32, p.b), dat); | 
 | } | } | 
 | else { | else { | 
| Line 785  static void IOOUTCALL gdc_oae(UINT port, | Line 883  static void IOOUTCALL gdc_oae(UINT port, | 
 | (void)port; | (void)port; | 
 | } | } | 
 |  |  | 
 |  | #if defined(SUPPORT_PC9821) | 
 |  | static REG8 IOINPCALL gdc_ia8(UINT port) { | 
 |  |  | 
 |  | if (gdc.analog & ((1 << GDCANALOG_256) + (1 << GDCANALOG_16))) { | 
 |  | return(gdc.palnum); | 
 |  | } | 
 |  | (void)port; | 
 |  | return(gdc.degpal[3]); | 
 |  | } | 
 |  |  | 
 |  | static REG8 IOINPCALL gdc_iaa(UINT port) { | 
 |  |  | 
 |  | if (gdc.analog & (1 << GDCANALOG_256)) { | 
 |  | return(gdc.anareg[(16 * 3) + (gdc.palnum * 4) + 0]); | 
 |  | } | 
 |  | if (gdc.analog & (1 << GDCANALOG_16)) { | 
 |  | return(gdc.anareg[(gdc.palnum * 3) + 0]); | 
 |  | } | 
 |  | (void)port; | 
 |  | return(gdc.degpal[1]); | 
 |  | } | 
 |  |  | 
 |  | static REG8 IOINPCALL gdc_iac(UINT port) { | 
 |  |  | 
 |  | if (gdc.analog & (1 << GDCANALOG_256)) { | 
 |  | return(gdc.anareg[(16 * 3) + (gdc.palnum * 4) + 1]); | 
 |  | } | 
 |  | if (gdc.analog & (1 << GDCANALOG_16)) { | 
 |  | return(gdc.anareg[(gdc.palnum * 3) + 1]); | 
 |  | } | 
 |  | (void)port; | 
 |  | return(gdc.degpal[2]); | 
 |  | } | 
 |  |  | 
 |  | static REG8 IOINPCALL gdc_iae(UINT port) { | 
 |  |  | 
 |  | if (gdc.analog & (1 << GDCANALOG_256)) { | 
 |  | return(gdc.anareg[(16 * 3) + (gdc.palnum * 4) + 2]); | 
 |  | } | 
 |  | if (gdc.analog & (1 << GDCANALOG_16)) { | 
 |  | return(gdc.anareg[(gdc.palnum * 3) + 2]); | 
 |  | } | 
 |  | (void)port; | 
 |  | return(gdc.degpal[0]); | 
 |  | } | 
 |  | #endif | 
 |  |  | 
 |  |  | 
 | // ---- extend | // ---- extend | 
 |  |  | 
 |  | #if defined(SUPPORT_PC9821) | 
 |  | static void IOOUTCALL gdc_o9a0(UINT port, REG8 dat) { | 
 |  |  | 
 |  | gdc.ff2 = dat; | 
 |  | (void)port; | 
 |  | } | 
 |  |  | 
 |  | static REG8 IOINPCALL gdc_i9a0(UINT port) { | 
 |  |  | 
 |  | REG8    ret; | 
 |  |  | 
 |  | ret = 0; | 
 |  | switch(gdc.ff2) { | 
 |  | case 0x00: | 
 |  | ret = 0xff; | 
 |  | break; | 
 |  |  | 
 |  | case 0x01: | 
 |  | ret = (gdc.mode1 >> 1) & 1; | 
 |  | break; | 
 |  |  | 
 |  | case 0x02: | 
 |  | ret = (gdc.mode1 >> 4) & 1; | 
 |  | break; | 
 |  |  | 
 |  | case 0x03: | 
 |  | ret = (gdc.mode1 >> 7) & 1; | 
 |  | break; | 
 |  |  | 
 |  | case 0x04: | 
 |  | ret = (gdc.mode2 >> 0) & 1; | 
 |  | break; | 
 |  |  | 
 |  | case 0x05: | 
 |  | ret = (gdc.display >> GDCDISP_PLAZMA) & 1; | 
 |  | break; | 
 |  |  | 
 |  | case 0x07: | 
 |  | ret = (gdc.mode2 >> 2) & 1; | 
 |  | break; | 
 |  |  | 
 |  | case 0x08: | 
 |  | ret = (gdc.mode2 >> 3) & 1; | 
 |  | break; | 
 |  |  | 
 |  | case 0x09: | 
 |  | ret = (gdc.clock >> 0) & 1; | 
 |  | break; | 
 |  |  | 
 |  | case 0x0a: | 
 |  | ret = (gdc.analog >> GDCANALOG_256) & 1; | 
 |  | break; | 
 |  |  | 
 |  | case 0x0b: | 
 |  | ret = 1; | 
 |  | break; | 
 |  |  | 
 |  | case 0x0d: | 
 |  | ret = (gdc.analog >> GDCANALOG_256E) & 1; | 
 |  | break; | 
 |  | } | 
 |  | ret |= (gdc.clock & 2); | 
 |  | (void)port; | 
 |  | return(ret); | 
 |  | } | 
 |  | #endif | 
 |  |  | 
 | #if defined(SUPPORT_CRT31KHZ) | #if defined(SUPPORT_CRT31KHZ) | 
 | static void IOOUTCALL gdc_o9a8(UINT port, REG8 dat) { | static void IOOUTCALL gdc_o9a8(UINT port, REG8 dat) { | 
 |  |  | 
| Line 820  static const IOINP gdci60[8] = { | Line 1032  static const IOINP gdci60[8] = { | 
 | gdc_i60,        gdc_i62,        NULL,           NULL, | gdc_i60,        gdc_i62,        NULL,           NULL, | 
 | gdc_i68,        gdc_i6a,        NULL,           NULL}; | gdc_i68,        gdc_i6a,        NULL,           NULL}; | 
 |  |  | 
 |  | #if defined(SUPPORT_PC9821) | 
 |  | static const IOINP gdcia0[8] = { | 
 |  | gdc_ia0,        gdc_ia2,        gdc_ia4,        gdc_ia6, | 
 |  | gdc_ia8,        gdc_iaa,        gdc_iac,        gdc_iae}; | 
 |  | #else | 
 | static const IOINP gdcia0[8] = { | static const IOINP gdcia0[8] = { | 
 | gdc_ia0,        gdc_ia2,        gdc_ia4,        gdc_ia6, | gdc_ia0,        gdc_ia2,        gdc_ia4,        gdc_ia6, | 
 | NULL,           NULL,           NULL,           NULL}; | NULL,           NULL,           NULL,           NULL}; | 
 |  | #endif | 
 |  |  | 
 |  |  | 
| void gdc_reset(void) { | void gdc_biosreset(void) { | 
 |  |  | 
| ZeroMemory(&gdc, sizeof(gdc)); | #if defined(SUPPORT_PC9821) | 
| ZeroMemory(&gdcs, sizeof(gdcs)); | UINT    i; | 
|  | UINT    j; | 
|  | UINT8   tmp; | 
|  | UINT8   *pal; | 
|  | #endif | 
 |  |  | 
 | if (!(np2cfg.dipsw[0] & 0x01)) { | if (!(np2cfg.dipsw[0] & 0x01)) { | 
 | gdc.mode1 = 0x98; | gdc.mode1 = 0x98; | 
| Line 848  void gdc_reset(void) { | Line 1070  void gdc_reset(void) { | 
 | CopyMemory(gdc.m.para + GDC_SYNC, defsyncm15, 8); | CopyMemory(gdc.m.para + GDC_SYNC, defsyncm15, 8); | 
 | CopyMemory(gdc.s.para + GDC_SYNC, defsyncs15, 8); | CopyMemory(gdc.s.para + GDC_SYNC, defsyncs15, 8); | 
 | } | } | 
 |  | if (np2cfg.dipsw[0] & 0x80) { | 
 |  | gdc.s.para[GDC_SYNC] = 0x16; | 
 |  | } | 
 | gdc_vectreset(&gdc.m); | gdc_vectreset(&gdc.m); | 
 | gdc_vectreset(&gdc.s); | gdc_vectreset(&gdc.s); | 
 |  |  | 
| Line 855  void gdc_reset(void) { | Line 1080  void gdc_reset(void) { | 
 | gdc.m.para[GDC_PITCH] = 80; | gdc.m.para[GDC_PITCH] = 80; | 
 | gdc.s.para[GDC_PITCH] = 40; | gdc.s.para[GDC_PITCH] = 40; | 
 |  |  | 
| gdc_paletteinit(); | gdc.bitac = 0xff; | 
 |  |  | 
| if (np2cfg.color16 & 1) { | // vram bank | 
| gdc.s.para[GDC_SYNC] = 0x16; | gdcs.disp = 0; | 
| gdc.display = (1 << GDCDISP_ANALOG); | gdcs.access = 0; | 
|  | gdc.analog &= ~(1 << GDCANALOG_16); | 
|  | gdcs.palchange = GDCSCRN_REDRAW; | 
|  |  | 
|  | gdc.mode2 &= ~(1 << 0); | 
|  | gdc.mode2 &= ~(1 << 2); | 
|  | gdc.mode2 &= ~(1 << 3); | 
|  | gdcs.mode2 = gdc.mode2; | 
|  |  | 
|  | vramop.operate &= ~(1 << VOPBIT_ACCESS); | 
|  | vramop.operate &= ~(1 << VOPBIT_EGC); | 
|  | vramop.operate &= ~(1 << VOPBIT_ANALOG); | 
|  | #if defined(SUPPORT_PC9821) | 
|  | gdc.analog &= ~(1 << (GDCANALOG_256)); | 
|  | vramop.operate &= ~(1 << VOPBIT_VGA); | 
|  | #endif | 
|  | i286_vram_dispatch(vramop.operate); | 
|  |  | 
|  | // palette | 
|  | CopyMemory(gdc.degpal, defdegpal, 4); | 
|  | if (gdc.display & (1 << GDCDISP_ANALOG)) { | 
|  | gdc_setanalogpalall(defanapal); | 
 | } | } | 
| gdc.bitac = 0xff; | #if defined(SUPPORT_PC9821) | 
|  | pal = gdc.anareg + (16 * 3); | 
|  | for (i=0; i<256; i+=8) { | 
|  | tmp = (UINT8)((i)?(i - 4):0); | 
|  | pal[0] = tmp; | 
|  | pal[1] = tmp; | 
|  | pal[2] = tmp; | 
|  | pal += 4; | 
|  | for (j=1; j<8; j++) { | 
|  | pal[0] = (UINT8)((i + 7) * ((j >> 2) & 1)); | 
|  | pal[1] = (UINT8)((i + 7) * ((j >> 1) & 1)); | 
|  | pal[2] = (UINT8)((i + 7) * ((j >> 0) & 1)); | 
|  | pal += 4; | 
|  | } | 
|  | } | 
|  | #endif | 
|  | gdcs.textdisp = GDCSCRN_ALLDRAW2 | GDCSCRN_EXT; | 
|  | gdcs.grphdisp = GDCSCRN_ALLDRAW2 | GDCSCRN_EXT; | 
|  | gdcs.palchange = GDCSCRN_REDRAW; | 
|  | screenupdate |= 2; | 
|  | } | 
|  |  | 
|  | void gdc_reset(void) { | 
 |  |  | 
 |  | ZeroMemory(&gdc, sizeof(gdc)); | 
 |  | ZeroMemory(&gdcs, sizeof(gdcs)); | 
 |  |  | 
 |  | #if defined(SUPPORT_PC9821) | 
 |  | gdc.display |= (1 << GDCDISP_ANALOG); | 
 |  | #else | 
 |  | if (np2cfg.color16 & 1) { | 
 |  | gdc.display |= (1 << GDCDISP_ANALOG); | 
 |  | } | 
 |  | #endif | 
 | if (!(np2cfg.dipsw[0] & 0x04)) {                        // dipsw1-3 on | if (!(np2cfg.dipsw[0] & 0x04)) {                        // dipsw1-3 on | 
 | gdc.display |= (1 << GDCDISP_PLAZMA2); | gdc.display |= (1 << GDCDISP_PLAZMA2); | 
 | } | } | 
|  | gdc_biosreset(); | 
| gdcs.textdisp = GDCSCRN_ENABLE | GDCSCRN_ALLDRAW2 | GDCSCRN_EXT; |  | 
| gdcs.grphdisp = GDCSCRN_ALLDRAW2 | GDCSCRN_EXT; |  | 
 | } | } | 
 |  |  | 
 | void gdc_bind(void) { | void gdc_bind(void) { | 
 |  |  | 
 | gdc_updateclock(); | gdc_updateclock(); | 
 |  | #if defined(SUPPORT_PC9821) | 
 |  | iocore_attachout(0x09a0, gdc_o9a0); | 
 |  | iocore_attachinp(0x09a0, gdc_i9a0); | 
 |  | #endif | 
 | #if defined(SUPPORT_CRT31KHZ) | #if defined(SUPPORT_CRT31KHZ) | 
 | iocore_attachout(0x09a8, gdc_o9a8); | iocore_attachout(0x09a8, gdc_o9a8); | 
 | iocore_attachinp(0x09a8, gdc_i9a8); | iocore_attachinp(0x09a8, gdc_i9a8); |