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| version 1.30, 2004/03/21 11:47:20 | version 1.33, 2004/03/24 06:07:57 |
|---|---|
| Line 117 void gdc_setanalogpalall(const UINT16 *p | Line 117 void gdc_setanalogpalall(const UINT16 *p |
| gdc.anareg[(c * 3) + 1] = (pal >> 4) & 15; | gdc.anareg[(c * 3) + 1] = (pal >> 4) & 15; |
| gdc.anareg[(c * 3) + 2] = (pal >> 0) & 15; | gdc.anareg[(c * 3) + 2] = (pal >> 0) & 15; |
| #endif | #endif |
| gdc_setanalogpal(c, offsetof(RGB32, p.g), (pal >> 8) & 15); | gdc_setanalogpal(c, offsetof(RGB32, p.g), (REG8)((pal >> 8) & 15)); |
| gdc_setanalogpal(c, offsetof(RGB32, p.r), (pal >> 4) & 15); | gdc_setanalogpal(c, offsetof(RGB32, p.r), (REG8)((pal >> 4) & 15)); |
| gdc_setanalogpal(c, offsetof(RGB32, p.b), (pal >> 0) & 15); | gdc_setanalogpal(c, offsetof(RGB32, p.b), (REG8)((pal >> 0) & 15)); |
| } | } |
| } | } |
| Line 404 const GDCCLK *clk; | Line 404 const GDCCLK *clk; |
| y = clk->maxy; | y = clk->maxy; |
| } | } |
| hclock = clk->clock / x; | hclock = clk->clock / x; |
| gdc.hclock = hclock; | |
| gdc.vclock = hclock * 10 / y; | |
| cnt = (pccore.baseclock * y) / hclock; | cnt = (pccore.baseclock * y) / hclock; |
| cnt *= pccore.multiple; | cnt *= pccore.multiple; |
| gdc.rasterclock = cnt / y; | gdc.rasterclock = cnt / y; |
| Line 933 static REG8 IOINPCALL gdc_iae(UINT port) | Line 935 static REG8 IOINPCALL gdc_iae(UINT port) |
| #if defined(SUPPORT_PC9821) | #if defined(SUPPORT_PC9821) |
| static void IOOUTCALL gdc_o9a0(UINT port, REG8 dat) { | static void IOOUTCALL gdc_o9a0(UINT port, REG8 dat) { |
| gdc.ff2 = dat; | |
| (void)port; | (void)port; |
| (void)dat; | |
| } | } |
| static REG8 IOINPCALL gdc_i9a0(UINT port) { | static REG8 IOINPCALL gdc_i9a0(UINT port) { |
| REG8 ret; | |
| ret = 0; | |
| switch(gdc.ff2) { | |
| case 0x00: | |
| ret = 0xff; | |
| break; | |
| case 0x01: | |
| ret = (gdc.mode1 >> 1) & 1; | |
| break; | |
| case 0x02: | |
| ret = (gdc.mode1 >> 4) & 1; | |
| break; | |
| case 0x03: | |
| ret = (gdc.mode1 >> 7) & 1; | |
| break; | |
| case 0x04: | |
| ret = (gdc.mode2 >> 0) & 1; | |
| break; | |
| case 0x05: | |
| ret = (gdc.display >> GDCDISP_PLAZMA) & 1; | |
| break; | |
| case 0x07: | |
| ret = (gdc.mode2 >> 2) & 1; | |
| break; | |
| case 0x08: | |
| ret = (gdc.mode2 >> 3) & 1; | |
| break; | |
| case 0x09: | |
| ret = (gdc.clock >> 0) & 1; | |
| break; | |
| case 0x0a: | |
| ret = (gdc.analog >> GDCANALOG_256) & 1; | |
| break; | |
| case 0x0b: | |
| ret = 1; | |
| break; | |
| case 0x0d: | |
| ret = (gdc.analog >> GDCANALOG_256E) & 1; | |
| break; | |
| } | |
| ret |= (gdc.clock & 2); | |
| (void)port; | (void)port; |
| return(0); | return(ret); |
| } | } |
| #endif | #endif |
| Line 1087 void gdc_reset(void) { | Line 1142 void gdc_reset(void) { |
| void gdc_bind(void) { | void gdc_bind(void) { |
| gdc_updateclock(); | gdc_updateclock(); |
| #if defined(SUPPORT_PC9821) // とりあえずフックだけ | #if defined(SUPPORT_PC9821) |
| iocore_attachout(0x09a0, gdc_o9a0); | iocore_attachout(0x09a0, gdc_o9a0); |
| iocore_attachinp(0x09a0, gdc_i9a0); | iocore_attachinp(0x09a0, gdc_i9a0); |
| #endif | #endif |