| version 1.2, 2003/10/17 07:17:20 | version 1.40, 2007/11/03 00:00:20 | 
| Line 1 | Line 1 | 
 | #include        "compiler.h" | #include        "compiler.h" | 
 | #include        "scrnmng.h" | #include        "scrnmng.h" | 
| #include        "i286.h" | #include        "cpucore.h" | 
| #include        "memory.h" |  | 
 | #include        "pccore.h" | #include        "pccore.h" | 
 | #include        "iocore.h" | #include        "iocore.h" | 
 | #include        "gdc_cmd.tbl" | #include        "gdc_cmd.tbl" | 
| #include        "palettes.h" | #include        "gdc_sub.h" | 
 | #include        "vram.h" | #include        "vram.h" | 
 |  | #include        "palettes.h" | 
 |  | #include        "timing.h" | 
 |  |  | 
|  | #if !defined(CPUCORE_IA32) | 
| #define SEARHC_SYNC | #define SEARCH_SYNC | 
|  | #endif | 
 | #define TURE_SYNC | #define TURE_SYNC | 
 |  |  | 
| extern BYTE screenupdate; | typedef struct { | 
|  | UINT32  clock; | 
|  | UINT    minx; | 
|  | UINT    maxx; | 
|  | UINT    miny; | 
|  | UINT    maxy; | 
|  | } GDCCLK; | 
|  |  | 
|  | // 31kHzの時の動作クロックが不明… | 
|  | static const GDCCLK gdcclk[] = { | 
|  | {14318180 / 8, 112 - 8, 112 + 8, 200, 300}, | 
|  | {21052600 / 8, 106 - 6, 106 + 6, 400, 575}, | 
|  | {25260000 / 8, 100 - 8, 100 + 8, 400, 575}}; | 
|  |  | 
|  |  | 
|  | typedef struct { | 
|  | UINT8   master[8]; | 
|  | UINT8   slave[8]; | 
|  | } GDCSYNC; | 
|  |  | 
|  | static const UINT8 defsyncm15[8] = {0x10,0x4e,0x07,0x25,0x0d,0x0f,0xc8,0x94}; | 
|  | static const UINT8 defsyncs15[8] = {0x06,0x26,0x03,0x11,0x86,0x0f,0xc8,0x94}; | 
 |  |  | 
 |  | static const UINT8 defsyncm24[8] = {0x10,0x4e,0x07,0x25,0x07,0x07,0x90,0x65}; | 
 |  | static const UINT8 defsyncs24[8] = {0x06,0x26,0x03,0x11,0x83,0x07,0x90,0x65}; | 
 |  |  | 
| static const BYTE defdegpal[4] = {0x04,0x15,0x26,0x37}; | static const UINT8 defsyncm31[8] = {0x10,0x4e,0x47,0x0c,0x07,0x0d,0x90,0x89}; | 
| static const BYTE defsync[8] = {0x10,0x4e,0x07,0x25,0x07,0x07,0x90,0x65}; | static const UINT8 defsyncs31[8] = {0x06,0x26,0x41,0x0c,0x83,0x0d,0x90,0x89}; | 
 |  |  | 
 |  |  | 
| void gdc_setdegitalpal(int color, BYTE value) { | static const UINT8 defdegpal[4] = {0x04,0x15,0x26,0x37}; | 
|  | static const UINT16 defanapal[16] = { | 
|  | 0x000,0x007,0x070,0x077,0x700,0x707,0x770,0x777, | 
|  | 0x444,0x00f,0x0f0,0x0ff,0xf00,0xf0f,0xff0,0xfff}; | 
|  |  | 
|  |  | 
|  | void gdc_setdegitalpal(int color, REG8 value) { | 
 |  |  | 
 | if (color & 4) { | if (color & 4) { | 
 | color &= 3; | color &= 3; | 
| Line 41  void gdc_setdegitalpal(int color, BYTE v | Line 72  void gdc_setdegitalpal(int color, BYTE v | 
 | } | } | 
 | } | } | 
 |  |  | 
| void gdc_setanalogpal(int color, int rgb, BYTE value) { | void gdc_setdegpalpack(int color, REG8 value) { | 
|  |  | 
|  | if ((gdc.degpal[color] ^ value) & 0x77) { | 
|  | gdcs.palchange = GDCSCRN_REDRAW; | 
|  | } | 
|  | gdc.degpal[color] = (UINT8)value; | 
|  | } | 
|  |  | 
|  | void gdc_setanalogpal(int color, int rgb, REG8 value) { | 
 |  |  | 
| BYTE            *ptr; | UINT8           *ptr; | 
 | PAL1EVENT       *event; | PAL1EVENT       *event; | 
 |  |  | 
| ptr = ((BYTE *)(gdc.anapal + color)) + rgb; | ptr = ((UINT8 *)(gdc.anapal + color)) + rgb; | 
| if ((*ptr ^ value) & 0x0f) { | if (((*ptr) ^ value) & 0x0f) { | 
 | gdcs.palchange = GDCSCRN_REDRAW; | gdcs.palchange = GDCSCRN_REDRAW; | 
| if ((palevent.events < PALEVENTMAX) && (!gdc.vsync)) { | if (palevent.events < PALEVENTMAX) { | 
| event = palevent.event + palevent.events; | if (!gdc.vsync) { | 
| event->clock = nevent.item[NEVENT_FLAMES].clock - | event = palevent.event + palevent.events; | 
| (nevent.baseclock - nevent.remainclock); | event->clock = nevent.item[NEVENT_FLAMES].clock - | 
| event->color = (color * sizeof(RGB32)) + rgb; | (CPU_BASECLOCK - CPU_REMCLOCK); | 
| event->value = value; | event->color = (UINT16)((color * sizeof(RGB32)) + rgb); | 
| palevent.events++; | event->value = (UINT8)value; | 
|  | palevent.events++; | 
|  | } | 
|  | else { | 
|  | palevent.vsyncpal = 1; | 
|  | } | 
 | } | } | 
 | } | } | 
 | *ptr = value; | *ptr = value; | 
 | } | } | 
 |  |  | 
| void gdc_setdegpalpack(int color, BYTE value) { | void gdc_setanalogpalall(const UINT16 *paltbl) { | 
 |  |  | 
| if ((gdc.degpal[color] ^ value) & 0x77) { | UINT    c; | 
| gdcs.palchange = GDCSCRN_REDRAW; | UINT    pal; | 
|  |  | 
|  | for (c=0; c<16; c++) { | 
|  | pal = *paltbl++; | 
|  | #if defined(SUPPORT_PC9821) | 
|  | gdc.anareg[(c * 3) + 0] = (pal >> 8) & 15; | 
|  | gdc.anareg[(c * 3) + 1] = (pal >> 4) & 15; | 
|  | gdc.anareg[(c * 3) + 2] = (pal >> 0) & 15; | 
|  | #endif | 
|  | gdc_setanalogpal(c, offsetof(RGB32, p.g), (REG8)((pal >> 8) & 15)); | 
|  | gdc_setanalogpal(c, offsetof(RGB32, p.r), (REG8)((pal >> 4) & 15)); | 
|  | gdc_setanalogpal(c, offsetof(RGB32, p.b), (REG8)((pal >> 0) & 15)); | 
 | } | } | 
 | gdc.degpal[color] = value; |  | 
 | } | } | 
 |  |  | 
 |  |  | 
 | void gdc_paletteinit(void) { | void gdc_paletteinit(void) { | 
 |  |  | 
| BYTE    c; | int             c; | 
 |  |  | 
 | CopyMemory(gdc.degpal, defdegpal, 4); | CopyMemory(gdc.degpal, defdegpal, 4); | 
 | for (c=0; c<8; c++) { | for (c=0; c<8; c++) { | 
| Line 88  void gdc_paletteinit(void) { | Line 143  void gdc_paletteinit(void) { | 
 | gdcs.palchange = GDCSCRN_REDRAW; | gdcs.palchange = GDCSCRN_REDRAW; | 
 | } | } | 
 |  |  | 
 |  | #if defined(SUPPORT_PC9821) | 
 |  | void gdc_analogext(BOOL extend) { | 
 |  |  | 
 |  | if (extend) { | 
 |  | gdc.analog |= (1 << GDCANALOG_256); | 
 |  | vramop.operate |= (1 << VOPBIT_VGA); | 
 |  | } | 
 |  | else { | 
 |  | gdc.analog &= ~(1 << (GDCANALOG_256)); | 
 |  | vramop.operate &= ~(1 << VOPBIT_VGA); | 
 |  | } | 
 |  | gdcs.palchange = GDCSCRN_REDRAW; | 
 |  | gdcs.grphdisp |= GDCSCRN_EXT | GDCSCRN_ALLDRAW2; | 
 |  | MEMM_VRAM(vramop.operate); | 
 |  | } | 
 |  | #endif | 
 |  |  | 
 |  |  | 
 | // -------------------------------------------------------------------------- | // -------------------------------------------------------------------------- | 
 |  |  | 
 |  | void gdc_vectreset(GDCDATA item) { | 
 |  |  | 
 |  | item->para[GDC_VECTW+1] = 0x00; | 
 |  | item->para[GDC_VECTW+2] = 0x00; | 
 |  | item->para[GDC_VECTW+3] = 0x08; | 
 |  | item->para[GDC_VECTW+4] = 0x00; | 
 |  | item->para[GDC_VECTW+5] = 0x08; | 
 |  | item->para[GDC_VECTW+6] = 0x00; | 
 |  | item->para[GDC_VECTW+7] = 0xff; | 
 |  | item->para[GDC_VECTW+8] = 0xff; | 
 |  | item->para[GDC_VECTW+9] = 0xff; | 
 |  | item->para[GDC_VECTW+10] = 0xff; | 
 |  | } | 
 |  |  | 
 | static void vectdraw(void) { | static void vectdraw(void) { | 
 |  |  | 
| UINT32  csrw; | UINT32          csrw; | 
| UINT16  textw; | const GDCVECT   *vect; | 
|  | REG16           textw; | 
|  | REG8            ope; | 
 |  |  | 
 | csrw = LOADINTELDWORD(gdc.s.para + GDC_CSRW); | csrw = LOADINTELDWORD(gdc.s.para + GDC_CSRW); | 
 |  | vect = (GDCVECT *)(gdc.s.para + GDC_VECTW); | 
 | textw = LOADINTELWORD(gdc.s.para + GDC_TEXTW); | textw = LOADINTELWORD(gdc.s.para + GDC_TEXTW); | 
 |  | ope = gdc.s.para[GDC_WRITE]; | 
 |  |  | 
| if (gdc.s.para[GDC_VECTW] & 0x8) { | if (vect->ope & 0x08) { | 
| gdcsub_line(csrw, (GDCVECT *)(gdc.s.para + GDC_VECTW), | gdcsub_vectl(csrw, vect, textw, ope); | 
| textw, gdc.s.para[GDC_WRITE]); | } | 
|  | if (vect->ope & 0x10) {         // undocumented | 
|  | gdcsub_vectt(csrw, vect, textw, ope); | 
 | } | } | 
| if (gdc.s.para[GDC_VECTW] & 0x20) { | if (vect->ope & 0x20) { | 
| gdcsub_circle(csrw, (GDCVECT *)(gdc.s.para + GDC_VECTW), | gdcsub_vectc(csrw, vect, textw, ope); | 
| textw, gdc.s.para[GDC_WRITE]); |  | 
 | } | } | 
| if (gdc.s.para[GDC_VECTW] & 0x40) { | if (vect->ope & 0x40) { | 
| gdcsub_box(csrw, (GDCVECT *)(gdc.s.para + GDC_VECTW), | gdcsub_vectr(csrw, vect, textw, ope); | 
| textw, gdc.s.para[GDC_WRITE]); |  | 
 | } | } | 
 |  | gdc_vectreset(&gdc.s); | 
 | } | } | 
 |  |  | 
| static void textdraw(void) {                                                                    // ver0.30 | static void textdraw(void) { | 
 |  |  | 
| UINT32  csrw; | UINT32          csrw; | 
| UINT16  textw; | const GDCVECT   *vect; | 
|  | REG16           textw; | 
|  | REG8            ope; | 
 |  |  | 
| if (gdc.s.para[GDC_VECTW] & 0x10) { | csrw = LOADINTELDWORD(gdc.s.para + GDC_CSRW); | 
| csrw = LOADINTELDWORD(gdc.s.para + GDC_CSRW); | vect = (GDCVECT *)(gdc.s.para + GDC_VECTW); | 
| textw = LOADINTELWORD(gdc.s.para + GDC_TEXTW); | textw = gdc.s.para[GDC_TEXTW + 7]; | 
| gdcsub_text(csrw, (GDCVECT *)(gdc.s.para + GDC_VECTW), | textw = (textw << 8) + textw; | 
| textw, gdc.s.para[GDC_WRITE]); | ope = gdc.s.para[GDC_WRITE]; | 
|  |  | 
|  | if (vect->ope & 0x08) {         // undocumented | 
|  | gdcsub_vectl(csrw, vect, textw, ope); | 
|  | } | 
|  | if (vect->ope & 0x10) { | 
|  | gdcsub_text(csrw, vect, gdc.s.para + GDC_TEXTW, ope); | 
|  | } | 
|  | if (vect->ope & 0x20) {         // undocumented | 
|  | gdcsub_vectc(csrw, vect, textw, ope); | 
 | } | } | 
 |  | if (vect->ope & 0x40) {         // undocumented | 
 |  | gdcsub_vectr(csrw, vect, textw, ope); | 
 |  | } | 
 |  | gdc_vectreset(&gdc.s); | 
 | } | } | 
 |  |  | 
 | void gdc_work(int id) { | void gdc_work(int id) { | 
 |  |  | 
 | UINT16          i; |  | 
 | BYTE            data; |  | 
 | GDCDATA         item; | GDCDATA         item; | 
| BYTE            *dispflag; | UINT8           *dispflag; | 
|  | UINT            i; | 
|  | UINT8           data; | 
 |  |  | 
| item = ((id==GDCWORK_MASTER)?(&gdc.m):(&gdc.s)); | item = (id == GDCWORK_MASTER)?&gdc.m:&gdc.s; | 
| dispflag = ((id==GDCWORK_MASTER)?(&gdcs.textdisp):(&gdcs.grphdisp)); | dispflag = (id == GDCWORK_MASTER)?&gdcs.textdisp:&gdcs.grphdisp; | 
 |  |  | 
 | for (i=0; i<item->cnt; i++) { | for (i=0; i<item->cnt; i++) { | 
| data = (BYTE)item->fifo[i]; | data = (UINT8)item->fifo[i]; | 
 | if (item->fifo[i] & 0xff00) { | if (item->fifo[i] & 0xff00) { | 
| item->cmd = data;                                                                               // ver0.29 | item->cmd = data; | 
 | item->paracb = 0; | item->paracb = 0; | 
 | if ((data & 0x60) == 0x20) { | if ((data & 0x60) == 0x20) { | 
 | item->para[GDC_WRITE] = data; | item->para[GDC_WRITE] = data; | 
| Line 148  void gdc_work(int id) { | Line 254  void gdc_work(int id) { | 
 | item->rcv = 2; | item->rcv = 2; | 
 | item->paracb = 1; | item->paracb = 1; | 
 | break; | break; | 
 |  |  | 
 | case 0x10: | case 0x10: | 
 | case 0x18: | case 0x18: | 
 | item->rcv = 1; | item->rcv = 1; | 
 | item->paracb = 1; | item->paracb = 1; | 
 | break; | break; | 
 |  |  | 
 | default: | default: | 
 | item->rcv = 0; | item->rcv = 0; | 
 | break; | break; | 
| Line 166  void gdc_work(int id) { | Line 274  void gdc_work(int id) { | 
 | case CMD_START: | case CMD_START: | 
 | case CMD_SYNC_ON: | case CMD_SYNC_ON: | 
 | (*dispflag) |= GDCSCRN_ENABLE | GDCSCRN_ALLDRAW2; | (*dispflag) |= GDCSCRN_ENABLE | GDCSCRN_ALLDRAW2; | 
| screenupdate |= 2;                                                              // ver0.28 | screenupdate |= 2; | 
 | break; | break; | 
 |  |  | 
 |  | case CMD_STOP_: | 
 | case CMD_STOP: | case CMD_STOP: | 
 | case CMD_SYNC_OFF: | case CMD_SYNC_OFF: | 
 | (*dispflag) &= (~GDCSCRN_ENABLE); | (*dispflag) &= (~GDCSCRN_ENABLE); | 
 | //                                      (*dispflag) |= GDCSCRN_ALLDRAW2; | //                                      (*dispflag) |= GDCSCRN_ALLDRAW2; | 
| screenupdate |= 2;                                                              // ver0.28 | screenupdate |= 2; | 
 | break; | break; | 
 |  |  | 
 | case CMD_VECTE: | case CMD_VECTE: | 
| Line 182  void gdc_work(int id) { | Line 291  void gdc_work(int id) { | 
 | } | } | 
 | break; | break; | 
 |  |  | 
| case CMD_TEXTE:                                                                         // ver0.30 | case CMD_TEXTE: | 
 | if (id != GDCWORK_MASTER) { | if (id != GDCWORK_MASTER) { | 
 | textdraw(); | textdraw(); | 
 | } | } | 
 | break; | break; | 
 |  |  | 
 | } | } | 
 | item->ptr = gdc_cmd[data].pos; | item->ptr = gdc_cmd[data].pos; | 
 | item->rcv = gdc_cmd[data].outdatas; | item->rcv = gdc_cmd[data].outdatas; | 
| Line 210  void gdc_work(int id) { | Line 318  void gdc_work(int id) { | 
 | (*dispflag) |= gdc_dirtyflag[id][item->ptr]; | (*dispflag) |= gdc_dirtyflag[id][item->ptr]; | 
 | } | } | 
 | (item->ptr)++; | (item->ptr)++; | 
| (item->rcv)--;                                  // ver0.29 | (item->rcv)--; | 
 | if ((!(item->rcv)) && (id == GDCWORK_SLAVE) && | if ((!(item->rcv)) && (id == GDCWORK_SLAVE) && | 
 | (((item->cmd) & 0xe4) == 0x20)) { | (((item->cmd) & 0xe4) == 0x20)) { | 
 | gdcsub_write(); | gdcsub_write(); | 
| item->paracb = 0;                       // ver0.29 | item->paracb = 0; | 
 | } | } | 
 | } | } | 
 | } | } | 
| Line 222  void gdc_work(int id) { | Line 330  void gdc_work(int id) { | 
 | } | } | 
 |  |  | 
 | // BIOSとかで弄った時にリセット | // BIOSとかで弄った時にリセット | 
| void gdc_forceready(GDCDATA item) { | void gdc_forceready(int id) { | 
 |  |  | 
 |  | GDCDATA item; | 
 |  | item = (id == GDCWORK_MASTER)?&gdc.m:&gdc.s; | 
 |  | if (item->cnt) { | 
 |  | gdc_work(id); | 
 |  | } | 
 | item->rcv = 0; | item->rcv = 0; | 
 | item->snd = 0; | item->snd = 0; | 
 | } | } | 
 |  |  | 
 |  |  | 
 |  | void gdc_updateclock(void) { | 
 |  |  | 
 |  | UINT            tmp; | 
 |  | UINT            cr; | 
 |  | UINT            hfbs; | 
 |  | UINT            vfbs; | 
 |  | UINT            lf; | 
 |  | UINT            x; | 
 |  | UINT            y; | 
 |  | UINT            cnt; | 
 |  | const GDCCLK    *clk; | 
 |  | UINT32          hclock; | 
 |  |  | 
 |  | cr = gdc.m.para[GDC_SYNC + 1] + 2; | 
 |  | tmp = LOADINTELWORD(gdc.m.para + GDC_SYNC + 2); | 
 |  | hfbs = tmp & 0x1f;                                                                      // HS | 
 |  | hfbs += tmp >> 10;                                                                      // HFP | 
 |  | vfbs = (tmp >> 5) & 0x1f;                                                       // VS | 
 |  | hfbs += gdc.m.para[GDC_SYNC + 4] & 0x3f;                        // HFP | 
 |  | vfbs += gdc.m.para[GDC_SYNC + 5] & 0x3f;                        // VFP | 
 |  | tmp = LOADINTELWORD(gdc.m.para + GDC_SYNC + 6); | 
 |  | lf = ((tmp - 1) & 0x3ff) + 1; | 
 |  | vfbs += tmp >> 10;                                                                      // VBP | 
 |  |  | 
 |  | hfbs += 3; | 
 |  | x = cr + hfbs; | 
 |  | if (!vfbs) { | 
 |  | vfbs = 1; | 
 |  | } | 
 |  | y = lf + vfbs; | 
 |  | //      TRACEOUT(("h %d:%d / v %d:%d", cr, x, lf, y)); | 
 |  |  | 
 |  | #if defined(SUPPORT_CRT31KHZ) | 
 |  | if (gdc.display & (1 << GDCDISP_31)) { | 
 |  | clk = gdcclk + 2; | 
 |  | } | 
 |  | else | 
 |  | #endif | 
 |  | if (!(gdc.crt15khz & 2)) {                                                      // 24.83±300Hz | 
 |  | clk = gdcclk + 1; | 
 |  | } | 
 |  | else {                                                                                          // 15.98±300Hz | 
 |  | clk = gdcclk; | 
 |  | } | 
 |  |  | 
 |  | if (x < clk->minx) { | 
 |  | cr = (clk->minx * cr) / x; | 
 |  | x = clk->minx; | 
 |  | } | 
 |  | else if (x > clk->maxx) { | 
 |  | cr = (clk->maxx * cr) / x; | 
 |  | x = clk->maxx; | 
 |  | } | 
 |  | if (y < clk->miny) { | 
 |  | lf = (clk->miny * lf) / y; | 
 |  | y = clk->miny; | 
 |  | } | 
 |  | else if (y > clk->maxy) { | 
 |  | lf = (clk->maxy * lf) / y; | 
 |  | y = clk->maxy; | 
 |  | } | 
 |  | hclock = clk->clock / x; | 
 |  | gdc.hclock = hclock; | 
 |  | gdc.vclock = hclock * 10 / y; | 
 |  | cnt = (pccore.baseclock * y) / hclock; | 
 |  | cnt *= pccore.multiple; | 
 |  | gdc.rasterclock = cnt / y; | 
 |  | gdc.hsyncclock = (gdc.rasterclock * cr) / x; | 
 |  | gdc.dispclock = gdc.rasterclock * lf; | 
 |  | gdc.vsyncclock = cnt - gdc.dispclock; | 
 |  | timing_setrate(y, hclock); | 
 |  | } | 
 |  |  | 
 | void gdc_restorekacmode(void) { | void gdc_restorekacmode(void) { | 
 |  |  | 
| BYTE    bit; | UINT8   bit; | 
 |  |  | 
 | bit = (((!np2cfg.uPD72020) && (gdc.mode1 & 0x20))?0x00:0xff); | bit = (((!np2cfg.uPD72020) && (gdc.mode1 & 0x20))?0x00:0xff); | 
 | if (gdc.bitac != bit) { | if (gdc.bitac != bit) { | 
| Line 240  void gdc_restorekacmode(void) { | Line 427  void gdc_restorekacmode(void) { | 
 | } | } | 
 |  |  | 
 |  |  | 
| // ---- I/O | // ---- I/O master | 
 |  |  | 
| static void IOOUTCALL gdc_o60(UINT port, BYTE dat) { | static void IOOUTCALL gdc_o60(UINT port, REG8 dat) { | 
 |  |  | 
 | if (gdc.m.cnt < GDCCMD_MAX) { | if (gdc.m.cnt < GDCCMD_MAX) { | 
 | gdc.m.fifo[gdc.m.cnt++] = dat; | gdc.m.fifo[gdc.m.cnt++] = dat; | 
| Line 250  static void IOOUTCALL gdc_o60(UINT port, | Line 437  static void IOOUTCALL gdc_o60(UINT port, | 
 | (void)port; | (void)port; | 
 | } | } | 
 |  |  | 
| static void IOOUTCALL gdc_o62(UINT port, BYTE dat) { | static void IOOUTCALL gdc_o62(UINT port, REG8 dat) { | 
 |  |  | 
 | if (gdc.m.cnt < GDCCMD_MAX) { | if (gdc.m.cnt < GDCCMD_MAX) { | 
 | gdc.m.fifo[gdc.m.cnt++] = 0x100 | dat; | gdc.m.fifo[gdc.m.cnt++] = 0x100 | dat; | 
| Line 259  static void IOOUTCALL gdc_o62(UINT port, | Line 446  static void IOOUTCALL gdc_o62(UINT port, | 
 | (void)port; | (void)port; | 
 | } | } | 
 |  |  | 
| static void IOOUTCALL gdc_o64(UINT port, BYTE dat) { | static void IOOUTCALL gdc_o64(UINT port, REG8 dat) { | 
 |  |  | 
 | gdc.vsyncint = 1; | gdc.vsyncint = 1; | 
 | (void)port; | (void)port; | 
 | (void)dat; | (void)dat; | 
 | } | } | 
 |  |  | 
| static void IOOUTCALL gdc_o68(UINT port, BYTE dat) { | static void IOOUTCALL gdc_o68(UINT port, REG8 dat) { | 
 |  |  | 
| BYTE    bit; | REG8    bit; | 
 |  |  | 
| if (!(dat & 0xf0)) {                                                                    // ver0.28 | if (!(dat & 0xf0)) { | 
 | bit = 1 << ((dat >> 1) & 7); | bit = 1 << ((dat >> 1) & 7); | 
 | if (dat & 1) { | if (dat & 1) { | 
 | gdc.mode1 |= bit; | gdc.mode1 |= bit; | 
| Line 281  static void IOOUTCALL gdc_o68(UINT port, | Line 468  static void IOOUTCALL gdc_o68(UINT port, | 
 | if (bit & (0x01 | 0x04 | 0x10)) { | if (bit & (0x01 | 0x04 | 0x10)) { | 
 | gdcs.grphdisp |= GDCSCRN_ALLDRAW2; | gdcs.grphdisp |= GDCSCRN_ALLDRAW2; | 
 | } | } | 
| else if (bit == 0x02) {                                                         // ver0.28 | else if (bit == 0x02) { | 
 | gdcs.grphdisp |= GDCSCRN_ALLDRAW2; | gdcs.grphdisp |= GDCSCRN_ALLDRAW2; | 
 | gdcs.palchange = GDCSCRN_REDRAW; | gdcs.palchange = GDCSCRN_REDRAW; | 
 | } | } | 
 |  | else if (bit == 0x08) { | 
 |  | gdcs.textdisp |= GDCSCRN_ALLDRAW2; | 
 |  | } | 
 | else if (bit == 0x20) { | else if (bit == 0x20) { | 
 | gdc_restorekacmode(); | gdc_restorekacmode(); | 
 | } | } | 
| Line 296  static void IOOUTCALL gdc_o68(UINT port, | Line 486  static void IOOUTCALL gdc_o68(UINT port, | 
 | (void)port; | (void)port; | 
 | } | } | 
 |  |  | 
| static void IOOUTCALL gdc_o6a(UINT port, BYTE dat) { | static void IOOUTCALL gdc_o6a(UINT port, REG8 dat) { | 
 |  |  | 
| BYTE    bit; | REG8    bit; | 
 |  |  | 
 | if (!(dat & 0xf8)) { | if (!(dat & 0xf8)) { | 
 | bit = (dat >> 1) & 3; | bit = (dat >> 1) & 3; | 
| Line 309  static void IOOUTCALL gdc_o6a(UINT port, | Line 499  static void IOOUTCALL gdc_o6a(UINT port, | 
 | gdc.mode2 ^= (1 << bit); | gdc.mode2 ^= (1 << bit); | 
 | switch(bit) { | switch(bit) { | 
 | case 0: | case 0: | 
| if (gdc.display & 2) { | if (gdc.display & (1 << GDCDISP_ANALOG)) { | 
| gdc.analog = dat; | gdc.analog &= ~(1 << GDCANALOG_16); | 
|  | gdc.analog |= (dat << GDCANALOG_16); | 
 | gdcs.palchange = GDCSCRN_REDRAW; | gdcs.palchange = GDCSCRN_REDRAW; | 
| vramop.operate &= VOP_ANALOGMASK; | vramop.operate &= ~(1 << VOPBIT_ANALOG); | 
| vramop.operate |= dat << 4; | vramop.operate |= dat << VOPBIT_ANALOG; | 
| i286_vram_dispatch(vramop.operate); | MEMM_VRAM(vramop.operate); | 
 | } | } | 
 | break; | break; | 
 |  |  | 
 | case 2: | case 2: | 
 | if ((gdc.mode2 & 0x08) && (grcg.chip == 3)) { | if ((gdc.mode2 & 0x08) && (grcg.chip == 3)) { | 
| vramop.operate &= VOP_EGCMASK; | vramop.operate &= ~(1 << VOPBIT_EGC); | 
| vramop.operate |= dat << 1; | vramop.operate |= dat << VOPBIT_EGC; | 
| i286_vram_dispatch(vramop.operate); | MEMM_VRAM(vramop.operate); | 
 | } | } | 
 | break; | break; | 
 | } | } | 
| Line 330  static void IOOUTCALL gdc_o6a(UINT port, | Line 521  static void IOOUTCALL gdc_o6a(UINT port, | 
 | } | } | 
 | else { | else { | 
 | switch(dat) { | switch(dat) { | 
 |  | #if defined(SUPPORT_PC9821) | 
 |  | case 0x20: | 
 |  | if (gdc.mode2 & 0x08) { | 
 |  | gdc_analogext(FALSE); | 
 |  | } | 
 |  | break; | 
 |  |  | 
 |  | case 0x21: | 
 |  | if (gdc.mode2 & 0x08) { | 
 |  | gdc_analogext(TRUE); | 
 |  | } | 
 |  | break; | 
 |  |  | 
 |  | case 0x68: | 
 |  | gdc.analog &= ~(1 << GDCANALOG_256E); | 
 |  | break; | 
 |  |  | 
 |  | case 0x69: | 
 |  | gdc.analog |= (1 << GDCANALOG_256E); | 
 |  | break; | 
 |  | #endif | 
 | case 0x40: | case 0x40: | 
| gdc.display &= ~1; | case 0x80:                                      // EPSON? | 
|  | gdc.display &= ~(1 << GDCDISP_PLAZMA); | 
 | gdcs.textdisp |= GDCSCRN_EXT; | gdcs.textdisp |= GDCSCRN_EXT; | 
 | break; | break; | 
 |  |  | 
 | case 0x41: | case 0x41: | 
| gdc.display |= 1; | case 0x81:                                      // EPSON? | 
|  | gdc.display |= (1 << GDCDISP_PLAZMA); | 
 | gdcs.textdisp |= GDCSCRN_EXT; | gdcs.textdisp |= GDCSCRN_EXT; | 
 | break; | break; | 
 |  |  | 
| Line 364  static void IOOUTCALL gdc_o6a(UINT port, | Line 578  static void IOOUTCALL gdc_o6a(UINT port, | 
 | (void)port; | (void)port; | 
 | } | } | 
 |  |  | 
| static BYTE IOINPCALL gdc_i60(UINT port) { | static void IOOUTCALL gdc_o6e(UINT port, REG8 dat) { | 
|  |  | 
|  | switch(dat) { | 
|  | case 0: | 
|  | gdc.crt15khz &= ~1; | 
|  | gdcs.textdisp |= GDCSCRN_ALLDRAW2; | 
|  | break; | 
|  |  | 
|  | case 1: | 
|  | gdc.crt15khz |= 1; | 
|  | gdcs.textdisp |= GDCSCRN_ALLDRAW2; | 
|  | break; | 
|  | } | 
|  | (void)port; | 
|  | } | 
 |  |  | 
| BYTE    ret; | static REG8 IOINPCALL gdc_i60(UINT port) { | 
| long    remain; |  | 
|  | REG8    ret; | 
|  | SINT32  remain; | 
 |  |  | 
 | ret = 0x80 | gdc.vsync;         // | m_drawing; | ret = 0x80 | gdc.vsync;         // | m_drawing; | 
 | remain = nevent_getremain(NEVENT_FLAMES); | remain = nevent_getremain(NEVENT_FLAMES); | 
 | if (remain >= 0) { | if (remain >= 0) { | 
| if ((remain % pc.raster) < pc.hsync) { | if ((remain % gdc.rasterclock) < gdc.hsyncclock) { | 
 | ret |= 0x40; | ret |= 0x40; | 
 | } | } | 
 | } | } | 
| Line 388  static BYTE IOINPCALL gdc_i60(UINT port) | Line 618  static BYTE IOINPCALL gdc_i60(UINT port) | 
 | else { | else { | 
 | gdc_work(GDCWORK_MASTER); | gdc_work(GDCWORK_MASTER); | 
 | } | } | 
| #ifdef SEARHC_SYNC | #ifdef SEARCH_SYNC              // ToDo: フェッチキューを参照するように… | 
| if ((i286reg.inport) && (nevent.remainclock >= 5)) { | if ((CPU_INPADRS) && (CPU_REMCLOCK >= 5)) { | 
| UINT16 jadr = 0xfa74; | UINT32 addr; | 
|  | UINT16 jadr; | 
 | UINT16 memv; | UINT16 memv; | 
| memv = i286_memoryread_w(i286reg.inport); | addr = CPU_INPADRS; | 
|  | jadr = 0xfa74; | 
|  | memv = MEML_READ16(addr); | 
 | while((memv == 0x00eb) || (memv == 0x5fe6)) { | while((memv == 0x00eb) || (memv == 0x5fe6)) { | 
 | jadr -= 0x200; | jadr -= 0x200; | 
| i286reg.inport += 2; | addr += 2; | 
| memv = i286_memoryread_w(i286reg.inport); | memv = MEML_READ16(addr); | 
 | } | } | 
 | if ((memv == 0x20a8) || (memv == 0x2024)) { | if ((memv == 0x20a8) || (memv == 0x2024)) { | 
| memv = i286_memoryread_w(i286reg.inport + 2); | memv = MEML_READ16(addr + 2); | 
 | if (memv == jadr) {                                     // je | if (memv == jadr) {                                     // je | 
 | if (!gdc.vsync) { | if (!gdc.vsync) { | 
| nevent.remainclock = -1; | CPU_REMCLOCK = -1; | 
 | } | } | 
 | } | } | 
 | else if (memv == (jadr + 1)) {          // jne | else if (memv == (jadr + 1)) {          // jne | 
 | if (gdc.vsync) { | if (gdc.vsync) { | 
| nevent.remainclock = -1; | CPU_REMCLOCK = -1; | 
 | } | } | 
 | } | } | 
 | } | } | 
 | } | } | 
 | #endif | #endif | 
 | #ifdef TURE_SYNC                                // クロックイベントの誤差修正 | #ifdef TURE_SYNC                                // クロックイベントの誤差修正 | 
| if (nevent.item[NEVENT_FLAMES].clock < | if (nevent.item[NEVENT_FLAMES].clock < (CPU_BASECLOCK - CPU_REMCLOCK)) { | 
| (nevent.baseclock - nevent.remainclock)) { |  | 
 | ret ^= 0x20; | ret ^= 0x20; | 
 | } | } | 
 | #endif | #endif | 
| Line 423  static BYTE IOINPCALL gdc_i60(UINT port) | Line 655  static BYTE IOINPCALL gdc_i60(UINT port) | 
 | return(ret); | return(ret); | 
 | } | } | 
 |  |  | 
| static BYTE IOINPCALL gdc_i62(UINT port) { | static REG8 IOINPCALL gdc_i62(UINT port) { | 
 |  |  | 
 | if (gdc.m.snd) { | if (gdc.m.snd) { | 
 | gdc.m.snd--; | gdc.m.snd--; | 
| Line 433  static BYTE IOINPCALL gdc_i62(UINT port) | Line 665  static BYTE IOINPCALL gdc_i62(UINT port) | 
 | return(0xff); | return(0xff); | 
 | } | } | 
 |  |  | 
| static BYTE IOINPCALL gdc_i68(UINT port) { | static REG8 IOINPCALL gdc_i68(UINT port) { | 
 |  |  | 
 | (void)port; | (void)port; | 
 | return(gdc.mode1); | return(gdc.mode1); | 
 | } | } | 
 |  |  | 
| static BYTE IOINPCALL gdc_i6a(UINT port) { | static REG8 IOINPCALL gdc_i6a(UINT port) { | 
 |  |  | 
 | (void)port; | (void)port; | 
 | return(gdc.mode2); | return(gdc.mode2); | 
 | } | } | 
 |  |  | 
 |  |  | 
| static void IOOUTCALL gdc_oa0(UINT port, BYTE dat) { | // ---- I/O slave | 
|  |  | 
|  | static void IOOUTCALL gdc_oa0(UINT port, REG8 dat) { | 
 |  |  | 
 | if (gdc.s.cnt < GDCCMD_MAX) { | if (gdc.s.cnt < GDCCMD_MAX) { | 
 | gdc.s.fifo[gdc.s.cnt++] = dat; | gdc.s.fifo[gdc.s.cnt++] = dat; | 
 | } | } | 
| if (gdc.s.paracb) {                                             // ver0.29 | //      TRACEOUT(("GDC-B %.2x [%.4x:%.4x]", dat, CPU_CS, CPU_IP)); | 
|  | if (gdc.s.paracb) { | 
 | gdc_work(GDCWORK_SLAVE); | gdc_work(GDCWORK_SLAVE); | 
 | } | } | 
 | (void)port; | (void)port; | 
 | } | } | 
 |  |  | 
| static void IOOUTCALL gdc_oa2(UINT port, BYTE dat) { | static void IOOUTCALL gdc_oa2(UINT port, REG8 dat) { | 
 |  |  | 
 | if (gdc.s.cnt < GDCCMD_MAX) { | if (gdc.s.cnt < GDCCMD_MAX) { | 
 | gdc.s.fifo[gdc.s.cnt++] = 0x100 | dat; | gdc.s.fifo[gdc.s.cnt++] = 0x100 | dat; | 
 | } | } | 
 |  | //      TRACEOUT(("GDC-A %.2x", dat)); | 
 | gdc_work(GDCWORK_SLAVE); | gdc_work(GDCWORK_SLAVE); | 
 | (void)port; | (void)port; | 
 | } | } | 
 |  |  | 
| static void IOOUTCALL gdc_oa4(UINT port, BYTE dat) { | static void IOOUTCALL gdc_oa4(UINT port, REG8 dat) { | 
 |  |  | 
 | if ((gdcs.disp ^ dat) & 1) { | if ((gdcs.disp ^ dat) & 1) { | 
 | gdcs.disp = dat & 1; | gdcs.disp = dat & 1; | 
| Line 475  static void IOOUTCALL gdc_oa4(UINT port, | Line 711  static void IOOUTCALL gdc_oa4(UINT port, | 
 | (void)port; | (void)port; | 
 | } | } | 
 |  |  | 
| static void IOOUTCALL gdc_oa6(UINT port, BYTE dat) { | static void IOOUTCALL gdc_oa6(UINT port, REG8 dat) { | 
|  |  | 
| if ((gdcs.access ^ dat) & 1) { |  | 
| gdcs.access = dat & 1; |  | 
| vramop.operate &= VOP_ACCESSMASK; |  | 
| vramop.operate |= gdcs.access; |  | 
| i286_vram_dispatch(vramop.operate); |  | 
| } |  | 
| (void)port; |  | 
| } |  | 
|  |  | 
| static void IOOUTCALL gdc_oa8(UINT port, BYTE dat) { |  | 
|  |  | 
| if (gdc.analog) { |  | 
| gdc.palnum = dat & 0x0f; |  | 
| } |  | 
| else { |  | 
| gdc_setdegpalpack(3, dat); |  | 
| } |  | 
| (void)port; |  | 
| } |  | 
|  |  | 
| static void IOOUTCALL gdc_oaa(UINT port, BYTE dat) { |  | 
|  |  | 
| if (gdc.analog) { |  | 
| gdc_setanalogpal(gdc.palnum, offsetof(RGB32, p.g), dat); |  | 
| } |  | 
| else { |  | 
| gdc_setdegpalpack(1, dat); |  | 
| } |  | 
| (void)port; |  | 
| } |  | 
|  |  | 
| static void IOOUTCALL gdc_oac(UINT port, BYTE dat) { |  | 
 |  |  | 
| if (gdc.analog) { | dat = dat & 1; | 
| gdc_setanalogpal(gdc.palnum, offsetof(RGB32, p.r), dat); | if (gdcs.access != dat) { | 
| } | gdcs.access = (UINT8)dat; | 
| else { | vramop.operate &= ~(1 << VOPBIT_ACCESS); | 
| gdc_setdegpalpack(2, dat); | vramop.operate |= dat << VOPBIT_ACCESS; | 
|  | MEMM_VRAM(vramop.operate); | 
 | } | } | 
 | (void)port; | (void)port; | 
 | } | } | 
 |  |  | 
| static void IOOUTCALL gdc_oae(UINT port, BYTE dat) { | static REG8 IOINPCALL gdc_ia0(UINT port) { | 
 |  |  | 
| if (gdc.analog) { | REG8    ret; | 
| gdc_setanalogpal(gdc.palnum, offsetof(RGB32, p.b), dat); |  | 
| } |  | 
| else { |  | 
| gdc_setdegpalpack(0, dat); |  | 
| } |  | 
| (void)port; |  | 
| } |  | 
|  |  | 
| static BYTE IOINPCALL gdc_ia0(UINT port) { |  | 
|  |  | 
| BYTE    ret; |  | 
 | SINT32  remain; | SINT32  remain; | 
 |  |  | 
 | ret = 0x80 | gdc.vsync | gdc.s_drawing; | ret = 0x80 | gdc.vsync | gdc.s_drawing; | 
 | remain = nevent_getremain(NEVENT_FLAMES); | remain = nevent_getremain(NEVENT_FLAMES); | 
 | if (remain >= 0) { | if (remain >= 0) { | 
| if ((remain % pc.raster) < (pc.hsync)) { | if ((remain % gdc.rasterclock) < (gdc.hsyncclock)) { | 
 | ret |= 0x40; | ret |= 0x40; | 
 | } | } | 
 | } | } | 
| Line 554  static BYTE IOINPCALL gdc_ia0(UINT port) | Line 747  static BYTE IOINPCALL gdc_ia0(UINT port) | 
 | else { | else { | 
 | gdc_work(GDCWORK_SLAVE); | gdc_work(GDCWORK_SLAVE); | 
 | } | } | 
| #ifdef SEARHC_SYNC | #ifdef SEARCH_SYNC | 
| if ((i286reg.inport) && (nevent.remainclock >= 5)) { | if ((CPU_INPADRS) && (CPU_REMCLOCK >= 5)) { | 
| UINT16 jadr = 0xfa74; | UINT32 addr; | 
|  | UINT16 jadr; | 
 | UINT16 memv; | UINT16 memv; | 
| memv = i286_memoryread_w(i286reg.inport); | addr = CPU_INPADRS; | 
|  | jadr = 0xfa74; | 
|  | memv = MEML_READ16(addr); | 
 | while((memv == 0x00eb) || (memv == 0x5fe6)) { | while((memv == 0x00eb) || (memv == 0x5fe6)) { | 
 | jadr -= 0x200; | jadr -= 0x200; | 
| i286reg.inport += 2; | addr += 2; | 
| memv = i286_memoryread_w(i286reg.inport); | memv = MEML_READ16(addr); | 
 | } | } | 
 | if ((memv == 0x20a8) || (memv == 0x2024)) { | if ((memv == 0x20a8) || (memv == 0x2024)) { | 
| memv = i286_memoryread_w(i286reg.inport + 2); | memv = MEML_READ16(addr + 2); | 
 | if (memv == jadr) {                                     // je | if (memv == jadr) {                                     // je | 
 | if (!gdc.vsync) { | if (!gdc.vsync) { | 
| nevent.remainclock = -1; | CPU_REMCLOCK = -1; | 
 | } | } | 
 | } | } | 
 | else if (memv == (jadr + 1)) {          // jne | else if (memv == (jadr + 1)) {          // jne | 
 | if (gdc.vsync) { | if (gdc.vsync) { | 
| nevent.remainclock = -1; | CPU_REMCLOCK = -1; | 
 | } | } | 
 | } | } | 
 | } | } | 
 | } | } | 
 | #endif | #endif | 
 | #ifdef TURE_SYNC                                // クロックイベントの誤差修正 | #ifdef TURE_SYNC                                // クロックイベントの誤差修正 | 
| if (nevent.item[NEVENT_FLAMES].clock < | if (nevent.item[NEVENT_FLAMES].clock < (CPU_BASECLOCK - CPU_REMCLOCK)) { | 
| (nevent.baseclock - nevent.remainclock)) { |  | 
 | ret ^= 0x20; | ret ^= 0x20; | 
 | } | } | 
 | #endif | #endif | 
| Line 589  static BYTE IOINPCALL gdc_ia0(UINT port) | Line 784  static BYTE IOINPCALL gdc_ia0(UINT port) | 
 | return(ret); | return(ret); | 
 | } | } | 
 |  |  | 
| static BYTE IOINPCALL gdc_ia2(UINT port) { | static REG8 IOINPCALL gdc_ia2(UINT port) { | 
 |  |  | 
 | if (gdc.s.snd) { | if (gdc.s.snd) { | 
 | gdc.s.snd--; | gdc.s.snd--; | 
| Line 599  static BYTE IOINPCALL gdc_ia2(UINT port) | Line 794  static BYTE IOINPCALL gdc_ia2(UINT port) | 
 | return(0xff); | return(0xff); | 
 | } | } | 
 |  |  | 
| static BYTE IOINPCALL gdc_ia4(UINT port) { | static REG8 IOINPCALL gdc_ia4(UINT port) { | 
 |  |  | 
 | (void)port; | (void)port; | 
 | return(gdcs.disp); | return(gdcs.disp); | 
 | } | } | 
 |  |  | 
| static BYTE IOINPCALL gdc_ia6(UINT port) { | static REG8 IOINPCALL gdc_ia6(UINT port) { | 
 |  |  | 
 | (void)port; | (void)port; | 
 | return(gdcs.access); | return(gdcs.access); | 
 | } | } | 
 |  |  | 
 |  |  | 
 |  | // ---- I/O palette | 
 |  |  | 
 |  | static void IOOUTCALL gdc_oa8(UINT port, REG8 dat) { | 
 |  |  | 
 |  | if (gdc.analog & ((1 << GDCANALOG_256) + (1 << GDCANALOG_16))) { | 
 |  | gdc.palnum = dat; | 
 |  | } | 
 |  | else { | 
 |  | gdc_setdegpalpack(3, dat); | 
 |  | } | 
 |  | (void)port; | 
 |  | } | 
 |  |  | 
 |  | static void IOOUTCALL gdc_oaa(UINT port, REG8 dat) { | 
 |  |  | 
 |  | #if defined(SUPPORT_PC9821) | 
 |  | if (gdc.analog & (1 << GDCANALOG_256)) { | 
 |  | gdcs.palchange = GDCSCRN_REDRAW; | 
 |  | gdc.anareg[(16 * 3) + (gdc.palnum * 4) + 0] = dat; | 
 |  | } | 
 |  | else | 
 |  | #endif | 
 |  | if (gdc.analog & (1 << GDCANALOG_16)) { | 
 |  | #if defined(SUPPORT_PC9821) | 
 |  | gdc.anareg[(gdc.palnum * 3) + 0] = dat; | 
 |  | #endif | 
 |  | gdc_setanalogpal(gdc.palnum & 15, offsetof(RGB32, p.g), dat); | 
 |  | } | 
 |  | else { | 
 |  | gdc_setdegpalpack(1, dat); | 
 |  | } | 
 |  | (void)port; | 
 |  | } | 
 |  |  | 
 |  | static void IOOUTCALL gdc_oac(UINT port, REG8 dat) { | 
 |  |  | 
 |  | #if defined(SUPPORT_PC9821) | 
 |  | if (gdc.analog & (1 << GDCANALOG_256)) { | 
 |  | gdcs.palchange = GDCSCRN_REDRAW; | 
 |  | gdc.anareg[(16 * 3) + (gdc.palnum * 4) + 1] = dat; | 
 |  | } | 
 |  | else | 
 |  | #endif | 
 |  | if (gdc.analog & (1 << GDCANALOG_16)) { | 
 |  | #if defined(SUPPORT_PC9821) | 
 |  | gdc.anareg[(gdc.palnum * 3) + 1] = dat; | 
 |  | #endif | 
 |  | gdc_setanalogpal(gdc.palnum & 15, offsetof(RGB32, p.r), dat); | 
 |  | } | 
 |  | else { | 
 |  | gdc_setdegpalpack(2, dat); | 
 |  | } | 
 |  | (void)port; | 
 |  | } | 
 |  |  | 
 |  | static void IOOUTCALL gdc_oae(UINT port, REG8 dat) { | 
 |  |  | 
 |  | #if defined(SUPPORT_PC9821) | 
 |  | if (gdc.analog & (1 << GDCANALOG_256)) { | 
 |  | gdcs.palchange = GDCSCRN_REDRAW; | 
 |  | gdc.anareg[(16 * 3) + (gdc.palnum * 4) + 2] = dat; | 
 |  | } | 
 |  | else | 
 |  | #endif | 
 |  | if (gdc.analog & (1 << GDCANALOG_16)) { | 
 |  | #if defined(SUPPORT_PC9821) | 
 |  | gdc.anareg[(gdc.palnum * 3) + 2] = dat; | 
 |  | #endif | 
 |  | gdc_setanalogpal(gdc.palnum & 15, offsetof(RGB32, p.b), dat); | 
 |  | } | 
 |  | else { | 
 |  | gdc_setdegpalpack(0, dat); | 
 |  | } | 
 |  | (void)port; | 
 |  | } | 
 |  |  | 
 |  | #if defined(SUPPORT_PC9821) | 
 |  | static REG8 IOINPCALL gdc_ia8(UINT port) { | 
 |  |  | 
 |  | if (gdc.analog & ((1 << GDCANALOG_256) + (1 << GDCANALOG_16))) { | 
 |  | return(gdc.palnum); | 
 |  | } | 
 |  | (void)port; | 
 |  | return(gdc.degpal[3]); | 
 |  | } | 
 |  |  | 
 |  | static REG8 IOINPCALL gdc_iaa(UINT port) { | 
 |  |  | 
 |  | if (gdc.analog & (1 << GDCANALOG_256)) { | 
 |  | return(gdc.anareg[(16 * 3) + (gdc.palnum * 4) + 0]); | 
 |  | } | 
 |  | if (gdc.analog & (1 << GDCANALOG_16)) { | 
 |  | return(gdc.anareg[(gdc.palnum * 3) + 0]); | 
 |  | } | 
 |  | (void)port; | 
 |  | return(gdc.degpal[1]); | 
 |  | } | 
 |  |  | 
 |  | static REG8 IOINPCALL gdc_iac(UINT port) { | 
 |  |  | 
 |  | if (gdc.analog & (1 << GDCANALOG_256)) { | 
 |  | return(gdc.anareg[(16 * 3) + (gdc.palnum * 4) + 1]); | 
 |  | } | 
 |  | if (gdc.analog & (1 << GDCANALOG_16)) { | 
 |  | return(gdc.anareg[(gdc.palnum * 3) + 1]); | 
 |  | } | 
 |  | (void)port; | 
 |  | return(gdc.degpal[2]); | 
 |  | } | 
 |  |  | 
 |  | static REG8 IOINPCALL gdc_iae(UINT port) { | 
 |  |  | 
 |  | if (gdc.analog & (1 << GDCANALOG_256)) { | 
 |  | return(gdc.anareg[(16 * 3) + (gdc.palnum * 4) + 2]); | 
 |  | } | 
 |  | if (gdc.analog & (1 << GDCANALOG_16)) { | 
 |  | return(gdc.anareg[(gdc.palnum * 3) + 2]); | 
 |  | } | 
 |  | (void)port; | 
 |  | return(gdc.degpal[0]); | 
 |  | } | 
 |  | #endif | 
 |  |  | 
 |  |  | 
 |  | // ---- extend | 
 |  |  | 
 |  | #if defined(SUPPORT_PC9821) | 
 |  | static void IOOUTCALL gdc_o9a0(UINT port, REG8 dat) { | 
 |  |  | 
 |  | gdc.ff2 = dat; | 
 |  | (void)port; | 
 |  | } | 
 |  |  | 
 |  | static REG8 IOINPCALL gdc_i9a0(UINT port) { | 
 |  |  | 
 |  | REG8    ret; | 
 |  |  | 
 |  | ret = 0; | 
 |  | switch(gdc.ff2) { | 
 |  | case 0x00: | 
 |  | ret = 0xff; | 
 |  | break; | 
 |  |  | 
 |  | case 0x01: | 
 |  | ret = (gdc.mode1 >> 1) & 1; | 
 |  | break; | 
 |  |  | 
 |  | case 0x02: | 
 |  | ret = (gdc.mode1 >> 4) & 1; | 
 |  | break; | 
 |  |  | 
 |  | case 0x03: | 
 |  | ret = (gdc.mode1 >> 7) & 1; | 
 |  | break; | 
 |  |  | 
 |  | case 0x04: | 
 |  | ret = (gdc.mode2 >> 0) & 1; | 
 |  | break; | 
 |  |  | 
 |  | case 0x05: | 
 |  | ret = (gdc.display >> GDCDISP_PLAZMA) & 1; | 
 |  | break; | 
 |  |  | 
 |  | case 0x07: | 
 |  | ret = (gdc.mode2 >> 2) & 1; | 
 |  | break; | 
 |  |  | 
 |  | case 0x08: | 
 |  | ret = (gdc.mode2 >> 3) & 1; | 
 |  | break; | 
 |  |  | 
 |  | case 0x09: | 
 |  | ret = (gdc.clock >> 0) & 1; | 
 |  | break; | 
 |  |  | 
 |  | case 0x0a: | 
 |  | ret = (gdc.analog >> GDCANALOG_256) & 1; | 
 |  | break; | 
 |  |  | 
 |  | case 0x0b: | 
 |  | ret = 1; | 
 |  | break; | 
 |  |  | 
 |  | case 0x0d: | 
 |  | ret = (gdc.analog >> GDCANALOG_256E) & 1; | 
 |  | break; | 
 |  | } | 
 |  | ret |= (gdc.clock & 2); | 
 |  | (void)port; | 
 |  | return(ret); | 
 |  | } | 
 |  | #endif | 
 |  |  | 
 |  | #if defined(SUPPORT_CRT31KHZ) | 
 |  | static void IOOUTCALL gdc_o9a8(UINT port, REG8 dat) { | 
 |  |  | 
 |  | if ((gdc.display ^ (dat << GDCDISP_31)) & (1 << GDCDISP_31)) { | 
 |  | gdc.display ^= (1 << GDCDISP_31); | 
 |  | gdcs.textdisp |= GDCSCRN_EXT; | 
 |  | } | 
 |  | (void)port; | 
 |  | } | 
 |  |  | 
 |  | static REG8 IOINPCALL gdc_i9a8(UINT port) { | 
 |  |  | 
 |  | (void)port; | 
 |  | return((gdc.display >> GDCDISP_31) & 1); | 
 |  | } | 
 |  | #endif | 
 |  |  | 
 |  |  | 
 | // ---- I/F | // ---- I/F | 
 |  |  | 
 | static const IOOUT gdco60[8] = { | static const IOOUT gdco60[8] = { | 
 | gdc_o60,        gdc_o62,        gdc_o64,        NULL, | gdc_o60,        gdc_o62,        gdc_o64,        NULL, | 
| gdc_o68,        gdc_o6a,        NULL,           NULL}; | gdc_o68,        gdc_o6a,        NULL,           gdc_o6e}; | 
 |  |  | 
 | static const IOOUT gdcoa0[8] = { | static const IOOUT gdcoa0[8] = { | 
 | gdc_oa0,        gdc_oa2,        gdc_oa4,        gdc_oa6, | gdc_oa0,        gdc_oa2,        gdc_oa4,        gdc_oa6, | 
| Line 626  static const IOINP gdci60[8] = { | Line 1032  static const IOINP gdci60[8] = { | 
 | gdc_i60,        gdc_i62,        NULL,           NULL, | gdc_i60,        gdc_i62,        NULL,           NULL, | 
 | gdc_i68,        gdc_i6a,        NULL,           NULL}; | gdc_i68,        gdc_i6a,        NULL,           NULL}; | 
 |  |  | 
 |  | #if defined(SUPPORT_PC9821) | 
 |  | static const IOINP gdcia0[8] = { | 
 |  | gdc_ia0,        gdc_ia2,        gdc_ia4,        gdc_ia6, | 
 |  | gdc_ia8,        gdc_iaa,        gdc_iac,        gdc_iae}; | 
 |  | #else | 
 | static const IOINP gdcia0[8] = { | static const IOINP gdcia0[8] = { | 
 | gdc_ia0,        gdc_ia2,        gdc_ia4,        gdc_ia6, | gdc_ia0,        gdc_ia2,        gdc_ia4,        gdc_ia6, | 
 | NULL,           NULL,           NULL,           NULL}; | NULL,           NULL,           NULL,           NULL}; | 
 |  | #endif | 
 |  |  | 
 | void gdc_reset(void) { |  | 
 |  |  | 
| ZeroMemory(&gdc, sizeof(gdc)); | void gdc_biosreset(void) { | 
| ZeroMemory(&gdcs, sizeof(gdcs)); |  | 
 |  |  | 
| gdc.mode1 = 0x98; | #if defined(SUPPORT_PC9821) | 
|  | UINT    i; | 
|  | UINT    j; | 
|  | UINT8   tmp; | 
|  | UINT8   *pal; | 
|  | #endif | 
 |  |  | 
| gdc.m.para[GDC_CSRFORM + 0] = 0x0f; | if (!(np2cfg.dipsw[0] & 0x01)) { | 
| gdc.m.para[GDC_CSRFORM + 1] = 0xc0; | gdc.mode1 = 0x98; | 
| gdc.m.para[GDC_CSRFORM + 2] = 0x7b; | gdc.m.para[GDC_CSRFORM + 0] = 0x0f; | 
| CopyMemory(gdc.m.para + GDC_SYNC, defsync, 8); | gdc.m.para[GDC_CSRFORM + 1] = 0xc0; | 
| CopyMemory(gdc.s.para + GDC_SYNC, defsync, 8); | gdc.m.para[GDC_CSRFORM + 2] = 0x7b; | 
|  | CopyMemory(gdc.m.para + GDC_SYNC, defsyncm24, 8); | 
|  | gdc.s.para[GDC_CSRFORM + 0] = 1; | 
|  | CopyMemory(gdc.s.para + GDC_SYNC, defsyncs24, 8); | 
|  | } | 
|  | else { | 
|  | gdc.crt15khz = 3; | 
|  | gdc.mode1 = 0x80; | 
|  | gdc.m.para[GDC_CSRFORM + 0] = 0x07; | 
|  | gdc.m.para[GDC_CSRFORM + 1] = 0xc0; | 
|  | gdc.m.para[GDC_CSRFORM + 2] = 0x3b; | 
|  | CopyMemory(gdc.m.para + GDC_SYNC, defsyncm15, 8); | 
|  | CopyMemory(gdc.s.para + GDC_SYNC, defsyncs15, 8); | 
|  | } | 
|  | if (np2cfg.dipsw[0] & 0x80) { | 
|  | gdc.s.para[GDC_SYNC] = 0x16; | 
|  | } | 
|  | gdc_vectreset(&gdc.m); | 
|  | gdc_vectreset(&gdc.s); | 
 |  |  | 
 | gdc.s.para[GDC_CSRFORM] = 1; |  | 
 | gdc.clock = 0; | gdc.clock = 0; | 
| gdc.m.para[GDC_PITCH] = 80;                                     // ver0.26 | gdc.m.para[GDC_PITCH] = 80; | 
 | gdc.s.para[GDC_PITCH] = 40; | gdc.s.para[GDC_PITCH] = 40; | 
 |  |  | 
| gdc_paletteinit(); | gdc.bitac = 0xff; | 
 |  |  | 
| gdcs.textdisp = GDCSCRN_ENABLE | GDCSCRN_ALLDRAW2 | GDCSCRN_EXT; | // vram bank | 
|  | gdcs.disp = 0; | 
|  | gdcs.access = 0; | 
|  | gdc.analog &= ~(1 << GDCANALOG_16); | 
|  | gdcs.palchange = GDCSCRN_REDRAW; | 
|  |  | 
|  | gdc.mode2 &= ~(1 << 0); | 
|  | gdc.mode2 &= ~(1 << 2); | 
|  | gdc.mode2 &= ~(1 << 3); | 
|  | gdcs.mode2 = gdc.mode2; | 
|  |  | 
|  | vramop.operate &= ~(1 << VOPBIT_ACCESS); | 
|  | vramop.operate &= ~(1 << VOPBIT_EGC); | 
|  | vramop.operate &= ~(1 << VOPBIT_ANALOG); | 
|  | #if defined(SUPPORT_PC9821) | 
|  | gdc.analog &= ~(1 << (GDCANALOG_256)); | 
|  | vramop.operate &= ~(1 << VOPBIT_VGA); | 
|  | #endif | 
|  | MEMM_VRAM(vramop.operate); | 
|  |  | 
|  | // palette | 
|  | CopyMemory(gdc.degpal, defdegpal, 4); | 
|  | if (gdc.display & (1 << GDCDISP_ANALOG)) { | 
|  | gdc_setanalogpalall(defanapal); | 
|  | } | 
|  | #if defined(SUPPORT_PC9821) | 
|  | pal = gdc.anareg + (16 * 3); | 
|  | for (i=0; i<256; i+=8) { | 
|  | tmp = (UINT8)((i)?(i - 4):0); | 
|  | pal[0] = tmp; | 
|  | pal[1] = tmp; | 
|  | pal[2] = tmp; | 
|  | pal += 4; | 
|  | for (j=1; j<8; j++) { | 
|  | pal[0] = (UINT8)((i + 7) * ((j >> 2) & 1)); | 
|  | pal[1] = (UINT8)((i + 7) * ((j >> 1) & 1)); | 
|  | pal[2] = (UINT8)((i + 7) * ((j >> 0) & 1)); | 
|  | pal += 4; | 
|  | } | 
|  | } | 
|  | #endif | 
|  | gdcs.textdisp = GDCSCRN_ALLDRAW2 | GDCSCRN_EXT; | 
 | gdcs.grphdisp = GDCSCRN_ALLDRAW2 | GDCSCRN_EXT; | gdcs.grphdisp = GDCSCRN_ALLDRAW2 | GDCSCRN_EXT; | 
| gdc.display = (np2cfg.color16 & 1) << 1; | gdcs.palchange = GDCSCRN_REDRAW; | 
| gdc.bitac = 0xff; | screenupdate |= 2; | 
|  | } | 
|  |  | 
|  | void gdc_reset(const NP2CFG *pConfig) { | 
|  |  | 
|  | ZeroMemory(&gdc, sizeof(gdc)); | 
|  | ZeroMemory(&gdcs, sizeof(gdcs)); | 
|  |  | 
|  | #if defined(SUPPORT_PC9821) | 
|  | gdc.display |= (1 << GDCDISP_ANALOG); | 
|  | #else | 
|  | if (np2cfg.color16 & 1) { | 
|  | gdc.display |= (1 << GDCDISP_ANALOG); | 
|  | } | 
|  | #endif | 
|  | if (!(np2cfg.dipsw[0] & 0x04)) {                        // dipsw1-3 on | 
|  | gdc.display |= (1 << GDCDISP_PLAZMA2); | 
|  | } | 
|  | gdc_biosreset(); | 
|  |  | 
|  | (void)pConfig; | 
 | } | } | 
 |  |  | 
 | void gdc_bind(void) { | void gdc_bind(void) { | 
 |  |  | 
 |  | gdc_updateclock(); | 
 |  | #if defined(SUPPORT_PC9821) | 
 |  | iocore_attachout(0x09a0, gdc_o9a0); | 
 |  | iocore_attachinp(0x09a0, gdc_i9a0); | 
 |  | #endif | 
 |  | #if defined(SUPPORT_CRT31KHZ) | 
 |  | iocore_attachout(0x09a8, gdc_o9a8); | 
 |  | iocore_attachinp(0x09a8, gdc_i9a8); | 
 |  | #endif | 
 | iocore_attachsysoutex(0x0060, 0x0cf1, gdco60, 8); | iocore_attachsysoutex(0x0060, 0x0cf1, gdco60, 8); | 
 | iocore_attachsysinpex(0x0060, 0x0cf1, gdci60, 8); | iocore_attachsysinpex(0x0060, 0x0cf1, gdci60, 8); | 
 | iocore_attachsysoutex(0x00a0, 0x0cf1, gdcoa0, 8); | iocore_attachsysoutex(0x00a0, 0x0cf1, gdcoa0, 8); |