--- np2/io/gdc.c	2004/02/19 06:10:13	1.21
+++ np2/io/gdc.c	2004/02/26 08:44:32	1.23
@@ -3,9 +3,10 @@
 #include	"cpucore.h"
 #include	"pccore.h"
 #include	"iocore.h"
+#include	"gdc_cmd.tbl"
+#include	"gdc_sub.h"
 #include	"vram.h"
 #include	"palettes.h"
-#include	"gdc_cmd.tbl"
 #include	"timing.h"
 
 
@@ -20,13 +21,17 @@ typedef struct {
 	UINT	maxy;
 } GDCCLK;
 
+// 31kHzの時の動作クロックが不明…
 static const GDCCLK gdcclk[] = {
 			{14318180 / 8, 112 - 8, 112 + 8, 200, 300},
 			{21052600 / 8, 106 - 6, 106 + 6, 400, 575},
-			{25056815 / 8, 106 - 6, 106 + 6, 400, 575},
-			{25175000 / 8, 100 - 4, 100 + 4, 400, 575}};
+			{25260000 / 8, 100 - 8, 100 + 8, 400, 575}};
 
-static const UINT8 defdegpal[4] = {0x04,0x15,0x26,0x37};
+
+typedef struct {
+	UINT8	master[8];
+	UINT8	slave[8];
+} GDCSYNC;
 
 static const UINT8 defsyncm15[8] = {0x10,0x4e,0x07,0x25,0x0d,0x0f,0xc8,0x94};
 static const UINT8 defsyncs15[8] = {0x06,0x26,0x03,0x11,0x86,0x0f,0xc8,0x94};
@@ -34,6 +39,14 @@ static const UINT8 defsyncs15[8] = {0x06
 static const UINT8 defsyncm24[8] = {0x10,0x4e,0x07,0x25,0x07,0x07,0x90,0x65};
 static const UINT8 defsyncs24[8] = {0x06,0x26,0x03,0x11,0x83,0x07,0x90,0x65};
 
+static const UINT8 defsyncm31[8] = {0x10,0x4e,0x47,0x0c,0x07,0x0d,0x90,0x89};
+static const UINT8 defsyncs31[8] = {0x06,0x26,0x41,0x0c,0x83,0x0d,0x90,0x89};
+
+
+static const UINT8 defdegpal[4] = {0x04,0x15,0x26,0x37};
+
+
+
 
 void gdc_setdegitalpal(int color, REG8 value) {
 
@@ -279,8 +292,13 @@ void gdc_work(int id) {
 }
 
 // BIOSとかで弄った時にリセット
-void gdc_forceready(GDCDATA item) {
+void gdc_forceready(int id) {
 
+	GDCDATA	item;
+	item = (id == GDCWORK_MASTER)?&gdc.m:&gdc.s;
+	if (item->cnt) {
+		gdc_work(id);
+	}
 	item->rcv = 0;
 	item->snd = 0;
 }