--- np2/io/gdc.c 2004/02/21 00:25:33 1.22 +++ np2/io/gdc.c 2005/05/20 13:59:47 1.38 @@ -9,8 +9,9 @@ #include "palettes.h" #include "timing.h" - +#if !defined(CPUCORE_IA32) #define SEARCH_SYNC +#endif #define TURE_SYNC typedef struct { @@ -21,13 +22,17 @@ typedef struct { UINT maxy; } GDCCLK; +// 31kHzの時の動作クロックが不明… static const GDCCLK gdcclk[] = { {14318180 / 8, 112 - 8, 112 + 8, 200, 300}, {21052600 / 8, 106 - 6, 106 + 6, 400, 575}, - {25056815 / 8, 106 - 6, 106 + 6, 400, 575}, - {25175000 / 8, 100 - 4, 100 + 4, 400, 575}}; + {25260000 / 8, 100 - 8, 100 + 8, 400, 575}}; -static const UINT8 defdegpal[4] = {0x04,0x15,0x26,0x37}; + +typedef struct { + UINT8 master[8]; + UINT8 slave[8]; +} GDCSYNC; static const UINT8 defsyncm15[8] = {0x10,0x4e,0x07,0x25,0x0d,0x0f,0xc8,0x94}; static const UINT8 defsyncs15[8] = {0x06,0x26,0x03,0x11,0x86,0x0f,0xc8,0x94}; @@ -35,6 +40,15 @@ static const UINT8 defsyncs15[8] = {0x06 static const UINT8 defsyncm24[8] = {0x10,0x4e,0x07,0x25,0x07,0x07,0x90,0x65}; static const UINT8 defsyncs24[8] = {0x06,0x26,0x03,0x11,0x83,0x07,0x90,0x65}; +static const UINT8 defsyncm31[8] = {0x10,0x4e,0x47,0x0c,0x07,0x0d,0x90,0x89}; +static const UINT8 defsyncs31[8] = {0x06,0x26,0x41,0x0c,0x83,0x0d,0x90,0x89}; + + +static const UINT8 defdegpal[4] = {0x04,0x15,0x26,0x37}; +static const UINT16 defanapal[16] = { + 0x000,0x007,0x070,0x077,0x700,0x707,0x770,0x777, + 0x444,0x00f,0x0f0,0x0ff,0xf00,0xf0f,0xff0,0xfff}; + void gdc_setdegitalpal(int color, REG8 value) { @@ -58,6 +72,14 @@ void gdc_setdegitalpal(int color, REG8 v } } +void gdc_setdegpalpack(int color, REG8 value) { + + if ((gdc.degpal[color] ^ value) & 0x77) { + gdcs.palchange = GDCSCRN_REDRAW; + } + gdc.degpal[color] = (UINT8)value; +} + void gdc_setanalogpal(int color, int rgb, REG8 value) { UINT8 *ptr; @@ -83,14 +105,25 @@ void gdc_setanalogpal(int color, int rgb *ptr = value; } -void gdc_setdegpalpack(int color, REG8 value) { +void gdc_setanalogpalall(const UINT16 *paltbl) { - if ((gdc.degpal[color] ^ value) & 0x77) { - gdcs.palchange = GDCSCRN_REDRAW; + UINT c; + UINT pal; + + for (c=0; c<16; c++) { + pal = *paltbl++; +#if defined(SUPPORT_PC9821) + gdc.anareg[(c * 3) + 0] = (pal >> 8) & 15; + gdc.anareg[(c * 3) + 1] = (pal >> 4) & 15; + gdc.anareg[(c * 3) + 2] = (pal >> 0) & 15; +#endif + gdc_setanalogpal(c, offsetof(RGB32, p.g), (REG8)((pal >> 8) & 15)); + gdc_setanalogpal(c, offsetof(RGB32, p.r), (REG8)((pal >> 4) & 15)); + gdc_setanalogpal(c, offsetof(RGB32, p.b), (REG8)((pal >> 0) & 15)); } - gdc.degpal[color] = (UINT8)value; } + void gdc_paletteinit(void) { int c; @@ -110,6 +143,23 @@ void gdc_paletteinit(void) { gdcs.palchange = GDCSCRN_REDRAW; } +#if defined(SUPPORT_PC9821) +void gdc_analogext(BOOL extend) { + + if (extend) { + gdc.analog |= (1 << GDCANALOG_256); + vramop.operate |= (1 << VOPBIT_VGA); + } + else { + gdc.analog &= ~(1 << (GDCANALOG_256)); + vramop.operate &= ~(1 << VOPBIT_VGA); + } + gdcs.palchange = GDCSCRN_REDRAW; + gdcs.grphdisp |= GDCSCRN_EXT | GDCSCRN_ALLDRAW2; + MEMM_VRAM(vramop.operate); +} +#endif + // -------------------------------------------------------------------------- @@ -324,6 +374,12 @@ const GDCCLK *clk; y = lf + vfbs; // TRACEOUT(("h %d:%d / v %d:%d", cr, x, lf, y)); +#if defined(SUPPORT_CRT31KHZ) + if (gdc.display & (1 << GDCDISP_31)) { + clk = gdcclk + 2; + } + else +#endif if (!(gdc.crt15khz & 2)) { // 24.83±300Hz clk = gdcclk + 1; } @@ -348,6 +404,8 @@ const GDCCLK *clk; y = clk->maxy; } hclock = clk->clock / x; + gdc.hclock = hclock; + gdc.vclock = hclock * 10 / y; cnt = (pccore.baseclock * y) / hclock; cnt *= pccore.multiple; gdc.rasterclock = cnt / y; @@ -359,7 +417,7 @@ const GDCCLK *clk; void gdc_restorekacmode(void) { - BYTE bit; + UINT8 bit; bit = (((!np2cfg.uPD72020) && (gdc.mode1 & 0x20))?0x00:0xff); if (gdc.bitac != bit) { @@ -369,7 +427,7 @@ void gdc_restorekacmode(void) { } -// ---- I/O +// ---- I/O master static void IOOUTCALL gdc_o60(UINT port, REG8 dat) { @@ -441,20 +499,21 @@ static void IOOUTCALL gdc_o6a(UINT port, gdc.mode2 ^= (1 << bit); switch(bit) { case 0: - if (gdc.display & 2) { - gdc.analog = dat; + if (gdc.display & (1 << GDCDISP_ANALOG)) { + gdc.analog &= ~(1 << GDCANALOG_16); + gdc.analog |= (dat << GDCANALOG_16); gdcs.palchange = GDCSCRN_REDRAW; - vramop.operate &= VOP_ANALOGMASK; - vramop.operate |= dat << 4; - i286_vram_dispatch(vramop.operate); + vramop.operate &= ~(1 << VOPBIT_ANALOG); + vramop.operate |= dat << VOPBIT_ANALOG; + MEMM_VRAM(vramop.operate); } break; case 2: if ((gdc.mode2 & 0x08) && (grcg.chip == 3)) { - vramop.operate &= VOP_EGCMASK; - vramop.operate |= dat << 1; - i286_vram_dispatch(vramop.operate); + vramop.operate &= ~(1 << VOPBIT_EGC); + vramop.operate |= dat << VOPBIT_EGC; + MEMM_VRAM(vramop.operate); } break; } @@ -462,15 +521,36 @@ static void IOOUTCALL gdc_o6a(UINT port, } else { switch(dat) { +#if defined(SUPPORT_PC9821) + case 0x20: + if (gdc.mode2 & 0x08) { + gdc_analogext(FALSE); + } + break; + + case 0x21: + if (gdc.mode2 & 0x08) { + gdc_analogext(TRUE); + } + break; + + case 0x68: + gdc.analog &= ~(1 << GDCANALOG_256E); + break; + + case 0x69: + gdc.analog |= (1 << GDCANALOG_256E); + break; +#endif case 0x40: case 0x80: // EPSON? - gdc.display &= ~1; + gdc.display &= ~(1 << GDCDISP_PLAZMA); gdcs.textdisp |= GDCSCRN_EXT; break; case 0x41: case 0x81: // EPSON? - gdc.display |= 1; + gdc.display |= (1 << GDCDISP_PLAZMA); gdcs.textdisp |= GDCSCRN_EXT; break; @@ -538,18 +618,21 @@ static REG8 IOINPCALL gdc_i60(UINT port) else { gdc_work(GDCWORK_MASTER); } -#ifdef SEARCH_SYNC +#ifdef SEARCH_SYNC // ToDo: フェッチキューを参照するように… if ((CPU_INPADRS) && (CPU_REMCLOCK >= 5)) { - UINT16 jadr = 0xfa74; + UINT32 addr; + UINT16 jadr; UINT16 memv; - memv = i286_memoryread_w(CPU_INPADRS); + addr = CPU_INPADRS; + jadr = 0xfa74; + memv = MEML_READ16(addr); while((memv == 0x00eb) || (memv == 0x5fe6)) { jadr -= 0x200; - CPU_INPADRS += 2; - memv = i286_memoryread_w(CPU_INPADRS); + addr += 2; + memv = MEML_READ16(addr); } if ((memv == 0x20a8) || (memv == 0x2024)) { - memv = i286_memoryread_w(CPU_INPADRS + 2); + memv = MEML_READ16(addr + 2); if (memv == jadr) { // je if (!gdc.vsync) { CPU_REMCLOCK = -1; @@ -595,6 +678,8 @@ static REG8 IOINPCALL gdc_i6a(UINT port) } +// ---- I/O slave + static void IOOUTCALL gdc_oa0(UINT port, REG8 dat) { if (gdc.s.cnt < GDCCMD_MAX) { @@ -628,55 +713,12 @@ static void IOOUTCALL gdc_oa4(UINT port, static void IOOUTCALL gdc_oa6(UINT port, REG8 dat) { - if ((gdcs.access ^ dat) & 1) { - gdcs.access = dat & 1; - vramop.operate &= VOP_ACCESSMASK; - vramop.operate |= gdcs.access; - i286_vram_dispatch(vramop.operate); - } - (void)port; -} - -static void IOOUTCALL gdc_oa8(UINT port, REG8 dat) { - - if (gdc.analog) { - gdc.palnum = dat & 0x0f; - } - else { - gdc_setdegpalpack(3, dat); - } - (void)port; -} - -static void IOOUTCALL gdc_oaa(UINT port, REG8 dat) { - - if (gdc.analog) { - gdc_setanalogpal(gdc.palnum, offsetof(RGB32, p.g), dat); - } - else { - gdc_setdegpalpack(1, dat); - } - (void)port; -} - -static void IOOUTCALL gdc_oac(UINT port, REG8 dat) { - - if (gdc.analog) { - gdc_setanalogpal(gdc.palnum, offsetof(RGB32, p.r), dat); - } - else { - gdc_setdegpalpack(2, dat); - } - (void)port; -} - -static void IOOUTCALL gdc_oae(UINT port, REG8 dat) { - - if (gdc.analog) { - gdc_setanalogpal(gdc.palnum, offsetof(RGB32, p.b), dat); - } - else { - gdc_setdegpalpack(0, dat); + dat = dat & 1; + if (gdcs.access != dat) { + gdcs.access = (UINT8)dat; + vramop.operate &= ~(1 << VOPBIT_ACCESS); + vramop.operate |= dat << VOPBIT_ACCESS; + MEMM_VRAM(vramop.operate); } (void)port; } @@ -707,16 +749,19 @@ static REG8 IOINPCALL gdc_ia0(UINT port) } #ifdef SEARCH_SYNC if ((CPU_INPADRS) && (CPU_REMCLOCK >= 5)) { - UINT16 jadr = 0xfa74; + UINT32 addr; + UINT16 jadr; UINT16 memv; - memv = i286_memoryread_w(CPU_INPADRS); + addr = CPU_INPADRS; + jadr = 0xfa74; + memv = MEML_READ16(addr); while((memv == 0x00eb) || (memv == 0x5fe6)) { jadr -= 0x200; - CPU_INPADRS += 2; - memv = i286_memoryread_w(CPU_INPADRS); + addr += 2; + memv = MEML_READ16(addr); } if ((memv == 0x20a8) || (memv == 0x2024)) { - memv = i286_memoryread_w(CPU_INPADRS + 2); + memv = MEML_READ16(addr + 2); if (memv == jadr) { // je if (!gdc.vsync) { CPU_REMCLOCK = -1; @@ -762,6 +807,217 @@ static REG8 IOINPCALL gdc_ia6(UINT port) } +// ---- I/O palette + +static void IOOUTCALL gdc_oa8(UINT port, REG8 dat) { + + if (gdc.analog & ((1 << GDCANALOG_256) + (1 << GDCANALOG_16))) { + gdc.palnum = dat; + } + else { + gdc_setdegpalpack(3, dat); + } + (void)port; +} + +static void IOOUTCALL gdc_oaa(UINT port, REG8 dat) { + +#if defined(SUPPORT_PC9821) + if (gdc.analog & (1 << GDCANALOG_256)) { + gdcs.palchange = GDCSCRN_REDRAW; + gdc.anareg[(16 * 3) + (gdc.palnum * 4) + 0] = dat; + } + else +#endif + if (gdc.analog & (1 << GDCANALOG_16)) { +#if defined(SUPPORT_PC9821) + gdc.anareg[(gdc.palnum * 3) + 0] = dat; +#endif + gdc_setanalogpal(gdc.palnum & 15, offsetof(RGB32, p.g), dat); + } + else { + gdc_setdegpalpack(1, dat); + } + (void)port; +} + +static void IOOUTCALL gdc_oac(UINT port, REG8 dat) { + +#if defined(SUPPORT_PC9821) + if (gdc.analog & (1 << GDCANALOG_256)) { + gdcs.palchange = GDCSCRN_REDRAW; + gdc.anareg[(16 * 3) + (gdc.palnum * 4) + 1] = dat; + } + else +#endif + if (gdc.analog & (1 << GDCANALOG_16)) { +#if defined(SUPPORT_PC9821) + gdc.anareg[(gdc.palnum * 3) + 1] = dat; +#endif + gdc_setanalogpal(gdc.palnum & 15, offsetof(RGB32, p.r), dat); + } + else { + gdc_setdegpalpack(2, dat); + } + (void)port; +} + +static void IOOUTCALL gdc_oae(UINT port, REG8 dat) { + +#if defined(SUPPORT_PC9821) + if (gdc.analog & (1 << GDCANALOG_256)) { + gdcs.palchange = GDCSCRN_REDRAW; + gdc.anareg[(16 * 3) + (gdc.palnum * 4) + 2] = dat; + } + else +#endif + if (gdc.analog & (1 << GDCANALOG_16)) { +#if defined(SUPPORT_PC9821) + gdc.anareg[(gdc.palnum * 3) + 2] = dat; +#endif + gdc_setanalogpal(gdc.palnum & 15, offsetof(RGB32, p.b), dat); + } + else { + gdc_setdegpalpack(0, dat); + } + (void)port; +} + +#if defined(SUPPORT_PC9821) +static REG8 IOINPCALL gdc_ia8(UINT port) { + + if (gdc.analog & ((1 << GDCANALOG_256) + (1 << GDCANALOG_16))) { + return(gdc.palnum); + } + (void)port; + return(gdc.degpal[3]); +} + +static REG8 IOINPCALL gdc_iaa(UINT port) { + + if (gdc.analog & (1 << GDCANALOG_256)) { + return(gdc.anareg[(16 * 3) + (gdc.palnum * 4) + 0]); + } + if (gdc.analog & (1 << GDCANALOG_16)) { + return(gdc.anareg[(gdc.palnum * 3) + 0]); + } + (void)port; + return(gdc.degpal[1]); +} + +static REG8 IOINPCALL gdc_iac(UINT port) { + + if (gdc.analog & (1 << GDCANALOG_256)) { + return(gdc.anareg[(16 * 3) + (gdc.palnum * 4) + 1]); + } + if (gdc.analog & (1 << GDCANALOG_16)) { + return(gdc.anareg[(gdc.palnum * 3) + 1]); + } + (void)port; + return(gdc.degpal[2]); +} + +static REG8 IOINPCALL gdc_iae(UINT port) { + + if (gdc.analog & (1 << GDCANALOG_256)) { + return(gdc.anareg[(16 * 3) + (gdc.palnum * 4) + 2]); + } + if (gdc.analog & (1 << GDCANALOG_16)) { + return(gdc.anareg[(gdc.palnum * 3) + 2]); + } + (void)port; + return(gdc.degpal[0]); +} +#endif + + +// ---- extend + +#if defined(SUPPORT_PC9821) +static void IOOUTCALL gdc_o9a0(UINT port, REG8 dat) { + + gdc.ff2 = dat; + (void)port; +} + +static REG8 IOINPCALL gdc_i9a0(UINT port) { + + REG8 ret; + + ret = 0; + switch(gdc.ff2) { + case 0x00: + ret = 0xff; + break; + + case 0x01: + ret = (gdc.mode1 >> 1) & 1; + break; + + case 0x02: + ret = (gdc.mode1 >> 4) & 1; + break; + + case 0x03: + ret = (gdc.mode1 >> 7) & 1; + break; + + case 0x04: + ret = (gdc.mode2 >> 0) & 1; + break; + + case 0x05: + ret = (gdc.display >> GDCDISP_PLAZMA) & 1; + break; + + case 0x07: + ret = (gdc.mode2 >> 2) & 1; + break; + + case 0x08: + ret = (gdc.mode2 >> 3) & 1; + break; + + case 0x09: + ret = (gdc.clock >> 0) & 1; + break; + + case 0x0a: + ret = (gdc.analog >> GDCANALOG_256) & 1; + break; + + case 0x0b: + ret = 1; + break; + + case 0x0d: + ret = (gdc.analog >> GDCANALOG_256E) & 1; + break; + } + ret |= (gdc.clock & 2); + (void)port; + return(ret); +} +#endif + +#if defined(SUPPORT_CRT31KHZ) +static void IOOUTCALL gdc_o9a8(UINT port, REG8 dat) { + + if ((gdc.display ^ (dat << GDCDISP_31)) & (1 << GDCDISP_31)) { + gdc.display ^= (1 << GDCDISP_31); + gdcs.textdisp |= GDCSCRN_EXT; + } + (void)port; +} + +static REG8 IOINPCALL gdc_i9a8(UINT port) { + + (void)port; + return((gdc.display >> GDCDISP_31) & 1); +} +#endif + + // ---- I/F static const IOOUT gdco60[8] = { @@ -776,14 +1032,25 @@ static const IOINP gdci60[8] = { gdc_i60, gdc_i62, NULL, NULL, gdc_i68, gdc_i6a, NULL, NULL}; +#if defined(SUPPORT_PC9821) +static const IOINP gdcia0[8] = { + gdc_ia0, gdc_ia2, gdc_ia4, gdc_ia6, + gdc_ia8, gdc_iaa, gdc_iac, gdc_iae}; +#else static const IOINP gdcia0[8] = { gdc_ia0, gdc_ia2, gdc_ia4, gdc_ia6, NULL, NULL, NULL, NULL}; +#endif -void gdc_reset(void) { - ZeroMemory(&gdc, sizeof(gdc)); - ZeroMemory(&gdcs, sizeof(gdcs)); +void gdc_biosreset(void) { + +#if defined(SUPPORT_PC9821) + UINT i; + UINT j; + UINT8 tmp; + UINT8 *pal; +#endif if (!(np2cfg.dipsw[0] & 0x01)) { gdc.mode1 = 0x98; @@ -803,6 +1070,9 @@ void gdc_reset(void) { CopyMemory(gdc.m.para + GDC_SYNC, defsyncm15, 8); CopyMemory(gdc.s.para + GDC_SYNC, defsyncs15, 8); } + if (np2cfg.dipsw[0] & 0x80) { + gdc.s.para[GDC_SYNC] = 0x16; + } gdc_vectreset(&gdc.m); gdc_vectreset(&gdc.s); @@ -810,20 +1080,84 @@ void gdc_reset(void) { gdc.m.para[GDC_PITCH] = 80; gdc.s.para[GDC_PITCH] = 40; - gdc_paletteinit(); + gdc.bitac = 0xff; + + // vram bank + gdcs.disp = 0; + gdcs.access = 0; + gdc.analog &= ~(1 << GDCANALOG_16); + gdcs.palchange = GDCSCRN_REDRAW; - gdcs.textdisp = GDCSCRN_ENABLE | GDCSCRN_ALLDRAW2 | GDCSCRN_EXT; + gdc.mode2 &= ~(1 << 0); + gdc.mode2 &= ~(1 << 2); + gdc.mode2 &= ~(1 << 3); + gdcs.mode2 = gdc.mode2; + + vramop.operate &= ~(1 << VOPBIT_ACCESS); + vramop.operate &= ~(1 << VOPBIT_EGC); + vramop.operate &= ~(1 << VOPBIT_ANALOG); +#if defined(SUPPORT_PC9821) + gdc.analog &= ~(1 << (GDCANALOG_256)); + vramop.operate &= ~(1 << VOPBIT_VGA); +#endif + MEMM_VRAM(vramop.operate); + + // palette + CopyMemory(gdc.degpal, defdegpal, 4); + if (gdc.display & (1 << GDCDISP_ANALOG)) { + gdc_setanalogpalall(defanapal); + } +#if defined(SUPPORT_PC9821) + pal = gdc.anareg + (16 * 3); + for (i=0; i<256; i+=8) { + tmp = (UINT8)((i)?(i - 4):0); + pal[0] = tmp; + pal[1] = tmp; + pal[2] = tmp; + pal += 4; + for (j=1; j<8; j++) { + pal[0] = (UINT8)((i + 7) * ((j >> 2) & 1)); + pal[1] = (UINT8)((i + 7) * ((j >> 1) & 1)); + pal[2] = (UINT8)((i + 7) * ((j >> 0) & 1)); + pal += 4; + } + } +#endif + gdcs.textdisp = GDCSCRN_ALLDRAW2 | GDCSCRN_EXT; gdcs.grphdisp = GDCSCRN_ALLDRAW2 | GDCSCRN_EXT; + gdcs.palchange = GDCSCRN_REDRAW; + screenupdate |= 2; +} + +void gdc_reset(void) { + + ZeroMemory(&gdc, sizeof(gdc)); + ZeroMemory(&gdcs, sizeof(gdcs)); + +#if defined(SUPPORT_PC9821) + gdc.display |= (1 << GDCDISP_ANALOG); +#else if (np2cfg.color16 & 1) { - gdc.s.para[GDC_SYNC] = 0x16; - gdc.display = 2; + gdc.display |= (1 << GDCDISP_ANALOG); } - gdc.bitac = 0xff; +#endif + if (!(np2cfg.dipsw[0] & 0x04)) { // dipsw1-3 on + gdc.display |= (1 << GDCDISP_PLAZMA2); + } + gdc_biosreset(); } void gdc_bind(void) { gdc_updateclock(); +#if defined(SUPPORT_PC9821) + iocore_attachout(0x09a0, gdc_o9a0); + iocore_attachinp(0x09a0, gdc_i9a0); +#endif +#if defined(SUPPORT_CRT31KHZ) + iocore_attachout(0x09a8, gdc_o9a8); + iocore_attachinp(0x09a8, gdc_i9a8); +#endif iocore_attachsysoutex(0x0060, 0x0cf1, gdco60, 8); iocore_attachsysinpex(0x0060, 0x0cf1, gdci60, 8); iocore_attachsysoutex(0x00a0, 0x0cf1, gdcoa0, 8);