--- np2/io/gdc.c	2004/03/23 22:39:40	1.32
+++ np2/io/gdc.c	2007/11/03 00:00:20	1.40
@@ -93,7 +93,7 @@ void gdc_setanalogpal(int color, int rgb
 				event = palevent.event + palevent.events;
 				event->clock = nevent.item[NEVENT_FLAMES].clock -
 											(CPU_BASECLOCK - CPU_REMCLOCK);
-				event->color = (color * sizeof(RGB32)) + rgb;
+				event->color = (UINT16)((color * sizeof(RGB32)) + rgb);
 				event->value = (UINT8)value;
 				palevent.events++;
 			}
@@ -117,9 +117,9 @@ void gdc_setanalogpalall(const UINT16 *p
 		gdc.anareg[(c * 3) + 1] = (pal >> 4) & 15;
 		gdc.anareg[(c * 3) + 2] = (pal >> 0) & 15;
 #endif
-		gdc_setanalogpal(c, offsetof(RGB32, p.g), (pal >> 8) & 15);
-		gdc_setanalogpal(c, offsetof(RGB32, p.r), (pal >> 4) & 15);
-		gdc_setanalogpal(c, offsetof(RGB32, p.b), (pal >> 0) & 15);
+		gdc_setanalogpal(c, offsetof(RGB32, p.g), (REG8)((pal >> 8) & 15));
+		gdc_setanalogpal(c, offsetof(RGB32, p.r), (REG8)((pal >> 4) & 15));
+		gdc_setanalogpal(c, offsetof(RGB32, p.b), (REG8)((pal >> 0) & 15));
 	}
 }
 
@@ -148,15 +148,15 @@ void gdc_analogext(BOOL extend) {
 
 	if (extend) {
 		gdc.analog |= (1 << GDCANALOG_256);
-		vramop.operate |= 0x20;
+		vramop.operate |= (1 << VOPBIT_VGA);
 	}
 	else {
 		gdc.analog &= ~(1 << (GDCANALOG_256));
-		vramop.operate &= ~0x20;
+		vramop.operate &= ~(1 << VOPBIT_VGA);
 	}
 	gdcs.palchange = GDCSCRN_REDRAW;
 	gdcs.grphdisp |= GDCSCRN_EXT | GDCSCRN_ALLDRAW2;
-	i286_vram_dispatch(vramop.operate);
+	MEMM_VRAM(vramop.operate);
 }
 #endif
 
@@ -417,7 +417,7 @@ const GDCCLK	*clk;
 
 void gdc_restorekacmode(void) {
 
-	BYTE	bit;
+	UINT8	bit;
 
 	bit = (((!np2cfg.uPD72020) && (gdc.mode1 & 0x20))?0x00:0xff);
 	if (gdc.bitac != bit) {
@@ -503,17 +503,17 @@ static void IOOUTCALL gdc_o6a(UINT port,
 					gdc.analog &= ~(1 << GDCANALOG_16);
 					gdc.analog |= (dat << GDCANALOG_16);
 					gdcs.palchange = GDCSCRN_REDRAW;
-					vramop.operate &= VOP_ANALOGMASK;
-					vramop.operate |= dat << 4;
-					i286_vram_dispatch(vramop.operate);
+					vramop.operate &= ~(1 << VOPBIT_ANALOG);
+					vramop.operate |= dat << VOPBIT_ANALOG;
+					MEMM_VRAM(vramop.operate);
 				}
 				break;
 
 			case 2:
 				if ((gdc.mode2 & 0x08) && (grcg.chip == 3)) {
-					vramop.operate &= VOP_EGCMASK;
-					vramop.operate |= dat << 1;
-					i286_vram_dispatch(vramop.operate);
+					vramop.operate &= ~(1 << VOPBIT_EGC);
+					vramop.operate |= dat << VOPBIT_EGC;
+					MEMM_VRAM(vramop.operate);
 				}
 				break;
 		}
@@ -625,14 +625,14 @@ static REG8 IOINPCALL gdc_i60(UINT port)
 		UINT16 memv;
 		addr = CPU_INPADRS;
 		jadr = 0xfa74;
-		memv = i286_memoryread_w(addr);
+		memv = MEML_READ16(addr);
 		while((memv == 0x00eb) || (memv == 0x5fe6)) {
 			jadr -= 0x200;
 			addr += 2;
-			memv = i286_memoryread_w(addr);
+			memv = MEML_READ16(addr);
 		}
 		if ((memv == 0x20a8) || (memv == 0x2024)) {
-			memv = i286_memoryread_w(addr + 2);
+			memv = MEML_READ16(addr + 2);
 			if (memv == jadr) {					// je
 				if (!gdc.vsync) {
 					CPU_REMCLOCK = -1;
@@ -713,11 +713,12 @@ static void IOOUTCALL gdc_oa4(UINT port,
 
 static void IOOUTCALL gdc_oa6(UINT port, REG8 dat) {
 
-	if ((gdcs.access ^ dat) & 1) {
-		gdcs.access = dat & 1;
-		vramop.operate &= VOP_ACCESSMASK;
-		vramop.operate |= gdcs.access;
-		i286_vram_dispatch(vramop.operate);
+	dat = dat & 1;
+	if (gdcs.access != dat) {
+		gdcs.access = (UINT8)dat;
+		vramop.operate &= ~(1 << VOPBIT_ACCESS);
+		vramop.operate |= dat << VOPBIT_ACCESS;
+		MEMM_VRAM(vramop.operate);
 	}
 	(void)port;
 }
@@ -753,14 +754,14 @@ static REG8 IOINPCALL gdc_ia0(UINT port)
 		UINT16 memv;
 		addr = CPU_INPADRS;
 		jadr = 0xfa74;
-		memv = i286_memoryread_w(addr);
+		memv = MEML_READ16(addr);
 		while((memv == 0x00eb) || (memv == 0x5fe6)) {
 			jadr -= 0x200;
 			addr += 2;
-			memv = i286_memoryread_w(addr);
+			memv = MEML_READ16(addr);
 		}
 		if ((memv == 0x20a8) || (memv == 0x2024)) {
-			memv = i286_memoryread_w(addr + 2);
+			memv = MEML_READ16(addr + 2);
 			if (memv == jadr) {					// je
 				if (!gdc.vsync) {
 					CPU_REMCLOCK = -1;
@@ -1045,7 +1046,8 @@ static const IOINP gdcia0[8] = {
 void gdc_biosreset(void) {
 
 #if defined(SUPPORT_PC9821)
-	UINT	i, j;
+	UINT	i;
+	UINT	j;
 	UINT8	tmp;
 	UINT8	*pal;
 #endif
@@ -1085,14 +1087,20 @@ void gdc_biosreset(void) {
 	gdcs.access = 0;
 	gdc.analog &= ~(1 << GDCANALOG_16);
 	gdcs.palchange = GDCSCRN_REDRAW;
-	vramop.operate &= VOP_ACCESSMASK;
-	vramop.operate &= VOP_EGCMASK;
-	vramop.operate &= VOP_ANALOGMASK;
+
+	gdc.mode2 &= ~(1 << 0);
+	gdc.mode2 &= ~(1 << 2);
+	gdc.mode2 &= ~(1 << 3);
+	gdcs.mode2 = gdc.mode2;
+
+	vramop.operate &= ~(1 << VOPBIT_ACCESS);
+	vramop.operate &= ~(1 << VOPBIT_EGC);
+	vramop.operate &= ~(1 << VOPBIT_ANALOG);
 #if defined(SUPPORT_PC9821)
 	gdc.analog &= ~(1 << (GDCANALOG_256));
-	vramop.operate &= ~0x20;
+	vramop.operate &= ~(1 << VOPBIT_VGA);
 #endif
-	i286_vram_dispatch(vramop.operate);
+	MEMM_VRAM(vramop.operate);
 
 	// palette
 	CopyMemory(gdc.degpal, defdegpal, 4);
@@ -1121,7 +1129,7 @@ void gdc_biosreset(void) {
 	screenupdate |= 2;
 }
 
-void gdc_reset(void) {
+void gdc_reset(const NP2CFG *pConfig) {
 
 	ZeroMemory(&gdc, sizeof(gdc));
 	ZeroMemory(&gdcs, sizeof(gdcs));
@@ -1137,6 +1145,8 @@ void gdc_reset(void) {
 		gdc.display |= (1 << GDCDISP_PLAZMA2);
 	}
 	gdc_biosreset();
+
+	(void)pConfig;
 }
 
 void gdc_bind(void) {