--- np2/io/gdc.c	2004/02/29 07:36:56	1.26
+++ np2/io/gdc.c	2005/02/16 09:31:55	1.36
@@ -9,8 +9,9 @@
 #include	"palettes.h"
 #include	"timing.h"
 
-
+#if !defined(CPUCORE_IA32)
 #define	SEARCH_SYNC
+#endif
 #define	TURE_SYNC
 
 typedef struct {
@@ -44,8 +45,9 @@ static const UINT8 defsyncs31[8] = {0x06
 
 
 static const UINT8 defdegpal[4] = {0x04,0x15,0x26,0x37};
-
-
+static const UINT16 defanapal[16] = {
+				0x000,0x007,0x070,0x077,0x700,0x707,0x770,0x777,
+				0x444,0x00f,0x0f0,0x0ff,0xf00,0xf0f,0xff0,0xfff};
 
 
 void gdc_setdegitalpal(int color, REG8 value) {
@@ -70,6 +72,14 @@ void gdc_setdegitalpal(int color, REG8 v
 	}
 }
 
+void gdc_setdegpalpack(int color, REG8 value) {
+
+	if ((gdc.degpal[color] ^ value) & 0x77) {
+		gdcs.palchange = GDCSCRN_REDRAW;
+	}
+	gdc.degpal[color] = (UINT8)value;
+}
+
 void gdc_setanalogpal(int color, int rgb, REG8 value) {
 
 	UINT8		*ptr;
@@ -95,14 +105,25 @@ void gdc_setanalogpal(int color, int rgb
 	*ptr = value;
 }
 
-void gdc_setdegpalpack(int color, REG8 value) {
+void gdc_setanalogpalall(const UINT16 *paltbl) {
 
-	if ((gdc.degpal[color] ^ value) & 0x77) {
-		gdcs.palchange = GDCSCRN_REDRAW;
+	UINT	c;
+	UINT	pal;
+
+	for (c=0; c<16; c++) {
+		pal = *paltbl++;
+#if defined(SUPPORT_PC9821)
+		gdc.anareg[(c * 3) + 0] = (pal >> 8) & 15;
+		gdc.anareg[(c * 3) + 1] = (pal >> 4) & 15;
+		gdc.anareg[(c * 3) + 2] = (pal >> 0) & 15;
+#endif
+		gdc_setanalogpal(c, offsetof(RGB32, p.g), (REG8)((pal >> 8) & 15));
+		gdc_setanalogpal(c, offsetof(RGB32, p.r), (REG8)((pal >> 4) & 15));
+		gdc_setanalogpal(c, offsetof(RGB32, p.b), (REG8)((pal >> 0) & 15));
 	}
-	gdc.degpal[color] = (UINT8)value;
 }
 
+
 void gdc_paletteinit(void) {
 
 	int		c;
@@ -127,11 +148,11 @@ void gdc_analogext(BOOL extend) {
 
 	if (extend) {
 		gdc.analog |= (1 << GDCANALOG_256);
-		vramop.operate |= 0x20;
+		vramop.operate |= (1 << VOPBIT_VGA);
 	}
 	else {
 		gdc.analog &= ~(1 << (GDCANALOG_256));
-		vramop.operate &= ~0x20;
+		vramop.operate &= ~(1 << VOPBIT_VGA);
 	}
 	gdcs.palchange = GDCSCRN_REDRAW;
 	gdcs.grphdisp |= GDCSCRN_EXT | GDCSCRN_ALLDRAW2;
@@ -383,6 +404,8 @@ const GDCCLK	*clk;
 		y = clk->maxy;
 	}
 	hclock = clk->clock / x;
+	gdc.hclock = hclock;
+	gdc.vclock = hclock * 10 / y;
 	cnt = (pccore.baseclock * y) / hclock;
 	cnt *= pccore.multiple;
 	gdc.rasterclock = cnt / y;
@@ -394,7 +417,7 @@ const GDCCLK	*clk;
 
 void gdc_restorekacmode(void) {
 
-	BYTE	bit;
+	UINT8	bit;
 
 	bit = (((!np2cfg.uPD72020) && (gdc.mode1 & 0x20))?0x00:0xff);
 	if (gdc.bitac != bit) {
@@ -467,6 +490,8 @@ static void IOOUTCALL gdc_o6a(UINT port,
 
 	REG8	bit;
 
+	TRACEOUT(("port:%.4x %.2x", port, dat));
+
 	if (!(dat & 0xf8)) {
 		bit = (dat >> 1) & 3;
 		dat &= 1;
@@ -480,16 +505,16 @@ static void IOOUTCALL gdc_o6a(UINT port,
 					gdc.analog &= ~(1 << GDCANALOG_16);
 					gdc.analog |= (dat << GDCANALOG_16);
 					gdcs.palchange = GDCSCRN_REDRAW;
-					vramop.operate &= VOP_ANALOGMASK;
-					vramop.operate |= dat << 4;
+					vramop.operate &= ~(1 << VOPBIT_ANALOG);
+					vramop.operate |= dat << VOPBIT_ANALOG;
 					i286_vram_dispatch(vramop.operate);
 				}
 				break;
 
 			case 2:
 				if ((gdc.mode2 & 0x08) && (grcg.chip == 3)) {
-					vramop.operate &= VOP_EGCMASK;
-					vramop.operate |= dat << 1;
+					vramop.operate &= ~(1 << VOPBIT_EGC);
+					vramop.operate |= dat << VOPBIT_EGC;
 					i286_vram_dispatch(vramop.operate);
 				}
 				break;
@@ -595,18 +620,21 @@ static REG8 IOINPCALL gdc_i60(UINT port)
 	else {
 		gdc_work(GDCWORK_MASTER);
 	}
-#ifdef SEARCH_SYNC
+#ifdef SEARCH_SYNC		// ToDo: フェッチキューを参照するように…
 	if ((CPU_INPADRS) && (CPU_REMCLOCK >= 5)) {
-		UINT16 jadr = 0xfa74;
+		UINT32 addr;
+		UINT16 jadr;
 		UINT16 memv;
-		memv = i286_memoryread_w(CPU_INPADRS);
+		addr = CPU_INPADRS;
+		jadr = 0xfa74;
+		memv = i286_memoryread_w(addr);
 		while((memv == 0x00eb) || (memv == 0x5fe6)) {
 			jadr -= 0x200;
-			CPU_INPADRS += 2;
-			memv = i286_memoryread_w(CPU_INPADRS);
+			addr += 2;
+			memv = i286_memoryread_w(addr);
 		}
 		if ((memv == 0x20a8) || (memv == 0x2024)) {
-			memv = i286_memoryread_w(CPU_INPADRS + 2);
+			memv = i286_memoryread_w(addr + 2);
 			if (memv == jadr) {					// je
 				if (!gdc.vsync) {
 					CPU_REMCLOCK = -1;
@@ -687,10 +715,11 @@ static void IOOUTCALL gdc_oa4(UINT port,
 
 static void IOOUTCALL gdc_oa6(UINT port, REG8 dat) {
 
-	if ((gdcs.access ^ dat) & 1) {
-		gdcs.access = dat & 1;
-		vramop.operate &= VOP_ACCESSMASK;
-		vramop.operate |= gdcs.access;
+	dat = dat & 1;
+	if (gdcs.access != dat) {
+		gdcs.access = (UINT8)dat;
+		vramop.operate &= ~(1 << VOPBIT_ACCESS);
+		vramop.operate |= dat << VOPBIT_ACCESS;
 		i286_vram_dispatch(vramop.operate);
 	}
 	(void)port;
@@ -722,16 +751,19 @@ static REG8 IOINPCALL gdc_ia0(UINT port)
 	}
 #ifdef SEARCH_SYNC
 	if ((CPU_INPADRS) && (CPU_REMCLOCK >= 5)) {
-		UINT16 jadr = 0xfa74;
+		UINT32 addr;
+		UINT16 jadr;
 		UINT16 memv;
-		memv = i286_memoryread_w(CPU_INPADRS);
+		addr = CPU_INPADRS;
+		jadr = 0xfa74;
+		memv = i286_memoryread_w(addr);
 		while((memv == 0x00eb) || (memv == 0x5fe6)) {
 			jadr -= 0x200;
-			CPU_INPADRS += 2;
-			memv = i286_memoryread_w(CPU_INPADRS);
+			addr += 2;
+			memv = i286_memoryread_w(addr);
 		}
 		if ((memv == 0x20a8) || (memv == 0x2024)) {
-			memv = i286_memoryread_w(CPU_INPADRS + 2);
+			memv = i286_memoryread_w(addr + 2);
 			if (memv == jadr) {					// je
 				if (!gdc.vsync) {
 					CPU_REMCLOCK = -1;
@@ -801,7 +833,7 @@ static void IOOUTCALL gdc_oaa(UINT port,
 #endif
 	if (gdc.analog & (1 << GDCANALOG_16)) {
 #if defined(SUPPORT_PC9821)
-		gdc.anareg[(gdc.palnum * 3) + 2] = dat;
+		gdc.anareg[(gdc.palnum * 3) + 0] = dat;
 #endif
 		gdc_setanalogpal(gdc.palnum & 15, offsetof(RGB32, p.g), dat);
 	}
@@ -822,7 +854,7 @@ static void IOOUTCALL gdc_oac(UINT port,
 #endif
 	if (gdc.analog & (1 << GDCANALOG_16)) {
 #if defined(SUPPORT_PC9821)
-		gdc.anareg[(gdc.palnum * 3) + 2] = dat;
+		gdc.anareg[(gdc.palnum * 3) + 1] = dat;
 #endif
 		gdc_setanalogpal(gdc.palnum & 15, offsetof(RGB32, p.r), dat);
 	}
@@ -842,6 +874,9 @@ static void IOOUTCALL gdc_oae(UINT port,
 	else
 #endif
 	if (gdc.analog & (1 << GDCANALOG_16)) {
+#if defined(SUPPORT_PC9821)
+		gdc.anareg[(gdc.palnum * 3) + 2] = dat;
+#endif
 		gdc_setanalogpal(gdc.palnum & 15, offsetof(RGB32, p.b), dat);
 	}
 	else {
@@ -866,7 +901,7 @@ static REG8 IOINPCALL gdc_iaa(UINT port)
 		return(gdc.anareg[(16 * 3) + (gdc.palnum * 4) + 0]);
 	}
 	if (gdc.analog & (1 << GDCANALOG_16)) {
-		return(gdc.anareg[(gdc.palnum * 3) + 2]);
+		return(gdc.anareg[(gdc.palnum * 3) + 0]);
 	}
 	(void)port;
 	return(gdc.degpal[1]);
@@ -878,7 +913,7 @@ static REG8 IOINPCALL gdc_iac(UINT port)
 		return(gdc.anareg[(16 * 3) + (gdc.palnum * 4) + 1]);
 	}
 	if (gdc.analog & (1 << GDCANALOG_16)) {
-		return(gdc.anareg[(gdc.palnum * 3) + 2]);
+		return(gdc.anareg[(gdc.palnum * 3) + 1]);
 	}
 	(void)port;
 	return(gdc.degpal[2]);
@@ -903,14 +938,68 @@ static REG8 IOINPCALL gdc_iae(UINT port)
 #if defined(SUPPORT_PC9821)
 static void IOOUTCALL gdc_o9a0(UINT port, REG8 dat) {
 
+	TRACEOUT(("port:%.4x,%.2x", port, dat));
+	gdc.ff2 = dat;
 	(void)port;
-	(void)dat;
 }
 
 static REG8 IOINPCALL gdc_i9a0(UINT port) {
 
+	REG8	ret;
+
+	ret = 0;
+	switch(gdc.ff2) {
+		case 0x00:
+			ret = 0xff;
+			break;
+
+		case 0x01:
+			ret = (gdc.mode1 >> 1) & 1;
+			break;
+
+		case 0x02:
+			ret = (gdc.mode1 >> 4) & 1;
+			break;
+
+		case 0x03:
+			ret = (gdc.mode1 >> 7) & 1;
+			break;
+
+		case 0x04:
+			ret = (gdc.mode2 >> 0) & 1;
+			break;
+
+		case 0x05:
+			ret = (gdc.display >> GDCDISP_PLAZMA) & 1;
+			break;
+
+		case 0x07:
+			ret = (gdc.mode2 >> 2) & 1;
+			break;
+
+		case 0x08:
+			ret = (gdc.mode2 >> 3) & 1;
+			break;
+
+		case 0x09:
+			ret = (gdc.clock >> 0) & 1;
+			break;
+
+		case 0x0a:
+			ret = (gdc.analog >> GDCANALOG_256) & 1;
+			break;
+
+		case 0x0b:
+			ret = 1;
+			break;
+
+		case 0x0d:
+			ret = (gdc.analog >> GDCANALOG_256E) & 1;
+			break;
+	}
+	ret |= (gdc.clock & 2);
 	(void)port;
-	return(0);
+	return(ret);
 }
 #endif
 
@@ -957,10 +1046,14 @@ static const IOINP gdcia0[8] = {
 #endif
 
 
-void gdc_reset(void) {
+void gdc_biosreset(void) {
 
-	ZeroMemory(&gdc, sizeof(gdc));
-	ZeroMemory(&gdcs, sizeof(gdcs));
+#if defined(SUPPORT_PC9821)
+	UINT	i;
+	UINT	j;
+	UINT8	tmp;
+	UINT8	*pal;
+#endif
 
 	if (!(np2cfg.dipsw[0] & 0x01)) {
 		gdc.mode1 = 0x98;
@@ -980,6 +1073,9 @@ void gdc_reset(void) {
 		CopyMemory(gdc.m.para + GDC_SYNC, defsyncm15, 8);
 		CopyMemory(gdc.s.para + GDC_SYNC, defsyncs15, 8);
 	}
+	if (np2cfg.dipsw[0] & 0x80) {
+		gdc.s.para[GDC_SYNC] = 0x16;
+	}
 	gdc_vectreset(&gdc.m);
 	gdc_vectreset(&gdc.s);
 
@@ -987,25 +1083,74 @@ void gdc_reset(void) {
 	gdc.m.para[GDC_PITCH] = 80;
 	gdc.s.para[GDC_PITCH] = 40;
 
-	gdc_paletteinit();
+	gdc.bitac = 0xff;
 
-	if (np2cfg.color16 & 1) {
-		gdc.s.para[GDC_SYNC] = 0x16;
-		gdc.display = (1 << GDCDISP_ANALOG);
+	// vram bank
+	gdcs.disp = 0;
+	gdcs.access = 0;
+	gdc.analog &= ~(1 << GDCANALOG_16);
+	gdcs.palchange = GDCSCRN_REDRAW;
+	vramop.operate &= ~(1 << VOPBIT_ACCESS);
+	vramop.operate &= ~(1 << VOPBIT_EGC);
+	vramop.operate &= ~(1 << VOPBIT_ANALOG);
+#if defined(SUPPORT_PC9821)
+	gdc.analog &= ~(1 << (GDCANALOG_256));
+	vramop.operate &= ~(1 << VOPBIT_VGA);
+#endif
+	i286_vram_dispatch(vramop.operate);
+
+	// palette
+	CopyMemory(gdc.degpal, defdegpal, 4);
+	if (gdc.display & (1 << GDCDISP_ANALOG)) {
+		gdc_setanalogpalall(defanapal);
 	}
-	gdc.bitac = 0xff;
+#if defined(SUPPORT_PC9821)
+	pal = gdc.anareg + (16 * 3);
+	for (i=0; i<256; i+=8) {
+		tmp = (UINT8)((i)?(i - 4):0);
+		pal[0] = tmp;
+		pal[1] = tmp;
+		pal[2] = tmp;
+		pal += 4;
+		for (j=1; j<8; j++) {
+			pal[0] = (UINT8)((i + 7) * ((j >> 2) & 1));
+			pal[1] = (UINT8)((i + 7) * ((j >> 1) & 1));
+			pal[2] = (UINT8)((i + 7) * ((j >> 0) & 1));
+			pal += 4;
+		}
+	}
+#endif
+	gdcs.textdisp = GDCSCRN_ALLDRAW2 | GDCSCRN_EXT;
+	gdcs.grphdisp = GDCSCRN_ALLDRAW2 | GDCSCRN_EXT;
+	gdcs.palchange = GDCSCRN_REDRAW;
+	screenupdate |= 2;
+}
 
+void gdc_reset(void) {
+
+	ZeroMemory(&gdc, sizeof(gdc));
+	ZeroMemory(&gdcs, sizeof(gdcs));
+
+#if defined(SUPPORT_PC9821)
+	gdc.display |= (1 << GDCDISP_ANALOG);
+#else
+	if (np2cfg.color16 & 1) {
+		gdc.display |= (1 << GDCDISP_ANALOG);
+	}
+#endif
 	if (!(np2cfg.dipsw[0] & 0x04)) {			// dipsw1-3 on
 		gdc.display |= (1 << GDCDISP_PLAZMA2);
 	}
-
-	gdcs.textdisp = GDCSCRN_ENABLE | GDCSCRN_ALLDRAW2 | GDCSCRN_EXT;
-	gdcs.grphdisp = GDCSCRN_ALLDRAW2 | GDCSCRN_EXT;
+	gdc_biosreset();
 }
 
 void gdc_bind(void) {
 
 	gdc_updateclock();
+#if defined(SUPPORT_PC9821)
+	iocore_attachout(0x09a0, gdc_o9a0);
+	iocore_attachinp(0x09a0, gdc_i9a0);
+#endif
 #if defined(SUPPORT_CRT31KHZ)
 	iocore_attachout(0x09a8, gdc_o9a8);
 	iocore_attachinp(0x09a8, gdc_i9a8);