--- np2/io/gdc.c	2004/03/21 11:47:20	1.30
+++ np2/io/gdc.c	2005/02/27 15:07:36	1.37
@@ -117,9 +117,9 @@ void gdc_setanalogpalall(const UINT16 *p
 		gdc.anareg[(c * 3) + 1] = (pal >> 4) & 15;
 		gdc.anareg[(c * 3) + 2] = (pal >> 0) & 15;
 #endif
-		gdc_setanalogpal(c, offsetof(RGB32, p.g), (pal >> 8) & 15);
-		gdc_setanalogpal(c, offsetof(RGB32, p.r), (pal >> 4) & 15);
-		gdc_setanalogpal(c, offsetof(RGB32, p.b), (pal >> 0) & 15);
+		gdc_setanalogpal(c, offsetof(RGB32, p.g), (REG8)((pal >> 8) & 15));
+		gdc_setanalogpal(c, offsetof(RGB32, p.r), (REG8)((pal >> 4) & 15));
+		gdc_setanalogpal(c, offsetof(RGB32, p.b), (REG8)((pal >> 0) & 15));
 	}
 }
 
@@ -148,11 +148,11 @@ void gdc_analogext(BOOL extend) {
 
 	if (extend) {
 		gdc.analog |= (1 << GDCANALOG_256);
-		vramop.operate |= 0x20;
+		vramop.operate |= (1 << VOPBIT_VGA);
 	}
 	else {
 		gdc.analog &= ~(1 << (GDCANALOG_256));
-		vramop.operate &= ~0x20;
+		vramop.operate &= ~(1 << VOPBIT_VGA);
 	}
 	gdcs.palchange = GDCSCRN_REDRAW;
 	gdcs.grphdisp |= GDCSCRN_EXT | GDCSCRN_ALLDRAW2;
@@ -404,6 +404,8 @@ const GDCCLK	*clk;
 		y = clk->maxy;
 	}
 	hclock = clk->clock / x;
+	gdc.hclock = hclock;
+	gdc.vclock = hclock * 10 / y;
 	cnt = (pccore.baseclock * y) / hclock;
 	cnt *= pccore.multiple;
 	gdc.rasterclock = cnt / y;
@@ -415,7 +417,7 @@ const GDCCLK	*clk;
 
 void gdc_restorekacmode(void) {
 
-	BYTE	bit;
+	UINT8	bit;
 
 	bit = (((!np2cfg.uPD72020) && (gdc.mode1 & 0x20))?0x00:0xff);
 	if (gdc.bitac != bit) {
@@ -501,16 +503,16 @@ static void IOOUTCALL gdc_o6a(UINT port,
 					gdc.analog &= ~(1 << GDCANALOG_16);
 					gdc.analog |= (dat << GDCANALOG_16);
 					gdcs.palchange = GDCSCRN_REDRAW;
-					vramop.operate &= VOP_ANALOGMASK;
-					vramop.operate |= dat << 4;
+					vramop.operate &= ~(1 << VOPBIT_ANALOG);
+					vramop.operate |= dat << VOPBIT_ANALOG;
 					i286_vram_dispatch(vramop.operate);
 				}
 				break;
 
 			case 2:
 				if ((gdc.mode2 & 0x08) && (grcg.chip == 3)) {
-					vramop.operate &= VOP_EGCMASK;
-					vramop.operate |= dat << 1;
+					vramop.operate &= ~(1 << VOPBIT_EGC);
+					vramop.operate |= dat << VOPBIT_EGC;
 					i286_vram_dispatch(vramop.operate);
 				}
 				break;
@@ -711,10 +713,11 @@ static void IOOUTCALL gdc_oa4(UINT port,
 
 static void IOOUTCALL gdc_oa6(UINT port, REG8 dat) {
 
-	if ((gdcs.access ^ dat) & 1) {
-		gdcs.access = dat & 1;
-		vramop.operate &= VOP_ACCESSMASK;
-		vramop.operate |= gdcs.access;
+	dat = dat & 1;
+	if (gdcs.access != dat) {
+		gdcs.access = (UINT8)dat;
+		vramop.operate &= ~(1 << VOPBIT_ACCESS);
+		vramop.operate |= dat << VOPBIT_ACCESS;
 		i286_vram_dispatch(vramop.operate);
 	}
 	(void)port;
@@ -933,14 +936,67 @@ static REG8 IOINPCALL gdc_iae(UINT port)
 #if defined(SUPPORT_PC9821)
 static void IOOUTCALL gdc_o9a0(UINT port, REG8 dat) {
 
+	gdc.ff2 = dat;
 	(void)port;
-	(void)dat;
 }
 
 static REG8 IOINPCALL gdc_i9a0(UINT port) {
 
+	REG8	ret;
+
+	ret = 0;
+	switch(gdc.ff2) {
+		case 0x00:
+			ret = 0xff;
+			break;
+
+		case 0x01:
+			ret = (gdc.mode1 >> 1) & 1;
+			break;
+
+		case 0x02:
+			ret = (gdc.mode1 >> 4) & 1;
+			break;
+
+		case 0x03:
+			ret = (gdc.mode1 >> 7) & 1;
+			break;
+
+		case 0x04:
+			ret = (gdc.mode2 >> 0) & 1;
+			break;
+
+		case 0x05:
+			ret = (gdc.display >> GDCDISP_PLAZMA) & 1;
+			break;
+
+		case 0x07:
+			ret = (gdc.mode2 >> 2) & 1;
+			break;
+
+		case 0x08:
+			ret = (gdc.mode2 >> 3) & 1;
+			break;
+
+		case 0x09:
+			ret = (gdc.clock >> 0) & 1;
+			break;
+
+		case 0x0a:
+			ret = (gdc.analog >> GDCANALOG_256) & 1;
+			break;
+
+		case 0x0b:
+			ret = 1;
+			break;
+
+		case 0x0d:
+			ret = (gdc.analog >> GDCANALOG_256E) & 1;
+			break;
+	}
+	ret |= (gdc.clock & 2);
 	(void)port;
-	return(0);
+	return(ret);
 }
 #endif
 
@@ -990,7 +1046,8 @@ static const IOINP gdcia0[8] = {
 void gdc_biosreset(void) {
 
 #if defined(SUPPORT_PC9821)
-	UINT	i, j;
+	UINT	i;
+	UINT	j;
 	UINT8	tmp;
 	UINT8	*pal;
 #endif
@@ -1030,12 +1087,18 @@ void gdc_biosreset(void) {
 	gdcs.access = 0;
 	gdc.analog &= ~(1 << GDCANALOG_16);
 	gdcs.palchange = GDCSCRN_REDRAW;
-	vramop.operate &= VOP_ACCESSMASK;
-	vramop.operate &= VOP_EGCMASK;
-	vramop.operate &= VOP_ANALOGMASK;
+
+	gdc.mode2 &= ~(1 << 0);
+	gdc.mode2 &= ~(1 << 2);
+	gdc.mode2 &= ~(1 << 3);
+	gdcs.mode2 = gdc.mode2;
+
+	vramop.operate &= ~(1 << VOPBIT_ACCESS);
+	vramop.operate &= ~(1 << VOPBIT_EGC);
+	vramop.operate &= ~(1 << VOPBIT_ANALOG);
 #if defined(SUPPORT_PC9821)
 	gdc.analog &= ~(1 << (GDCANALOG_256));
-	vramop.operate &= ~0x20;
+	vramop.operate &= ~(1 << VOPBIT_VGA);
 #endif
 	i286_vram_dispatch(vramop.operate);
 
@@ -1087,7 +1150,7 @@ void gdc_reset(void) {
 void gdc_bind(void) {
 
 	gdc_updateclock();
-#if defined(SUPPORT_PC9821)				// とりあえずフックだけ
+#if defined(SUPPORT_PC9821)
 	iocore_attachout(0x09a0, gdc_o9a0);
 	iocore_attachinp(0x09a0, gdc_i9a0);
 #endif