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| version 1.7, 2004/02/21 00:25:33 | version 1.13, 2004/03/22 05:38:47 |
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| Line 26 typedef struct { | Line 26 typedef struct { |
| UINT8 vsyncint; | UINT8 vsyncint; |
| UINT8 display; | UINT8 display; |
| UINT8 bitac; | UINT8 bitac; |
| UINT8 reserved[2]; | UINT8 ff2; |
| UINT8 reserved; | |
| int analog; | int analog; |
| int palnum; | int palnum; |
| UINT8 degpal[4]; | UINT8 degpal[4]; |
| RGB32 anapal[16]; | RGB32 anapal[16]; |
| UINT32 dispclock; | UINT32 dispclock; |
| UINT32 vsyncclock; | UINT32 vsyncclock; |
| UINT32 rasterclock; | UINT32 rasterclock; |
| UINT32 hsyncclock; | UINT32 hsyncclock; |
| #if defined(SUPPORT_PC9821) | |
| UINT8 anareg[16*3 + 256*4]; | |
| #endif | |
| } _GDC, *GDC; | } _GDC, *GDC; |
| typedef struct { | typedef struct { |
| Line 62 enum { | Line 66 enum { |
| GDCSCRN_MAKE = (GDCSCRN_ALLDRAW | GDCSCRN_REDRAW), | GDCSCRN_MAKE = (GDCSCRN_ALLDRAW | GDCSCRN_REDRAW), |
| GDCWORK_MASTER = 0, | GDCWORK_MASTER = 0, |
| GDCWORK_SLAVE = 1 | GDCWORK_SLAVE = 1, |
| GDCANALOG_16 = 0, | |
| GDCANALOG_256 = 1, | |
| GDCANALOG_256E = 2, | |
| GDCDISP_PLAZMA = 0, | |
| GDCDISP_ANALOG = 1, | |
| GDCDISP_PLAZMA2 = 2, | |
| GDCDISP_15 = 6, | |
| GDCDISP_31 = 7 | |
| }; | }; |
| Line 79 void gdc_forceready(int id); | Line 93 void gdc_forceready(int id); |
| void gdc_paletteinit(void); | void gdc_paletteinit(void); |
| void gdc_setdegitalpal(int color, REG8 value); | void gdc_setdegitalpal(int color, REG8 value); |
| void gdc_setanalogpal(int color, int rgb, REG8 value); | |
| void gdc_setdegpalpack(int color, REG8 value); | void gdc_setdegpalpack(int color, REG8 value); |
| void gdc_setanalogpal(int color, int rgb, REG8 value); | |
| void gdc_setanalogpalall(const UINT16 *paltbl); | |
| #if defined(SUPPORT_PC9821) | |
| void gdc_analogext(BOOL extend); | |
| #endif | |
| void gdc_biosreset(void); | |
| void gdc_updateclock(void); | void gdc_updateclock(void); |
| void gdc_restorekacmode(void); | void gdc_restorekacmode(void); |