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| version 1.13, 2004/02/18 21:58:41 | version 1.15, 2004/02/20 15:20:30 |
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| Line 20 typedef struct { | Line 20 typedef struct { |
| SINT16 y2; | SINT16 y2; |
| } VECTDIR; | } VECTDIR; |
| const UINT32 gdcplaneseg[4] = {VRAM_E, VRAM_B, VRAM_R, VRAM_G}; | |
| static UINT16 gdc_rt[RT_TABLEMAX+1]; | static UINT16 gdc_rt[RT_TABLEMAX+1]; |
| static const VECTDIR vectdir[16] = { | static const VECTDIR vectdir[16] = { |
| Line 107 static void calc_gdcslavewait(UINT dots) | Line 109 static void calc_gdcslavewait(UINT dots) |
| SINT32 clk; | SINT32 clk; |
| clk = dots; | clk = dots; |
| if (pccore.baseclock != PCBASECLOCK20) { | if (pccore.cpumode & CPUMODE_8MHZ) { |
| clk *= 27648; | clk *= 22464; |
| } | } |
| else { | else { |
| clk *= 22464; | clk *= 27648; |
| } | } |
| clk *= pccore.multiple; | clk *= pccore.multiple; |
| clk /= 15625; | clk /= 15625; |
| Line 546 void gdcsub_write(void) { | Line 548 void gdcsub_write(void) { |
| } | } |
| gdcs.grphdisp |= (BYTE)updatebit; | gdcs.grphdisp |= (BYTE)updatebit; |
| ptr += vramplaneseg[(adrs >> 14) & 3]; | ptr += gdcplaneseg[(adrs >> 14) & 3]; |
| adrs = (adrs & 0x3fff) << 1; | adrs = (adrs & 0x3fff) << 1; |
| calc_gdcslavewait(leng); | calc_gdcslavewait(leng); |