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| version 1.14, 2003/11/12 20:02:54 | version 1.19, 2003/11/21 06:51:10 |
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| Line 11 | Line 11 |
| #include "pc9861k.h" | #include "pc9861k.h" |
| #include "mpu98ii.h" | #include "mpu98ii.h" |
| #include "bios.h" | #include "bios.h" |
| #include "biosmem.h" | |
| #include "vram.h" | #include "vram.h" |
| #include "scrndraw.h" | #include "scrndraw.h" |
| #include "dispsync.h" | #include "dispsync.h" |
| Line 34 | Line 35 |
| const char np2version[] = NP2VER_CORE; | const char np2version[] = NP2VER_CORE; |
| NP2CFG np2cfg = { | NP2CFG np2cfg = { |
| PCBASECLOCK25, 4, 0, | 0, 1, 0, 32, 0, 0, 0x40, |
| {0x3e, 0x63, 0x7a}, | 0, 0, 0, 0, |
| {0x48, 0x05, 0x04, 0x00, 0x01, 0x00, 0x00, 0x6E}, | {0x3e, 0x63, 0x7a}, 0, |
| {0x0c, 0x0c, 0x08, 0x06, 0x03, 0x0c}, | 0, 0, {1, 1, 6, 1, 8, 1}, |
| {1, 1, 6, 1, 8, 1}, | |
| 0, 4, 32, 22050, 800, 0, 1, 1, 0, | "VX", PCBASECLOCK25, 4, |
| 0, 0, | {0x48, 0x05, 0x04, 0x00, 0x01, 0x00, 0x00, 0x6e}, |
| 0, {0, 0, 0}, 0xd1, 0x7f, 0xd1, 0, 0, 1, 0x82, // ver0.30 | 1, 1, 2, 1, 0x000000, 0xffffff, |
| 1, 80, 3, 1, 1, 0, 0x000000, 0xffffff, | 22050, 800, 4, 0, |
| 0, 0, 0, 0x40, 0, | {0, 0, 0}, 0xd1, 0x7f, 0xd1, 0, 0, 1, |
| 64, 64, 64, 64, 64, | 3, {0x0c, 0x0c, 0x08, 0x06, 0x03, 0x0c}, 64, 64, 64, 64, 64, |
| 1, 0x82, | |
| 0, {0x17, 0x04, 0x1f}, {0x0c, 0x0c, 0x02, 0x10, 0x3f, 0x3f}, | 0, {0x17, 0x04, 0x1f}, {0x0c, 0x0c, 0x02, 0x10, 0x3f, 0x3f}, |
| 2, 1, 0, 0, | 1, 80, 0, |
| {"", ""}, ""}; | {"", ""}, ""}; |
| PCCORE pc = { PCBASECLOCK25, | PCCORE pc = { PCBASECLOCK25, |
| 4, | 4, |
| 4 * PCBASECLOCK25, | 4 * PCBASECLOCK25, |
| 4 * PCBASECLOCK25 * 50 / 3104, | 4 * PCBASECLOCK25 * 50 / 3104, |
| 4 * PCBASECLOCK25 * 5 / 3104, | 4 * PCBASECLOCK25 * 5 / 3104, |
| 4 * PCBASECLOCK25 / 120, | 4 * PCBASECLOCK25 / 120, |
| 4 * PCBASECLOCK25 / 1920, | 4 * PCBASECLOCK25 / 1920, |
| 4 * PCBASECLOCK25 / 3125, | 4 * PCBASECLOCK25 / 3125, |
| (4 * PCBASECLOCK25 / 56400), | 4 * PCBASECLOCK25 / 56400, |
| 100, 20, | 100, 20, 0, PCMODEL_VX}; |
| 0}; | |
| // // on=0, off=1 | // on=0, off=1 |
| // BYTE dip_default[3] = {0x3e, 0x63, 0x7a}; | // BYTE dip_default[3] = {0x3e, 0x63, 0x7a}; |
| static const BYTE msw_default[8] = | static const BYTE msw_default[8] = |
| {0x48, 0x05, 0x04, 0x00, 0x01, 0x00, 0x00, 0x6E}; | {0x48, 0x05, 0x04, 0x00, 0x01, 0x00, 0x00, 0x6e}; |
| BYTE screenupdate = 3; | BYTE screenupdate = 3; |
| int screendispflag = 1; | int screendispflag = 1; |
| Line 115 static void setvsyncclock(void) { | Line 116 static void setvsyncclock(void) { |
| pc.vsyncclock = cnt - pc.dispclock; | pc.vsyncclock = cnt - pc.dispclock; |
| } | } |
| static void setpcclock(UINT base, UINT multiple) { // ver0.28 | static void setpcclock(UINT base, UINT multiple) { |
| pc.model = PCMODEL_VX; | |
| if (base >= ((PCBASECLOCK25 + PCBASECLOCK20) / 2)) { | if (base >= ((PCBASECLOCK25 + PCBASECLOCK20) / 2)) { |
| pc.baseclock = PCBASECLOCK25; // 2.5MHz | pc.baseclock = PCBASECLOCK25; // 2.5MHz |
| Line 211 void pccore_term(void) { | Line 214 void pccore_term(void) { |
| fdd_eject(2); | fdd_eject(2); |
| fdd_eject(3); | fdd_eject(3); |
| extmemmng_clear(); // ver0.28 | extmemmng_clear(); |
| iocore_destroy(); | iocore_destroy(); |
| Line 230 void pccore_cfgupdate(void) { | Line 233 void pccore_cfgupdate(void) { |
| renewal = FALSE; | renewal = FALSE; |
| for (i=0; i<8; i++) { | for (i=0; i<8; i++) { |
| if (np2cfg.memsw[i] != mem[0xa3fe2 + i*4]) { | if (np2cfg.memsw[i] != mem[MEMB_MSW + i*4]) { |
| np2cfg.memsw[i] = mem[0xa3fe2 + i*4]; | np2cfg.memsw[i] = mem[MEMB_MSW + i*4]; |
| renewal = TRUE; | renewal = TRUE; |
| } | } |
| } | } |
| Line 527 void pccore_exec(BOOL draw) { | Line 530 void pccore_exec(BOOL draw) { |
| } | } |
| #else | #else |
| while(I286_REMCLOCK > 0) { | while(I286_REMCLOCK > 0) { |
| static BYTE sw = 0; | #if 0 |
| if (*(UINT32 *)(mem + 0x48) == 0x18000114) { | TRACEOUT(("%.4x:%.4x", I286_CS, I286_IP)); |
| if (sw == 0) { | #elif 1 |
| sw = 1; | if ((I286_CS == 0x1c29) && (I286_IP == 0x01E9)) { |
| TRACEOUT(("[%.8x] %.4x:%.4x %s", | if (I286_BX) { |
| *(UINT32 *)(mem + 0x48), | TRACEOUT(("set %.4x", I286_BX)); |
| I286_CS, I286_IP, debugsub_regs())); | } |
| } | } |
| } | if ((I286_CS == 0x4159) && (I286_IP == 0x02d6)) { |
| else { | if (I286_AX) { |
| if (sw != 0) { | TRACEOUT(("get %d", (short)I286_AX)); |
| sw = 0; | } |
| TRACEOUT(("[%.8x] %.4x:%.4x %s", | } |
| *(UINT32 *)(mem + 0x48), | #else |
| I286_CS, I286_IP, debugsub_regs())); | if (I286_CS == 0x4159) { |
| } | if ((I286_IP >= 0x02d1) && (I286_IP < 0x02e3)) { |
| } | TRACEOUT(("%s", debugsub_regs())); |
| } | |
| } | |
| #endif | |
| i286_step(); | i286_step(); |
| } | } |
| #endif | #endif |