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| version 1.4, 2003/12/21 23:27:09 | version 1.6, 2004/02/07 21:23:22 |
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| Line 61 G_MASTER equ (GD_SIZE * -1) | Line 61 G_MASTER equ (GD_SIZE * -1) |
| G_SLAVE equ 0 | G_SLAVE equ 0 |
| G_MODE1 equ (GD_SIZE + &00) | G_MODE1 equ (GD_SIZE + &00) |
| ; G_mode2 equ (GD_SIZE + &01) | ; G_mode2 equ (GD_SIZE + &01) |
| ; G_vsync equ (GD_SIZE + &02) | G_CLOCK equ (GD_SIZE + &02) |
| ; G_vsyncint equ (GD_SIZE + &03) | ; G_crt15khz equ (GD_SIZE + &03) |
| ; G_analog equ (GD_SIZE + &04) | ; G_m_drawing equ (GD_SIZE + &04) |
| ; G_palnum equ (GD_SIZE + &08) | ; G_s_drawing equ (GD_SIZE + &05) |
| ; G_degpal equ (GD_SIZE + &0c) | ; G_vsync equ (GD_SIZE + &06) |
| ; G_anapal equ (GD_SIZE + &10) | ; G_vsyncint equ (GD_SIZE + &07) |
| G_CLOCK equ (GD_SIZE + &50) | ; G_display equ (GD_SIZE + &08) |
| ; G_display equ (GD_SIZE + &51) | ; G_bitac equ (GD_SIZE + &09) |
| ; G_bitac equ (GD_SIZE + &52) | ; G_analog equ (GD_SIZE + &0c) |
| ; G_m_drawing equ (GD_SIZE + &53) | ; G_palnum equ (GD_SIZE + &10) |
| ; G_s_drawing equ (GD_SIZE + &54) | ; G_degpal equ (GD_SIZE + &14) |
| ; G_anapal equ (GD_SIZE + &18) | |
| INCLUDE ..\..\i286a\i286a.inc | INCLUDE ..\..\i286a\i286a.inc |
| IMPORT np2cfg | IMPORT np2cfg |
| IMPORT i286core | IMPORT i286acore |
| IMPORT np2_vram | IMPORT np2_vram |
| IMPORT dsync | IMPORT dsync |
| IMPORT vramupdate | IMPORT vramupdate |
| Line 327 mg_updclear ldr r12, [r7, r4] | Line 328 mg_updclear ldr r12, [r7, r4] |
| gp_dsync dcd dsync | gp_dsync dcd dsync |
| gp_vramupdate dcd vramupdate | gp_vramupdate dcd vramupdate |
| gp_vmem dcd i286core + CPU_SIZE + VRAM_B | gp_vmem dcd i286acore + CPU_SIZE + VRAM_B |
| gp_gdc dcd gdc - G_MASTER | gp_gdc dcd gdc - G_MASTER |
| gp_gtable0 dcd grph_table0 | gp_gtable0 dcd grph_table0 |
| gp_np2vram dcd np2_vram | gp_np2vram dcd np2_vram |