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| version 1.10, 2004/08/15 11:14:42 | version 1.14, 2005/02/04 06:42:11 |
|---|---|
| Line 7 enum { | Line 7 enum { |
| CRTC_PALB = 0, | CRTC_PALB = 0, |
| CRTC_PALR = 1, | CRTC_PALR = 1, |
| CRTC_PALG = 2, | CRTC_PALG = 2, |
| CRTC_PLY = 3 | CRTC_PLY = 3, |
| CRTC_BLACK = 4, | |
| CRTC_RGBPMAX = 5 | |
| }; | }; |
| #define PAL_NORMAL 0x00 | #define PAL_NORMAL 0x00 |
| Line 22 enum { | Line 24 enum { |
| #define PAL_4096 0x10 | #define PAL_4096 0x10 |
| #define SCRN_BANK0 0x00 | #if !defined(SUPPORT_TURBOZ) |
| #define SCRN_BANK1 0x80 | enum { |
| #define SCRN_DRAW4096 0x40 | DISPMODE_24KHZ = 0x01, |
| DISPMODE_200L = 0x02, | |
| #define SCRN64_MASK 0x0f | DISPMODE_TEXTYx2 = 0x04, |
| #define SCRN64_INVALID 0 | DISPMODE_UNDERLINE = 0x08, |
| #define SCRN64_320x200 1 | |
| #define SCRN64_L320x200x2 2 | DISPMODE_MASKMODE = 0x0f, |
| #define SCRN64_L640x200 3 | DISPMODE_WIDTH80 = 0x40, |
| #define SCRN64_H320x400 4 | DISPMODE_BANK1 = 0x80 |
| #define SCRN64_320x200x4096 5 | }; |
| #else | |
| #define SCRN64_320x100 6 | enum { |
| #define SCRN64_320x100x2 7 | DISPMODE_24KHZ = 0x01, |
| #define SCRN64_L640x100 8 | DISPMODE_200L = 0x02, |
| #define SCRN64_H320x200 9 | DISPMODE_TEXTYx2 = 0x04, |
| #define SCRN64_320x100x4096 10 | DISPMODE_UNDERLINE = 0x08, |
| DISPMODE_SCRN64 = 0x10, | |
| DISPMODE64_320x200 = 0x10, | |
| DISPMODE64_L320x200x2 = 0x11, | |
| DISPMODE64_L640x200 = 0x12, | |
| DISPMODE64_H320x400 = 0x13, | |
| DISPMODE64_320x200x4096 = 0x14, | |
| DISPMODE64_320x100 = 0x15, | |
| DISPMODE64_320x100x2 = 0x16, | |
| DISPMODE64_L640x100 = 0x17, | |
| DISPMODE64_H320x200 = 0x18, | |
| DISPMODE64_320x100x4096 = 0x19, | |
| DISPMODE_MASKMODE = 0x1f, | |
| DISPMODE_4096 = 0x20, | |
| DISPMODE_WIDTH80 = 0x40, | |
| DISPMODE_BANK1 = 0x80 | |
| }; | |
| #endif | |
| enum { | |
| SCRN_BANK0 = 0x00, | |
| SCRN_BANK1 = 0x80, | |
| SCRN_WIDTH80 = 0x40, | |
| SCRN_DRAW4096 = 0x20, | |
| SCRN64_320x200 = 0x10, | |
| SCRN64_L320x200x2 = 0x11, | |
| SCRN64_L640x200 = 0x12, | |
| SCRN64_H320x400 = 0x13, | |
| SCRN64_320x200x4096 = 0x14, | |
| SCRN64_320x100 = 0x15, | |
| SCRN64_320x100x2 = 0x16, | |
| SCRN64_L640x100 = 0x17, | |
| SCRN64_H320x200 = 0x18, | |
| SCRN64_320x100x4096 = 0x19, | |
| SCRN64_MASK = 0x1f, | |
| SCRN64_ENABLE = 0x10 | |
| }; | |
| // SCRN_24KHZ 0x01 // 0:15KHz 1:24KHz | // SCRN_24KHZ 0x01 // 0:15KHz 1:24KHz |
| // SCRN_200LINE 0x02 // 0:400line 1:200line | // SCRN_200LINE 0x02 // 0:400line 1:200line |
| Line 61 enum { | Line 103 enum { |
| SCRN_CPUFONT = 0x40, | SCRN_CPUFONT = 0x40, |
| SCRN_UNDERLINE = 0x80, | SCRN_UNDERLINE = 0x80, |
| SCRN_DISPCHANGE = SCRN_24KHZ|SCRN_200LINE|SCRN_TEXTYx2|SCRN_UNDERLINE | SCRN_DISPCHANGE = SCRN_24KHZ + SCRN_200LINE + SCRN_TEXTYx2 + SCRN_DISPVRAM + SCRN_UNDERLINE |
| }; | }; |
| enum { | enum { |
| Line 86 typedef struct { | Line 128 typedef struct { |
| UINT8 width40; | UINT8 width40; |
| UINT8 regnum; | UINT8 regnum; |
| UINT8 padding; | UINT8 padding; |
| UINT8 rgbp[4]; | UINT8 rgbp[6]; |
| UINT8 reg[CRTCREG_MAX]; | UINT8 reg[CRTCREG_MAX]; |
| UINT8 BLACKPAL; | #if defined(SUPPORT_TURBOZ) |
| UINT8 EXTPALMODE; | UINT8 EXTPALMODE; |
| UINT8 EXTGRPHPAL; | UINT8 EXTGRPHPAL; |
| UINT8 ZPRY; | UINT8 ZPRY; |
| UINT8 lastpal; | UINT8 lastpal; |
| #endif | |
| } CRTCSTAT; | } CRTCSTAT; |
| typedef struct { | typedef struct { |
| SINT32 rasterclock8; | UINT8 scrnflash; |
| SINT32 rasterdisp8; | UINT8 scrnallflash; |
| UINT fonty; | UINT8 remakeattr; // doubleatrchange |
| UINT yl; | UINT8 palandply; |
| SINT32 frameclock; | |
| UINT8 *gramacc; // curvram | |
| UINT8 *gram; // curvram | #if (!defined(MEMOPTIMIZE)) || (MEMOPTIMIZE < 100) |
| UINT updatemask; // updatemsk | UINT updatemask; // updatemsk |
| UINT8 updatebit; // curupdt | UINT8 updatebit; // curupdt |
| #else | |
| UINT8 updatebit; // curupdt | |
| UINT8 _padding1; | |
| UINT16 updatemask; // updatemsk | |
| UINT8 _padding2; | |
| #endif | |
| UINT8 dispmode; | UINT8 dispmode; |
| UINT8 existblink; // blinkflag | |
| UINT8 blinktime; | |
| #if defined(SUPPORT_TURBOZ) | |
| UINT8 pal_bank; | UINT8 pal_bank; |
| UINT8 pal_disp; | UINT8 pal_disp; |
| UINT8 pal_padding[2]; | |
| #endif | |
| SINT32 rasterclock8; | |
| SINT32 rasterdisp8; | |
| SINT32 frameclock; | |
| UINT fonty; | |
| UINT yl; | |
| UINT pos; | UINT pos; |
| SINT32 dispclock; | |
| SINT32 vsyncstart; | |
| SINT32 vpulseclock; | |
| } CRTCEXT; | } CRTCEXT; |
| #if defined(SUPPORT_TURBOZ) | |
| typedef struct { | typedef struct { |
| UINT8 text[8]; | UINT8 text[8]; |
| UINT16 grph[2][64]; | UINT16 grph[2][64]; |
| UINT16 grph4096[4096]; | UINT16 grph4096[4096]; |
| } CRTCPAL; | } CRTCPAL; |
| #endif | |
| typedef struct { | typedef struct { |
| CRTCSTAT s; | |
| CRTCEXT e; | CRTCEXT e; |
| CRTCSTAT s; | |
| #if defined(SUPPORT_TURBOZ) | |
| CRTCPAL p; | CRTCPAL p; |
| #endif | |
| } CRTC; | } CRTC; |
| Line 133 typedef struct { | Line 193 typedef struct { |
| void crtc_setwidth(REG8 width40); | void crtc_setwidth(REG8 width40); |
| void crtc_update(void); | void crtc_update(void); |
| // void crtc_bankupdate(void); // vrambank_patch | |
| // void crtc_regupdate(void); | |
| void IOOUTCALL crtc_o(UINT port, REG8 value); // x1_crtc_w | void IOOUTCALL crtc_o(UINT port, REG8 value); // x1_crtc_w |
| Line 142 void IOOUTCALL scrn_o(UINT port, REG8 va | Line 200 void IOOUTCALL scrn_o(UINT port, REG8 va |
| REG8 IOINPCALL scrn_i(UINT port); // x1_scrn_r | REG8 IOINPCALL scrn_i(UINT port); // x1_scrn_r |
| void IOOUTCALL ply_o(UINT port, REG8 value); // x1_ply_w | void IOOUTCALL ply_o(UINT port, REG8 value); // x1_ply_w |
| REG8 IOINPCALL ply_i(UINT port); // x1_ply_r | |
| void IOOUTCALL palette_o(UINT port, REG8 value); // x1_palet_w | void IOOUTCALL palette_o(UINT port, REG8 value); // x1_palet_w |
| void IOOUTCALL blackctrl_o(UINT port, REG8 value); // x1_blackctrl_w | |
| REG8 IOINPCALL blackctrl_i(UINT port); // x1_blackctrl_r | |
| #if defined(SUPPORT_TURBOZ) | |
| REG8 IOINPCALL ply_i(UINT port); // x1_ply_r | |
| REG8 IOINPCALL palette_i(UINT port); // x1_palet_r | REG8 IOINPCALL palette_i(UINT port); // x1_palet_r |
| void IOOUTCALL extpal_o(UINT port, REG8 value); // x1_extpal_w | void IOOUTCALL extpal_o(UINT port, REG8 value); // x1_extpal_w |
| REG8 IOINPCALL extpal_i(UINT port); // x1_extpal_r | REG8 IOINPCALL extpal_i(UINT port); // x1_extpal_r |
| void IOOUTCALL extgrphpal_o(UINT port, REG8 value); // x1_extgrphpal_w | void IOOUTCALL extgrphpal_o(UINT port, REG8 value); // x1_extgrphpal_w |
| REG8 IOINPCALL extgrphpal_i(UINT port); // x1_extgrphpal_r | REG8 IOINPCALL extgrphpal_i(UINT port); // x1_extgrphpal_r |
| void IOOUTCALL exttextpal_o(UINT port, REG8 value); // x1_exttextpal_w | void IOOUTCALL exttextpal_o(UINT port, REG8 value); // x1_exttextpal_w |
| REG8 IOINPCALL exttextpal_i(UINT port); // x1_exttextpal_r | REG8 IOINPCALL exttextpal_i(UINT port); // x1_exttextpal_r |
| void IOOUTCALL exttextdisp_o(UINT port, REG8 value); // x1_exttextdisp_w | void IOOUTCALL exttextdisp_o(UINT port, REG8 value); // x1_exttextdisp_w |
| REG8 IOINPCALL exttextdisp_i(UINT port); // x1_exttextdisp_r | REG8 IOINPCALL exttextdisp_i(UINT port); // x1_exttextdisp_r |
| #endif | |
| void IOOUTCALL blackctrl_o(UINT port, REG8 value); // x1_blackctrl_w | |
| REG8 IOINPCALL blackctrl_i(UINT port); // x1_blackctrl_r | |
| #if defined(SUPPORT_TURBOZ) | |
| void crtc_initialize(void); | void crtc_initialize(void); |
| #else | |
| #define crtc_initialize() | |
| #endif | |
| void crtc_reset(void); | void crtc_reset(void); |
| void crtc_forcesetwidth(REG8 width); | void crtc_forcesetwidth(REG8 width); |