|
|
| version 1.16, 2004/08/18 08:08:13 | version 1.17, 2005/02/04 06:42:11 |
|---|---|
| Line 1 | Line 1 |
| // #define CTCCOUNTER | |
| #define CTCFAST | |
| #include "compiler.h" | #include "compiler.h" |
| #include "z80core.h" | #include "z80core.h" |
| #include "pccore.h" | #include "pccore.h" |
| Line 6 | Line 10 |
| #include "ievent.h" | #include "ievent.h" |
| #if defined(TRACE) && defined(CTCCOUNTER) | |
| extern UINT ctccnt; | |
| #endif | |
| static SINT32 minclock(const CTCCH *ch) { | static SINT32 minclock(const CTCCH *ch) { |
| UINT32 event; | UINT32 event; |
| Line 42 static REG8 ctcwork(CTCCH *ch) { | Line 50 static REG8 ctcwork(CTCCH *ch) { |
| SINT32 pulse; | SINT32 pulse; |
| SINT32 count; | SINT32 count; |
| #if defined(TRACE) && defined(CTCCOUNTER) | |
| ctccnt++; | |
| #endif | |
| baseclock = CPU_CLOCK + CPU_BASECLOCK - CPU_REMCLOCK; | baseclock = CPU_CLOCK + CPU_BASECLOCK - CPU_REMCLOCK; |
| stepclock = baseclock - ch->s.baseclock; | stepclock = baseclock - ch->s.baseclock; |
| #if defined(FIX_Z80A) // 2x2MHz | |
| ch->s.baseclock += stepclock & (~1); | |
| stepclock = stepclock >> 1; | |
| #else | |
| stepclock /= pccore.multiple; | stepclock /= pccore.multiple; |
| ch->s.baseclock += stepclock * pccore.multiple; | ch->s.baseclock += stepclock * pccore.multiple; |
| #endif | |
| intr = 0; | intr = 0; |
| pulse3 = 0; | pulse3 = 0; |
| Line 56 static REG8 ctcwork(CTCCH *ch) { | Line 73 static REG8 ctcwork(CTCCH *ch) { |
| count = ch->s.count[0]; | count = ch->s.count[0]; |
| count -= pulse; | count -= pulse; |
| if (count <= 0) { | if (count <= 0) { |
| #if defined(CTCFAST) | |
| count += ch->s.countmax[0]; | |
| if (count <= 0) { | |
| pulse3 = (0 - count) / ch->s.countmax[0]; | |
| pulse3 += 1; | |
| count += pulse3 * ch->s.countmax[0]; | |
| } | |
| pulse3 += 1; | |
| #else | |
| pulse3 = (0 - count) / ch->s.countmax[0]; | pulse3 = (0 - count) / ch->s.countmax[0]; |
| pulse3 += 1; | pulse3 += 1; |
| count += pulse3 * ch->s.countmax[0]; | count += pulse3 * ch->s.countmax[0]; |
| #endif | |
| intr |= (ch->s.cmd[0] & 0x80) >> (7 - 0); | intr |= (ch->s.cmd[0] & 0x80) >> (7 - 0); |
| } | } |
| ch->s.count[0] = count; | ch->s.count[0] = count; |
| Line 72 static REG8 ctcwork(CTCCH *ch) { | Line 99 static REG8 ctcwork(CTCCH *ch) { |
| count = ch->s.count[3]; | count = ch->s.count[3]; |
| count -= pulse3; | count -= pulse3; |
| if (count <= 0) { | if (count <= 0) { |
| #if defined(CTCFAST) | |
| count += ch->s.countmax[3]; | |
| if (count <= 0) { | |
| count = ch->s.countmax[3] - ((0 - count) % ch->s.countmax[3]); | |
| } | |
| #else | |
| count = ch->s.countmax[3] - ((0 - count) % ch->s.countmax[3]); | count = ch->s.countmax[3] - ((0 - count) % ch->s.countmax[3]); |
| #endif | |
| intr |= (ch->s.cmd[3] & 0x80) >> (7 - 3); | intr |= (ch->s.cmd[3] & 0x80) >> (7 - 3); |
| // TRACEOUT(("<- ch.3 %.8x [%.2x:%.2x %.2x:%.2x]", baseclock, | |
| // ch->s.basecnt[0], ch->s.cmd[0], | |
| // ch->s.basecnt[3], ch->s.cmd[3])); | |
| } | } |
| ch->s.count[3] = count; | ch->s.count[3] = count; |
| } | } |
| Line 122 static void ctcnextevent(CTCCH *ch) { | Line 159 static void ctcnextevent(CTCCH *ch) { |
| if (ch->s.intr) { | if (ch->s.intr) { |
| return; | return; |
| } | } |
| #if defined(FIX_Z80A) | |
| event = minclock(ch) * 2; | |
| #else | |
| event = minclock(ch) * pccore.multiple; | event = minclock(ch) * pccore.multiple; |
| #endif | |
| nevent_set(NEVENT_CTC0 + ch->s.num, event, neitem_ctc, NEVENT_ABSOLUTE); | nevent_set(NEVENT_CTC0 + ch->s.num, event, neitem_ctc, NEVENT_ABSOLUTE); |
| } | } |
| Line 280 void IOOUTCALL ctc_o(UINT port, REG8 val | Line 321 void IOOUTCALL ctc_o(UINT port, REG8 val |
| CTCCH *ch; | CTCCH *ch; |
| TRACEOUT(("ctc - %.4x %.2x [%.4x]", port, value, Z80_PC)); | // TRACEOUT(("ctc - %.4x %.2x [%.4x]", port, value, Z80_PC)); |
| ch = getctcch(port); | ch = getctcch(port); |
| if (ch != NULL) { | if (ch != NULL) { |
| ctcch_o(ch, port, value); | ctcch_o(ch, port, value); |