xmil/io/dmac.c - diff

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Diff for /xmil/io/dmac.c between versions 1.1 and 1.4

version 1.1, 2004/08/01 05:31:30	version 1.4, 2004/08/11 16:09:04
Line 1	Line 1
#include "compiler.h"	#include "compiler.h"
	#include "z80core.h"
#include "pccore.h"	#include "pccore.h"
#include "iocore.h"	#include "iocore.h"
#include "x1_io.h"	#include "nevent.h"
#include "x1_fdc.h"	#include "ievent.h"


	static REG8 iswork(const DMAC *d) {

	REG8 r;

	r = d->cmd;
	if ((r & 3) == 0) return(FALSE);
	if (d->enable == 0) return(FALSE);
	if (d->ENDB_FLG != 0) return(FALSE); // mod
	if (r & 2) {
	if (d->MACH_FLG != 0) return(FALSE); // mod
	}
	if (d->mode != 1) {
	if ((d->WR[5] ^ d->ready) & 8) return(FALSE);
	}
	return(TRUE);
	}

	void dmac_sendready(BRESULT ready) {

	REG8 working;

	if (!ready) {
	dma.working = FALSE;
	dma.ready = 8;
	}
	else {
	dma.ready = 0;
	working = iswork(&dma);
	if (dma.working != working) {
	dma.working = working;
	nevent_forceexit();
	}
	}
	}

	BRESULT ieitem_dmac(UINT id) {

	REG8 vect;

	if (dma.INT_ENBL) {
	vect = 0;
	if ((dma.INT_FLG & 1) && (dma.MACH_FLG)) {
	vect = 2;
	}
	else if ((dma.INT_FLG & 2) && (dma.ENDB_FLG)) {
	vect = 4;
	}
	if (vect) {
	if (dma.INT_FLG & 0x20) {
	vect += (dma.INT_VCT & 0xf9);
	}
	else {
	vect = dma.INT_VCT;
	}
	Z80_INTERRUPT(vect);
	return(TRUE);
	}
	}
	(void)id;
	return(FALSE);
	}


	// ----

static void setdmareaddat(void) {	static void setdmareaddat(void) {

UINT cnt;	UINT cnt;
Line 41 static void setdmareaddat(void) {	Line 107 static void setdmareaddat(void) {
void IOOUTCALL dmac_o(UINT port, REG8 value) {	void IOOUTCALL dmac_o(UINT port, REG8 value) {

REG8 wr;	REG8 wr;
	REG8 working;

dma.DMA_ENBL = 0;	dma.enable = 0;

if (!dma.WR_CNT) {	if (!dma.WR_CNT) {
wr = 6;	wr = 6;
Line 76 void IOOUTCALL dmac_o(UINT port, REG8 va	Line 143 void IOOUTCALL dmac_o(UINT port, REG8 va
dma.WR[wr] = value;	dma.WR[wr] = value;
switch(wr) {	switch(wr) {
case 0:	case 0:
dma.DMA_CMND = (UINT8)(value & 3);	dma.cmd = (UINT8)(value & 3);
if (value & 0x08) {	if (value & 0x08) {
dma.WR_TBL[dma.WR_CNT++] = offsetof(DMAC, ADR_A.b.l);	dma.WR_TBL[dma.WR_CNT++] = offsetof(DMAC, ADR_A.b.l);
}	}
Line 106 void IOOUTCALL dmac_o(UINT port, REG8 va	Line 173 void IOOUTCALL dmac_o(UINT port, REG8 va
dma.WR_TBL[dma.WR_CNT++] = offsetof(DMAC, MACH_BYT);	dma.WR_TBL[dma.WR_CNT++] = offsetof(DMAC, MACH_BYT);
}	}
dma.INT_ENBL = (UINT8)((value & 0x20)?1:0);	dma.INT_ENBL = (UINT8)((value & 0x20)?1:0);
dma.DMA_ENBL = (UINT8)((value & 0x40)?1:0);	dma.enable = (UINT8)((value & 0x40)?1:0);
break;	break;

case 4:	case 4:
dma.DMA_MODE = (UINT8)((dma.WR[4] >> 5) & 3);	dma.mode = (UINT8)((dma.WR[4] >> 5) & 3);
if (value & 0x04) {	if (value & 0x04) {
dma.WR_TBL[dma.WR_CNT++] = offsetof(DMAC, ADR_B.b.l);	dma.WR_TBL[dma.WR_CNT++] = offsetof(DMAC, ADR_B.b.l);
}	}
Line 125 void IOOUTCALL dmac_o(UINT port, REG8 va	Line 192 void IOOUTCALL dmac_o(UINT port, REG8 va
case 6:	case 6:
switch(value) {	switch(value) {
case 0x83: // dma disable	case 0x83: // dma disable
dma.DMA_ENBL = 0;	dma.enable = 0;
break;	break;

case 0x87: // dma enable	case 0x87: // dma enable
dma.DMA_ENBL = 1;	dma.enable = 1;
break;	break;

case 0x8b: // re-init status byte	case 0x8b: // re-init status byte
dma.MACH_FLG = dma.ENDB_FLG = 0;	dma.MACH_FLG = 0;
	dma.ENDB_FLG = 0;
break;	break;

case 0xa7: // ��˥��ȥ꡼�ɥ��	case 0xa7: // ��˥��ȥ꡼�ɥ��
Line 149 void IOOUTCALL dmac_o(UINT port, REG8 va	Line 217 void IOOUTCALL dmac_o(UINT port, REG8 va
break;	break;

case 0xb3: // force ready	case 0xb3: // force ready
dma.DMA_REDY = (dma.WR[5] & 0x08);	dma.ready = (dma.WR[5] & 0x08);
break;	break;

case 0xbb: // read mask follows	case 0xbb: // read mask follows
Line 162 void IOOUTCALL dmac_o(UINT port, REG8 va	Line 230 void IOOUTCALL dmac_o(UINT port, REG8 va
break;	break;

case 0xc3: // reset	case 0xc3: // reset
#if 1 // ��饤�� // ver0.25	// ��饤�� // ver0.25
dma.DMA_CMND = 0;	dma.cmd = 0;
dma.DMA_ENBL = 0;	dma.enable = 0;
dma.INT_ENBL = 0;	dma.INT_ENBL = 0;
#else
init_dma();
#endif
break;	break;

case 0xc7: // �ꥻ�åȥ��ߥ�A	case 0xc7: // �ꥻ�åȥ��ߥ�A
Line 176 void IOOUTCALL dmac_o(UINT port, REG8 va	Line 241 void IOOUTCALL dmac_o(UINT port, REG8 va
break;	break;

case 0xcf: // ��	case 0xcf: // ��
dma.DMA_MODE = (UINT8)((dma.WR[4] >> 5) & 3);	dma.mode = (UINT8)((dma.WR[4] >> 5) & 3);
dma.CNT_A.w = dma.ADR_A.w;	dma.CNT_A.w = dma.ADR_A.w;
dma.CNT_B.w = dma.ADR_B.w;	dma.CNT_B.w = dma.ADR_B.w;
dma.BYT_N.w = 0;	dma.BYT_N.w = 0;
dma.ENDB_FLG = 0;	dma.ENDB_FLG = 0;
dma.MACH_FLG = 0; // 0619	dma.MACH_FLG = 0; // 0619
dma.DMA_ENBL = 0;	dma.enable = 0;
break;	break;

case 0xd3: // ��ƥ��˥塼	case 0xd3: // ��ƥ��˥塼
Line 211 void IOOUTCALL dmac_o(UINT port, REG8 va	Line 276 void IOOUTCALL dmac_o(UINT port, REG8 va
dma.BYT_N.w = 0; // 0619	dma.BYT_N.w = 0; // 0619
dma.MACH_FLG = 0; // 0619	dma.MACH_FLG = 0; // 0619
dma.ENDB_FLG = 0;	dma.ENDB_FLG = 0;
dma.DMA_ENBL = 1;	dma.enable = 1;
break;	break;
}	}
break;	break;
Line 235 void IOOUTCALL dmac_o(UINT port, REG8 va	Line 300 void IOOUTCALL dmac_o(UINT port, REG8 va
dma.WR_OFF++;	dma.WR_OFF++;
dma.WR_CNT--;	dma.WR_CNT--;
}	}

	working = iswork(&dma);
	if (dma.working != working) {
	dma.working = working;
	if (working) {
	nevent_forceexit();
	}
	}
	(void)port;
}	}

REG8 IOINPCALL dmac_i(UINT port) {	REG8 IOINPCALL dmac_i(UINT port) {
Line 242 REG8 IOINPCALL dmac_i(UINT port) {	Line 316 REG8 IOINPCALL dmac_i(UINT port) {
REG8 ret;	REG8 ret;

ret = 0xcc;	ret = 0xcc;
if (dma.DMA_ENBL) {	if (dma.enable) {
ret \|= 0x01;	ret \|= 0x01;
}	}
if ((dma.DMA_MODE != 1) && ((dma.WR[5] ^ dma.DMA_REDY) & 8)) {	if ((dma.mode != 1) && ((dma.WR[5] ^ dma.ready) & 8)) {
ret \|= 0x02;	ret \|= 0x02;
}	}
if (!dma.MACH_FLG) {	if (!dma.MACH_FLG) {
Line 261 REG8 IOINPCALL dmac_i(UINT port) {	Line 335 REG8 IOINPCALL dmac_i(UINT port) {
}	}
ret = ((((UINT8 )&dma) + dma.RR_TBL[dma.RR_OFF++]));	ret = ((((UINT8 )&dma) + dma.RR_TBL[dma.RR_OFF++]));
}	}
	(void)port;
return(ret);	return(ret);
}	}

Line 270 REG8 IOINPCALL dmac_i(UINT port) {	Line 345 REG8 IOINPCALL dmac_i(UINT port) {
void dmac_reset(void) {	void dmac_reset(void) {

ZeroMemory(&dma, sizeof(dma));	ZeroMemory(&dma, sizeof(dma));
dma.DMA_REDY = 8;	dma.ready = 8;
dma.RR = 0x38;	dma.RR = 0x38;
}	}

RetroPC.NET-CVS <cvs@retropc.net>

Removed from v.1.1
changed lines
	Added in v.1.4