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| version 1.6, 2005/02/04 06:42:11 | version 1.7, 2008/06/02 20:07:31 |
|---|---|
| Line 93 BRESULT ieitem_dmac(UINT id) { | Line 93 BRESULT ieitem_dmac(UINT id) { |
| } | } |
| // ---- | /* ---- */ |
| static void setdmareaddat(DMAC *d) { | static void setdmareaddat(DMAC *d) { |
| Line 132 void IOOUTCALL dmac_o(UINT port, REG8 va | Line 132 void IOOUTCALL dmac_o(UINT port, REG8 va |
| REG8 working; | REG8 working; |
| TRACEOUT(("out %.4x %.2x", port, value)); | /* TRACEOUT(("out %.4x %.2x", port, value)); */ |
| dma.enable = 0; | dma.enable = 0; |
| if (!dma.wcnt) { | if (!dma.wcnt) { |
| // dma.wcnt = 0; | /* dma.wcnt = 0; */ |
| dma.wptr = 0; | dma.wptr = 0; |
| if (!(value & 0x80)) { | if (!(value & 0x80)) { |
| if ((value & 3) != 0) { | if ((value & 3) != 0) { |
| Line 171 void IOOUTCALL dmac_o(UINT port, REG8 va | Line 171 void IOOUTCALL dmac_o(UINT port, REG8 va |
| REG8 cmd; | REG8 cmd; |
| cmd = value & 3; | cmd = value & 3; |
| if (cmd == 0) { | if (cmd == 0) { |
| // dma.WR3 = value; | /* dma.WR3 = value; */ |
| if (value & 0x08) { | if (value & 0x08) { |
| dma.wtbl[dma.wcnt++] = offsetof(DMAC, MASK_BYT); | dma.wtbl[dma.wcnt++] = offsetof(DMAC, MASK_BYT); |
| } | } |
| Line 211 void IOOUTCALL dmac_o(UINT port, REG8 va | Line 211 void IOOUTCALL dmac_o(UINT port, REG8 va |
| #endif | #endif |
| else if (cmd == 3) { | else if (cmd == 3) { |
| switch(DMACMD(value)) { | switch(DMACMD(value)) { |
| case DMACMD(0x83): // dma disable | case DMACMD(0x83): /* dma disable */ |
| // dma.enable = 0; | /* dma.enable = 0; */ |
| break; | break; |
| case DMACMD(0x87): // dma enable | case DMACMD(0x87): /* dma enable */ |
| #if !defined(DMAS_STOIC) | #if !defined(DMAS_STOIC) |
| dma.increment = 0; | dma.increment = 0; |
| #else | #else |
| Line 224 void IOOUTCALL dmac_o(UINT port, REG8 va | Line 224 void IOOUTCALL dmac_o(UINT port, REG8 va |
| dma.enable = 1; | dma.enable = 1; |
| break; | break; |
| case DMACMD(0x8b): // re-init status byte | case DMACMD(0x8b): /* re-init status byte */ |
| #if !defined(DMAS_STOIC) | #if !defined(DMAS_STOIC) |
| dma.MACH_FLG = 0; | dma.MACH_FLG = 0; |
| dma.ENDB_FLG = 0; | dma.ENDB_FLG = 0; |
| Line 233 void IOOUTCALL dmac_o(UINT port, REG8 va | Line 233 void IOOUTCALL dmac_o(UINT port, REG8 va |
| #endif | #endif |
| break; | break; |
| case DMACMD(0xa7): // イニシエイトリードシーケンス | case DMACMD(0xa7): /* イニシエイトリードシーケンス */ |
| setdmareaddat(&dma); | setdmareaddat(&dma); |
| break; | break; |
| case DMACMD(0xab): // interrupt enable | case DMACMD(0xab): /* interrupt enable */ |
| dma.INT_ENBL = 1; | dma.INT_ENBL = 1; |
| break; | break; |
| case DMACMD(0xaf): // interrupt disable | case DMACMD(0xaf): /* interrupt disable */ |
| dma.INT_ENBL = 0; | dma.INT_ENBL = 0; |
| break; | break; |
| case DMACMD(0xb3): // force ready | case DMACMD(0xb3): /* force ready */ |
| dma.ready = (dma.WR5 & 0x08); | dma.ready = (dma.WR5 & 0x08); |
| break; | break; |
| case DMACMD(0xbb): // read mask follows | case DMACMD(0xbb): /* read mask follows */ |
| dma.wtbl[dma.wcnt++] = offsetof(DMAC, RR_MSK); | dma.wtbl[dma.wcnt++] = offsetof(DMAC, RR_MSK); |
| break; | break; |
| case DMACMD(0xbf): // read status byte | case DMACMD(0xbf): /* read status byte */ |
| dma.RR_MSK = 1; | dma.RR_MSK = 1; |
| setdmareaddat(&dma); | setdmareaddat(&dma); |
| break; | break; |
| case DMACMD(0xc3): // reset | case DMACMD(0xc3): /* reset */ |
| // ローグアライアンス // ver0.25 | /* ローグアライアンス */ /* ver0.25 */ |
| dma.WR0 &= ~3; // 0でいいと思うケド… | dma.WR0 &= ~3; /* 0でいいと思うケド… */ |
| #if !defined(DMAS_STOIC) | #if !defined(DMAS_STOIC) |
| dma.increment = 0; | dma.increment = 0; |
| #else | #else |
| dma.flag &= ~DMAF_INCREMENT; | dma.flag &= ~DMAF_INCREMENT; |
| #endif | #endif |
| // dma.enable = 0; | /* dma.enable = 0; */ |
| dma.INT_ENBL = 0; | dma.INT_ENBL = 0; |
| break; | break; |
| case DMACMD(0xc7): // リセットタイミングA | case DMACMD(0xc7): /* リセットタイミングA */ |
| case DMACMD(0xcb): // リセットタイミングB | case DMACMD(0xcb): /* リセットタイミングB */ |
| break; | break; |
| case DMACMD(0xcf): // ロード | case DMACMD(0xcf): /* ロード */ |
| // dma.mode = (UINT8)((dma.WR4 >> 5) & 3); | /* dma.mode = (UINT8)((dma.WR4 >> 5) & 3); */ |
| dma.cnt_a.w.addr = dma.addr.w.a; | dma.cnt_a.w.addr = dma.addr.w.a; |
| dma.cnt_b.w.addr = dma.addr.w.b; | dma.cnt_b.w.addr = dma.addr.w.b; |
| dma.leng.w.n = 0; | dma.leng.w.n = 0; |
| Line 285 void IOOUTCALL dmac_o(UINT port, REG8 va | Line 285 void IOOUTCALL dmac_o(UINT port, REG8 va |
| #else | #else |
| dma.flag |= DMAF_MACH | DMAF_ENDB; | dma.flag |= DMAF_MACH | DMAF_ENDB; |
| #endif | #endif |
| // dma.enable = 0; | /* dma.enable = 0; */ |
| break; | break; |
| case DMACMD(0xd3): // コンティニュー | case DMACMD(0xd3): /* コンティニュー */ |
| #if !defined(DMAS_STOIC) | #if !defined(DMAS_STOIC) |
| if (dma.increment) { | if (dma.increment) { |
| dma.increment = 0; | dma.increment = 0; |
| Line 414 REG8 IOINPCALL dmac_i(UINT port) { | Line 414 REG8 IOINPCALL dmac_i(UINT port) { |
| ret = (*(((UINT8 *)&dma) + dma.rtbl[dma.rptr++])); | ret = (*(((UINT8 *)&dma) + dma.rtbl[dma.rptr++])); |
| } | } |
| (void)port; | (void)port; |
| TRACEOUT(("inp %.4x %.2x", port, ret)); | /* TRACEOUT(("inp %.4x %.2x", port, ret)); */ |
| return(ret); | return(ret); |
| } | } |
| // ---- | /* reset */ |
| void dmac_reset(void) { | void dmac_reset(void) { |