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| version 1.15, 2004/08/14 12:16:17 | version 1.16, 2004/08/15 07:52:16 |
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| Line 167 static REG8 type2cmd(REG8 sc) { | Line 167 static REG8 type2cmd(REG8 sc) { |
| } | } |
| size = sizeof(fdc.s.buffer); | size = sizeof(fdc.s.buffer); |
| fdd = fddfile + fdc.s.drv; | fdd = fddfile + fdc.s.drv; |
| TRACEOUT(("read %.2x %d %d", fdc.s.drv, track, sc)); | // TRACEOUT(("read %.2x %d %d", fdc.s.drv, track, sc)); |
| stat = fdd->read(fdd, fdc.s.media, track, sc, p, &size); | stat = fdd->read(fdd, fdc.s.media, track, sc, p, &size); |
| if (stat & FDDSTAT_RECNFND) { | if (stat & FDDSTAT_RECNFND) { |
| size = 0; | size = 0; |
| Line 198 static REG8 type2cmd(REG8 sc) { | Line 198 static REG8 type2cmd(REG8 sc) { |
| curclock -= fdc.s.motorclock[fdc.s.drv]; | curclock -= fdc.s.motorclock[fdc.s.drv]; |
| if (curclock < (SINT32)pccore.realclock) { | if (curclock < (SINT32)pccore.realclock) { |
| nextclock = pccore.realclock - curclock; | nextclock = pccore.realclock - curclock; |
| TRACEOUT(("motor starting busy %d", nextclock)); | // TRACEOUT(("motor starting busy %d", nextclock)); |
| clock += nextclock; | clock += nextclock; |
| } | } |
| } | } |
| Line 212 static REG8 type2cmd(REG8 sc) { | Line 212 static REG8 type2cmd(REG8 sc) { |
| if (nextclock < 0) { | if (nextclock < 0) { |
| nextclock += fdc.s.loopclock; | nextclock += fdc.s.loopclock; |
| } | } |
| TRACEOUT(("wait clock -> %d [%d/%d]", nextclock, | // TRACEOUT(("wait clock -> %d [%d/%d]", nextclock, |
| LOW16(secinfo), LOW16(secinfo >> 16))); | // LOW16(secinfo), LOW16(secinfo >> 16))); |
| clock += nextclock; | clock += nextclock; |
| } | } |
| setbusy(max(clock, 500)); | setbusy(max(clock, 500)); |
| Line 244 static REG8 crccmd(void) { | Line 244 static REG8 crccmd(void) { |
| track = (fdc.s.c << 1) + fdc.s.h; | track = (fdc.s.c << 1) + fdc.s.h; |
| fdd = fddfile + fdc.s.drv; | fdd = fddfile + fdc.s.drv; |
| TRACEOUT(("fdd->crc %d %d %d", fdc.s.drv, track, fdc.s.crcnum)); | // TRACEOUT(("fdd->crc %d %d %d", fdc.s.drv, track, fdc.s.crcnum)); |
| stat = fdd->crc(fdd, fdc.s.media, track, fdc.s.crcnum, fdc.s.buffer); | stat = fdd->crc(fdd, fdc.s.media, track, fdc.s.crcnum, fdc.s.buffer); |
| if (stat & FDDSTAT_RECNFND) { | if (stat & FDDSTAT_RECNFND) { |
| fdc.s.crcnum = 0; | fdc.s.crcnum = 0; |
| Line 310 void IOOUTCALL fdc_o(UINT port, REG8 val | Line 310 void IOOUTCALL fdc_o(UINT port, REG8 val |
| if ((port & (~7)) != 0x0ff8) { | if ((port & (~7)) != 0x0ff8) { |
| return; | return; |
| } | } |
| TRACEOUT(("fdc %.4x,%.2x [%.4x]", port, value, Z80_PC)); | // TRACEOUT(("fdc %.4x,%.2x [%.4x]", port, value, Z80_PC)); |
| switch(port & 7) { | switch(port & 7) { |
| case 0: // コマンド | case 0: // コマンド |
| fdc.s.cmd = value; | fdc.s.cmd = value; |
| cmd = (REG8)(value >> 4); | cmd = (REG8)(value >> 4); |
| fdc.s.type = fdctype[cmd]; | fdc.s.type = fdctype[cmd]; |
| TRACEOUT(("fdc cmd: %.2x", value)); | // TRACEOUT(("fdc cmd: %.2x", value)); |
| if (fdc.s.bufwrite) { | if (fdc.s.bufwrite) { |
| fdc.s.stat = type2flash(); | fdc.s.stat = type2flash(); |
| } | } |
| Line 473 REG8 IOINPCALL fdc_i(UINT port) { | Line 473 REG8 IOINPCALL fdc_i(UINT port) { |
| if (!(ret & 0x02)) { | if (!(ret & 0x02)) { |
| dmac_sendready(FALSE); | dmac_sendready(FALSE); |
| } | } |
| TRACEOUT(("ret->%.2x", ret)); | // TRACEOUT(("ret->%.2x", ret)); |
| return(ret); | return(ret); |
| case 1: // トラック | case 1: // トラック |
| Line 486 REG8 IOINPCALL fdc_i(UINT port) { | Line 486 REG8 IOINPCALL fdc_i(UINT port) { |
| if (fdc.s.motor) { | if (fdc.s.motor) { |
| if (fdc.s.bufdir == FDCDIR_IN) { | if (fdc.s.bufdir == FDCDIR_IN) { |
| fdc.s.data = fdc.s.buffer[fdc.s.bufpos]; | fdc.s.data = fdc.s.buffer[fdc.s.bufpos]; |
| TRACEOUT(("read %.2x - %.2x [%.4x]", fdc.s.bufpos, fdc.s.data, Z80_PC)); | // TRACEOUT(("read %.2x - %.2x [%.4x]", fdc.s.bufpos, fdc.s.data, Z80_PC)); |
| bufposinc(); | bufposinc(); |
| } | } |
| } | } |