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| version 1.10, 2004/08/12 11:03:09 | version 1.15, 2004/08/14 12:16:17 |
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| Line 1 | Line 1 |
| #include "compiler.h" | #include "compiler.h" |
| #include "pccore.h" | #include "pccore.h" |
| #include "iocore.h" | #include "iocore.h" |
| #include "nevent.h" | |
| #include "makescrn.h" | #include "makescrn.h" |
| Line 9 | Line 10 |
| static REG8 getportb(void) { | static REG8 getportb(void) { |
| REG8 ret; | REG8 ret; |
| UINT v; | SINT32 clock; |
| ret = cmt_test(); // | cmt_read(); // THUNDER BALL | ret = cmt_test(); // | cmt_read(); // THUNDER BALL |
| v = pccore_getraster(NULL); | clock = nevent_getwork(NEVENT_FRAMES); |
| if (v < crtc.s.CRT_YL) { | if (corestat.vsync) { |
| clock += corestat.dispclock; | |
| } | |
| if (clock < crtc.e.dispclock) { | |
| ret |= 0x80; // 1:DISP | ret |= 0x80; // 1:DISP |
| } | } |
| clock -= crtc.e.vsyncstart; | |
| if ((clock >= 0) && (clock < crtc.e.vpulseclock)) { | |
| ret |= 0x04; // 1:V-SYNC | |
| } | |
| if (subcpu.IBF) { | if (subcpu.IBF) { |
| subcpu.IBF = 0; | subcpu.IBF = 0; |
| ret |= 0x40; // 1:SUB-CPU BUSY | ret |= 0x40; // 1:SUB-CPU BUSY |
| Line 27 static REG8 getportb(void) { | Line 36 static REG8 getportb(void) { |
| if (memio.ram) { | if (memio.ram) { |
| ret |= 0x10; // 1:RAM | ret |= 0x10; // 1:RAM |
| } | } |
| #if 1 | |
| if (!(v < crtc.e.vs)) { | |
| ret |= 0x04; // V-SYNC | |
| } | |
| #else // ラプラステスト…VYSNCが長すぎるらしい | |
| if (v_cnt == crtc.e.vs) { | |
| ret |= 0x04; | |
| } | |
| #endif | |
| return(ret); | return(ret); |
| } | } |
| static void setportc(REG8 dat) { | static void setportc(REG8 dat) { |
| REG8 oldc; | REG8 modify; |
| UINT8 xl; | |
| oldc = ppi.portc; | |
| if (crtc.s.TXT_XL == 40) { | |
| oldc |= 0x40; | |
| } | |
| else { | |
| oldc &= ~0x40; | |
| } | |
| ppi.portc = dat; | |
| modify = ppi.portc ^ dat; | |
| // cmt_write((REG8)(dat & 1)); | // cmt_write((REG8)(dat & 1)); |
| if ((oldc & 0x20) && (!(dat & 0x20))) { | if ((modify & 0x20) && (!(dat & 0x20))) { |
| iocore.s.mode = 1; | iocore.s.mode = 1; |
| } | } |
| if (modify & 0x40) { | |
| crtc_setwidth((REG8)(dat & 0x40)); | |
| } | |
| #if 0 | |
| xl = ((dat & 0x40)?40:80); | xl = ((dat & 0x40)?40:80); |
| if (crtc.s.TXT_XL != xl) { | if (crtc.s.reg[CRTCREG_HDISP] != xl) { |
| crtc.s.TXT_XL = (UINT8)xl; | crtc.s.reg[CRTCREG_HDISP] = (UINT8)xl; |
| // crtc.s.GRP_XL = xl << 3; | crtc_bankupdate(); |
| vrambank_patch(); | |
| scrnallflash = 1; | scrnallflash = 1; |
| } | } |
| #endif | |
| } | } |
| Line 120 REG8 IOINPCALL ppi_i(UINT port) { | Line 115 REG8 IOINPCALL ppi_i(UINT port) { |
| return(getportb()); | return(getportb()); |
| case 2: | case 2: |
| #if 1 | // mode? |
| if (crtc.s.TXT_XL == 40) { | |
| ppi.portc |= 0x40; | |
| } | |
| else { | |
| ppi.portc &= ~0x40; | |
| } | |
| #endif | |
| return(ppi.portc); | return(ppi.portc); |
| case 3: | case 3: |
| Line 144 void ppi_initialize(void) { | Line 132 void ppi_initialize(void) { |
| ppi.porta = 0x00; | ppi.porta = 0x00; |
| ppi.portb = 0xff; | ppi.portb = 0xff; |
| ppi.portc = 0xff; | ppi.portc = 0xff; |
| ppi.mode = 0x9b; | ppi.mode = 0x82; |
| } | } |
| void ppi_reset(void) { | void ppi_reset(void) { |