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| version 1.16, 2004/08/17 14:46:37 | version 1.18, 2005/02/04 06:42:11 |
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| Line 1 | Line 1 |
| #include "compiler.h" | #include "compiler.h" |
| #include "z80core.h" | |
| #include "pccore.h" | #include "pccore.h" |
| #include "iocore.h" | #include "iocore.h" |
| #include "nevent.h" | |
| #include "makescrn.h" | |
| // ---- 8255 PPI〜 | // ---- 8255 PPI〜 |
| Line 10 | Line 9 |
| static REG8 getportb(void) { | static REG8 getportb(void) { |
| REG8 ret; | REG8 ret; |
| REG8 ppib; | |
| #if defined(MAINFRAMES_OLD) | |
| SINT32 clock; | SINT32 clock; |
| #endif | |
| ret = cmt_test(); // | cmt_read(); // THUNDER BALL | // if (subcpu.IBF) { |
| // subcpu.IBF = 0; | |
| clock = nevent_getwork(NEVENT_FRAMES); | // ret |= 0x40; // 1:SUB-CPU BUSY |
| if (corestat.vsync) { | // } |
| clock += corestat.dispclock; | // if (subcpu.OBF) { |
| } | // ret |= 0x20; // 1:SUB-CPU Data empty |
| if (clock < crtc.e.dispclock) { | // } |
| ppib = iocore.s.ppib; | |
| ret = ppib; | |
| // ret |= cmt_test(); // THUNDER BALL | |
| // /* -> */ ppib |= 0x01; | |
| iocore.s.ppib = (UINT8)((ppib & (~0x40)) | 0x01); | |
| // ret |= cmt_read(); | |
| #if defined(MAINFRAMES_OLD) | |
| clock = CPU_CLOCKCOUNT - iocore.e.framestartclock; | |
| if (clock < iocore.e.dispclock) { | |
| ret |= 0x80; // 1:DISP | ret |= 0x80; // 1:DISP |
| } | } |
| clock -= crtc.e.vsyncstart; | |
| if ((clock >= 0) && (clock < crtc.e.vpulseclock)) { | |
| ret |= 0x04; // 1:V-SYNC | |
| } | |
| if (subcpu.IBF) { | // 実機の動きを見ると どうも 読み込んだらリセットされるようだ? |
| subcpu.IBF = 0; | // 有効範囲が絞れるならそうすべき(VSYNCを取りこぼすソフトがある |
| ret |= 0x40; // 1:SUB-CPU BUSY | clock -= iocore.e.vsyncstart; |
| } | if ((clock >= 0) && (clock < iocore.e.vpulseclock)) { |
| if (subcpu.OBF) { | ret |= 0x04; // 1:V-SYNC |
| ret |= 0x20; // 1:SUB-CPU Data empty | |
| } | |
| if (memio.ram) { | |
| ret |= 0x10; // 1:RAM | |
| } | } |
| #endif | |
| return(ret); | return(ret); |
| } | } |
| Line 48 static void setportc(REG8 dat) { | Line 57 static void setportc(REG8 dat) { |
| // cmt_write((REG8)(dat & 1)); | // cmt_write((REG8)(dat & 1)); |
| if ((modify & 0x20) && (!(dat & 0x20))) { | if ((modify & 0x20) && (!(dat & 0x20))) { |
| iocore.s.mode = 1; | iocore.s.mode = 1; |
| // TRACEOUT(("iocore.s.mode = 1")); | |
| } | } |
| if (modify & 0x40) { | if (modify & 0x40) { |
| crtc_setwidth((REG8)(dat & 0x40)); | crtc_setwidth((REG8)(dat & 0x40)); |
| } | } |
| #if 0 | |
| xl = ((dat & 0x40)?40:80); | |
| if (crtc.s.reg[CRTCREG_HDISP] != xl) { | |
| crtc.s.reg[CRTCREG_HDISP] = (UINT8)xl; | |
| crtc_bankupdate(); | |
| scrnallflash = 1; | |
| } | |
| #endif | |
| } | } |