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| version 1.1, 2004/08/01 05:31:30 | version 1.7, 2004/08/08 15:14:08 |
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| Line 1 | Line 1 |
| #include "compiler.h" | #include "compiler.h" |
| #include "pccore.h" | #include "pccore.h" |
| #include "iocore.h" | #include "iocore.h" |
| #include "x1_io.h" | #include "makescrn.h" |
| #include "x1_crtc.h" | |
| #include "x1_vram.h" | |
| #include "draw.h" | |
| // ---- 8255 PPI〜 | // ---- 8255 PPI〜 |
| Line 15 void IOOUTCALL ppi_o(UINT port, REG8 val | Line 12 void IOOUTCALL ppi_o(UINT port, REG8 val |
| UINT8 bit; | UINT8 bit; |
| UINT8 xl; | UINT8 xl; |
| if (crtc.TXT_XL == 40) { | if (crtc.s.TXT_XL == 40) { |
| ppi.PORT_C |= 0x40; | ppi.PORT_C |= 0x40; |
| } | } |
| else { | else { |
| Line 69 void IOOUTCALL ppi_o(UINT port, REG8 val | Line 66 void IOOUTCALL ppi_o(UINT port, REG8 val |
| // cmt_write(ppi.PORT_C & 1); | // cmt_write(ppi.PORT_C & 1); |
| if ((bak_c & 0x20) && (!(ppi.PORT_C & 0x20))) { | if ((bak_c & 0x20) && (!(ppi.PORT_C & 0x20))) { |
| ppi.IO_MODE = 1; | iocore.s.mode = 1; |
| } | } |
| xl = ((ppi.PORT_C & 0x40)?40:80); | xl = ((ppi.PORT_C & 0x40)?40:80); |
| if (crtc.TXT_XL != xl) { | if (crtc.s.TXT_XL != xl) { |
| crtc.TXT_XL = (UINT8)xl; | crtc.s.TXT_XL = (UINT8)xl; |
| crtc.GRP_XL = xl << 3; | crtc.s.GRP_XL = xl << 3; |
| vrambank_patch(); | vrambank_patch(); |
| scrnallflash = 1; | scrnallflash = 1; |
| } | } |
| Line 84 REG8 IOINPCALL ppi_i(UINT port) { | Line 81 REG8 IOINPCALL ppi_i(UINT port) { |
| ppi.PORT_B = cmt_test(); // | cmt_read(); // THUNDER BALL | ppi.PORT_B = cmt_test(); // | cmt_read(); // THUNDER BALL |
| if (v_cnt < crtc.CRT_YL) { | if (v_cnt < crtc.s.CRT_YL) { |
| ppi.PORT_B |= 0x80; // 1:DISP | ppi.PORT_B |= 0x80; // 1:DISP |
| } | } |
| if (subcpu.IBF) { | if (subcpu.IBF) { |
| Line 94 REG8 IOINPCALL ppi_i(UINT port) { | Line 91 REG8 IOINPCALL ppi_i(UINT port) { |
| if (subcpu.OBF) { | if (subcpu.OBF) { |
| ppi.PORT_B |= 0x20; // 1:SUB-CPU Data empty | ppi.PORT_B |= 0x20; // 1:SUB-CPU Data empty |
| } | } |
| if (!pccore.ROM_SW) { | if (memio.ram) { |
| ppi.PORT_B |= 0x10; // 1:RAM | ppi.PORT_B |= 0x10; // 1:RAM |
| } | } |
| if (!(v_cnt < crtc.CRT_VS)) { | #if 1 |
| if (!(v_cnt < crtc.s.CRT_VS)) { | |
| ppi.PORT_B |= 0x04; // V-SYNC | ppi.PORT_B |= 0x04; // V-SYNC |
| } | } |
| if (crtc.TXT_XL == 40) { | #else // ラプラステスト…VYSNCが長すぎるらしい |
| if (v_cnt == crtc.s.CRT_VS) { | |
| ppi.PORT_B |= 0x04; | |
| } | |
| #endif | |
| if (crtc.s.TXT_XL == 40) { | |
| ppi.PORT_C |= 0x40; | ppi.PORT_C |= 0x40; |
| } | } |
| else { | else { |
| Line 131 void ppi_initialize(void) { | Line 134 void ppi_initialize(void) { |
| ppi.PORT_B = 0xff; | ppi.PORT_B = 0xff; |
| ppi.PORT_C = 0xff; | ppi.PORT_C = 0xff; |
| ppi.MODE = 0; | ppi.MODE = 0; |
| ppi.IO_MODE = 0; | |
| } | } |
| void ppi_reset(void) { | void ppi_reset(void) { |
| Line 139 void ppi_reset(void) { | Line 141 void ppi_reset(void) { |
| ppi.MODE = 0; | ppi.MODE = 0; |
| ppi.PORT_A = 0; | ppi.PORT_A = 0; |
| ppi.PORT_C |= 0x40; | ppi.PORT_C |= 0x40; |
| ppi.IO_MODE = 0; | |
| } | } |