--- xmil/io/ppi.c	2004/08/17 14:46:37	1.16
+++ xmil/io/ppi.c	2008/06/02 20:07:31	1.19
@@ -1,41 +1,51 @@
 #include	"compiler.h"
+#include	"z80core.h"
 #include	"pccore.h"
 #include	"iocore.h"
-#include	"nevent.h"
-#include	"makescrn.h"
 
 
-// ---- 8255 PPI〜
+/* 8255 PPI〜 */
 
 static REG8 getportb(void) {
 
 	REG8	ret;
+	REG8	ppib;
+#if defined(MAINFRAMES_OLD)
 	SINT32	clock;
+#endif
 
-	ret = cmt_test(); // | cmt_read();		// THUNDER BALL
-
-	clock = nevent_getwork(NEVENT_FRAMES);
-	if (corestat.vsync) {
-		clock += corestat.dispclock;
-	}
-	if (clock < crtc.e.dispclock) {
-		ret |= 0x80;						// 1:DISP
-	}
-	clock -= crtc.e.vsyncstart;
-	if ((clock >= 0) && (clock < crtc.e.vpulseclock)) {
-		ret |= 0x04;						// 1:V-SYNC
-	}
-
+#if 0
 	if (subcpu.IBF) {
 		subcpu.IBF = 0;
-		ret |= 0x40;						// 1:SUB-CPU BUSY
+		ret |= 0x40;						/* 1:SUB-CPU BUSY */
 	}
 	if (subcpu.OBF) {
-		ret |= 0x20;						// 1:SUB-CPU Data empty
+		ret |= 0x20;						/* 1:SUB-CPU Data empty */
+	}
+#endif	/* 0 */
+
+	ppib = iocore.s.ppib;
+	ret = ppib;
+
+	/* ret |= cmt_test(); */				/* THUNDER BALL */
+
+	iocore.s.ppib = (UINT8)((ppib & (~0x40)) | 0x01);
+
+	/* ret |= cmt_read(); */
+
+#if defined(MAINFRAMES_OLD)
+	clock = CPU_CLOCKCOUNT - iocore.e.framestartclock;
+	if (clock < iocore.e.dispclock) {
+		ret |= 0x80;						/* 1:DISP */
 	}
-	if (memio.ram) {
-		ret |= 0x10;						// 1:RAM
+
+	/* 実機の動きを見ると　どうも 読み込んだらリセットされるようだ？ */
+	/* 有効範囲が絞れるならそうすべき(VSYNCを取りこぼすソフトがある) */
+	clock -= iocore.e.vsyncstart;
+	if ((clock >= 0) && (clock < iocore.e.vpulseclock)) {
+		ret |= 0x04;						/* 1:V-SYNC */
 	}
+#endif
 	return(ret);
 }
 
@@ -45,25 +55,18 @@ static void setportc(REG8 dat) {
 
 	modify = ppi.portc ^ dat;
 	ppi.portc = dat;
-//	cmt_write((REG8)(dat & 1));
+	/* cmt_write((REG8)(dat & 1)); */
 	if ((modify & 0x20) && (!(dat & 0x20))) {
 		iocore.s.mode = 1;
+		/* TRACEOUT(("iocore.s.mode = 1")); */
 	}
 	if (modify & 0x40) {
 		crtc_setwidth((REG8)(dat & 0x40));
 	}
-#if 0
-	xl = ((dat & 0x40)?40:80);
-	if (crtc.s.reg[CRTCREG_HDISP] != xl) {
-		crtc.s.reg[CRTCREG_HDISP] = (UINT8)xl;
-		crtc_bankupdate();
-		scrnallflash = 1;
-	}
-#endif
 }
 
 
-// ----
+/* ---- */
 
 void IOOUTCALL ppi_o(UINT port, REG8 value) {
 
@@ -104,9 +107,11 @@ REG8 IOINPCALL ppi_i(UINT port) {
 
 	switch(port & 0x0f) {
 		case 0:
-		//	if (!(ppi.mode & 0x10)) {
-		//		return(ppi.porta);
-		//	}
+#if 0
+			if (!(ppi.mode & 0x10)) {
+				return(ppi.porta);
+			}
+#endif	/* 0 */
 			return(ppi.porta);
 
 		case 1:
@@ -116,7 +121,7 @@ REG8 IOINPCALL ppi_i(UINT port) {
 			return(getportb());
 
 		case 2:
-		// mode?
+			/* mode? */
 			return(ppi.portc);
 
 		case 3:
@@ -126,7 +131,7 @@ REG8 IOINPCALL ppi_i(UINT port) {
 }
 
 
-// ----
+/* initialize & reset */
 
 void ppi_initialize(void) {