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| version 1.13, 2004/08/07 12:10:27 | version 1.18, 2004/08/09 02:47:01 |
|---|---|
| Line 22 | Line 22 |
| const OEMCHAR xmilversion[] = OEMTEXT(XMILVER_CORE); | const OEMCHAR xmilversion[] = OEMTEXT(XMILVER_CORE); |
| XMILCFG xmilcfg = { 0, 0, 1, | XMILCFG xmilcfg = { 2, 0, 1, |
| 2, 0, 1, | 1, 0, 0, 0, |
| 22050, 1000, 0, 80, | 22050, 500, 0, 0, 80, |
| 0, 0, | 0, 0, 0, 0}; |
| 0, 0, | |
| 0, 0, 0, | |
| 1, 0}; | |
| PCCORE pccore = {250, 0, 1, 0}; | PCCORE pccore = {250, 0, 1, 0}; |
| CORESTAT corestat; | CORESTAT corestat; |
| BYTE mMAIN[0x10000]; | BYTE mMAIN[0x10000]; |
| BYTE mBIOS[0x8000]; | BYTE mBIOS[0x8000]; |
| BYTE mBANK[16][0x8000]; | #if defined(SUPPORT_BANKMEM) |
| WORD v_cnt; | UINT8 mBANK[16][0x8000]; |
| int s_cnt; | #endif |
| UINT v_cnt; | |
| UINT s_cnt; | |
| BYTE *RAM0r; | BYTE *RAM0r; |
| BYTE *RAM0w; | BYTE *RAM0w; |
| Line 48 const OEMCHAR xmilversion[] = OEMTEXT(XM | Line 47 const OEMCHAR xmilversion[] = OEMTEXT(XM |
| IPL-ROM LOAD | IPL-ROM LOAD |
| ***********************************************************************/ | ***********************************************************************/ |
| void ipl_load(void) { | static void ipl_load(void) { |
| FILEH hdl; | FILEH hdl; |
| Line 141 void pccore_initialize(void) { | Line 140 void pccore_initialize(void) { |
| crtc_initialize(); | crtc_initialize(); |
| pcg_initialize(); | pcg_initialize(); |
| ppi_initialize(); | ppi_initialize(); |
| // reset_x1(xmilcfg.ROM_TYPE, xmilcfg.SOUND_SW, xmilcfg.DIP_SW); | |
| // keystat_initialize(); | |
| // keystat_reset(); | |
| } | } |
| void pccore_reset(void) { | void pccore_reset(void) { |
| Line 213 void pccore_exec(BRESULT draw) { | Line 207 void pccore_exec(BRESULT draw) { |
| REG8 inttiming; | REG8 inttiming; |
| corestat.drawframe = draw; | corestat.drawframe = draw; |
| soundmng_sync(); | |
| v_cnt = 0; | v_cnt = 0; |
| s_cnt = 0; | s_cnt = 0; |
| Line 220 void pccore_exec(BRESULT draw) { | Line 215 void pccore_exec(BRESULT draw) { |
| while(s_cnt < 266) { | while(s_cnt < 266) { |
| while(h_cnt < pccore.HSYNC_CLK) { | while(h_cnt < pccore.HSYNC_CLK) { |
| #if IPTRACE | #if defined(TRACE) && IPTRACE |
| treip[trpos & (IPTRACE - 1)] = Z80_PC; | treip[trpos & (IPTRACE - 1)] = Z80_PC; |
| trpos++; | trpos++; |
| #endif | #endif |
| Line 252 void pccore_exec(BRESULT draw) { | Line 247 void pccore_exec(BRESULT draw) { |
| } | } |
| } | } |
| } | } |
| sound_sync(); | |
| calendar_inc(); | |
| scrnupdate(); | scrnupdate(); |
| calendar_inc(); | |
| sound_sync(); | |
| } | } |