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| version 1.34, 2004/08/20 12:09:20 | version 1.35, 2004/08/20 23:01:13 |
|---|---|
| Line 31 const OEMCHAR xmilversion[] = OEMTEXT(XM | Line 31 const OEMCHAR xmilversion[] = OEMTEXT(XM |
| PCCORE pccore; | PCCORE pccore; |
| CORESTAT corestat; | CORESTAT corestat; |
| UINT8 mMAIN[0x10000]; | |
| UINT8 mBIOS[0x8000]; | |
| #if defined(SUPPORT_BANKMEM) | |
| UINT8 mBANK[16][0x8000]; | |
| #endif | |
| UINT8 *RAM0r; | |
| UINT8 *RAM0w; | |
| // ---- | // ---- |
| Line 46 static void ipl_load(void) { | Line 39 static void ipl_load(void) { |
| FILEH hdl; | FILEH hdl; |
| ZeroMemory(mBIOS, sizeof(mBIOS)); | ZeroMemory(biosmem, 0x8000); |
| CopyMemory(mBIOS, DEFROM, sizeof(DEFROM)); | CopyMemory(biosmem, DEFROM, sizeof(DEFROM)); |
| if (pccore.ROM_TYPE >= 2) { | if (pccore.ROM_TYPE >= 2) { |
| if ((hdl = file_open_c(OEMTEXT("IPLROM.X1T"))) != FILEH_INVALID) { | if ((hdl = file_open_c(OEMTEXT("IPLROM.X1T"))) != FILEH_INVALID) { |
| file_read(hdl, mBIOS, 0x8000); | file_read(hdl, biosmem, 0x8000); |
| file_close(hdl); | file_close(hdl); |
| } | } |
| } | } |
| else if (pccore.ROM_TYPE == 1) { | else if (pccore.ROM_TYPE == 1) { |
| if ((hdl = file_open_c(OEMTEXT("IPLROM.X1"))) != FILEH_INVALID) { | if ((hdl = file_open_c(OEMTEXT("IPLROM.X1"))) != FILEH_INVALID) { |
| file_read(hdl, mBIOS, 0x8000); | file_read(hdl, biosmem, 0x8000); |
| file_close(hdl); | file_close(hdl); |
| } | } |
| } | } |
| Line 68 static void ipl_load(void) { | Line 61 static void ipl_load(void) { |
| void pccore_initialize(void) { | void pccore_initialize(void) { |
| Z80_INITIALIZE(); | |
| fddfile_initialize(); | fddfile_initialize(); |
| sndctrl_initialize(); | sndctrl_initialize(); |
| makescrn_initialize(); | makescrn_initialize(); |
| Line 129 void pccore_reset(void) { | Line 123 void pccore_reset(void) { |
| ipl_load(); | ipl_load(); |
| RAM0r = mBIOS; | |
| RAM0w = mMAIN; | |
| pal_reset(); | pal_reset(); |
| makescrn_reset(); | makescrn_reset(); |
| timing_reset(); | timing_reset(); |