--- xmil/vram/vram.h	2004/08/08 16:39:04	1.5
+++ xmil/vram/vram.h	2005/02/04 06:42:12	1.7
@@ -1,26 +1,7 @@
 
-enum {
-	GRAM_SIZE		= 0x10000,
-	GRAM_BANK0		= 0x00000,
-	GRAM_BANK1		= 0x10000,
-
-	GRAM_BANK0L		= 0x00000,
-	GRAM_BANK0H		= 0x08000,
-	GRAM_BANK1L		= 0x10000,
-	GRAM_BANK1H		= 0x18000,
-
-	GRAM_HALFSTEP	= 0x08000,
-
-	GRAM_B			= 8,
-	GRAM_R			= 16,
-	GRAM_G			= 24
-};
+// ---- TRAM
 
 enum {
-	TRAM_ANK		= 0x0000,
-	TRAM_ATR		= 0x0800,
-	TRAM_KNJ		= 0x1000,
-
 	TRAMATR_COLOR	= 0x07,
 	TRAMATR_REVERSE	= 0x08,
 	TRAMATR_BLINK	= 0x10,
@@ -38,16 +19,82 @@ enum {
 	UPDATE_TVRAM	= UPDATE_VRAM0 | UPDATE_VRAM1 | UPDATE_TRAM
 };
 
+typedef struct {
+	UINT8	ank;
+	UINT8	knj;
+	UINT8	atr;
+	UINT8	udt;
+} TRAM;
+
+
+// ---- GRAM
+
+#if !defined(VRAMSTOIC)		// メモリキャッシュ優先
+
+enum {
+	GRAM_SIZE		= 0x20000,
+	GRAM_BANK0		= 0x00000,
+	GRAM_BANK1		= 0x10000,
+
+	GRAM_BANK0L		= 0x00000,
+	GRAM_BANK0H		= 0x08000,
+	GRAM_BANK1L		= 0x10000,
+	GRAM_BANK1H		= 0x18000,
+
+	GRAM_HALFSTEP	= 0x08000,
+
+	GRAM_LINESTEP	= 0x01,
+	GRAM_B			= 0x08,
+	GRAM_R			= 0x10,
+	GRAM_G			= 0x18,
+	GRAM_RGBMASK	= 0x18
+};
+
+#define	PORT2GRAM(port)		((LOW11((port)) << 5) + ((port) >> 11))
+#define	PORT2GRAM2(port)	((((port) << 5) + ((port) >> 11)) & 0xffe7)
+#define	TRAM2GRAM(addr)		((addr) << 5)
+
+#else						// メモリ並び優先
+
+enum {
+	GRAM_SIZE		= 0x18000,
+	GRAM_BANK0		= 0x00000,
+	GRAM_BANK1		= 0x0c000,
+
+	GRAM_BANK0L		= 0x00000,
+	GRAM_BANK0H		= 0x00400,
+	GRAM_BANK1L		= 0x0c000,
+	GRAM_BANK1H		= 0x0c400,
+
+	GRAM_HALFSTEP	= 0x00400,
+
+	GRAM_LINESTEP	= 0x0800,
+	GRAM_B			= 0x0000,
+	GRAM_R			= 0x4000,
+	GRAM_G			= 0x8000,
+	GRAM_RGBMASK	= 0xc000
+};
+
+#define	PORT2GRAM(port)		((port) - 0x4000)
+#define	PORT2GRAM2(port)	((port) & (~0xc000))
+#define	TRAM2GRAM(addr)		(addr)
+
+#endif
+
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-extern	UINT8	GRP_RAM[0x20000];
-extern	UINT8	tram[0x01800];
-extern	UINT8	updatetmp[0x800+0x101];
+extern	TRAM	tram[0x800];
+extern	UINT8	gram[GRAM_SIZE];
 
 #ifdef __cplusplus
 }
 #endif
 
+#define	TRAM_ANK(addr)		tram[addr].ank
+#define	TRAM_KNJ(addr)		tram[addr].knj
+#define	TRAM_ATR(addr)		tram[addr].atr
+#define	TRAMUPDATE(addr)	tram[addr].udt
+